Memory system and operating method thereof

Abstract

The embodiment of the invention provides a memory system and an operation method thereof. The memory system comprises a memory device and a memory controller coupled with the memory device; the memory device includes a plurality of memory pages, and the memory controller is configured to: send a first command instructing a read operation on data in a target memory page at a first read voltage; obtaining a first value and a second value read from the target storage page; when the threshold voltage of the storage unit is smaller than the first read voltage, the read data is a first value; when the threshold voltage of the storage unit is greater than the first read voltage, the read data is a second value; obtaining a quantity difference between the first value and the second value; and determining whether the first read voltage is the target read voltage or not according to the number difference between the first value and the second value.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a memory system and an operating method thereof. Background Art

[0002] With the rapid development of data storage technology, more and more data storage systems are appearing in electronic devices used by people, such as solid state drives (SSDs). SSDs have been widely used in military, automotive, industrial, medical and aviation fields due to their fast read and write speed, vibration resistance, low power consumption, no noise, low heat and light weight.

[0003] However, there are still many problems to be solved in the memory system in the related art.

[0004] Public Content

[0005] According to a first aspect of an embodiment of the present disclosure, a memory system is provided, the memory system comprising a memory device and a memory controller coupled to the memory device; the memory device comprises a plurality of memory pages, and the memory controller is configured to:

[0006] Sending a first command, wherein the first command instructs to perform a read operation on data in a target storage page using a first read voltage;

[0007] Acquire a first value and a second value read from the target storage page; when the threshold voltage of the storage cell is less than the first read voltage, the read data is the first value; when the threshold voltage of the storage cell is greater than the first read voltage, the read data is the second value;

[0008] Obtaining a quantitative difference between the first value and the second value;

[0009] Whether the first read voltage is a target read voltage is determined according to a quantitative difference between the first value and the second value.

[0010] In the above solution, the memory controller is configured as:

[0011] When the absolute value of the difference between the first value and the second value is greater than a preset value, determining that the first read voltage is a non-target read voltage;

[0012] When the absolute value of the quantity difference between the first value and the second value is less than or equal to the preset value, the first read voltage is determined to be the target read voltage.

[0013] In the above solution, the preset value ranges from 100 to 300.

[0014] In the above solution, each of the storage pages includes a plurality of storage units, and each of the storage units stores one bit of data.

[0015] In the above solution, the memory controller is configured as:

[0016] When the absolute value of the difference between the first value and the second value is greater than a preset value, and the number of the first value is greater than the number of the second value, sending a second command instructing to read the data in the target storage page with a second read voltage; the second read voltage is less than the first read voltage;

[0017] When the absolute value of the difference between the first value and the second value is greater than a preset value, and the number of the first value is less than the number of the second value, a third command is sent, wherein the third command instructs a read operation to be performed on the data in the target storage page with a third read voltage; the third read voltage is greater than the first read voltage.

[0018] In the above solution, the memory controller includes a register, and the memory controller is configured as follows:

[0019] temporarily storing the first value and the second value read from the target storage page in the register;

[0020] The register is used to count the number of the first value and the second value.

[0021] In the above solution, the storage page corresponds to a read voltage table, the read voltage table includes a plurality of read voltages arranged in ascending order, and the values ​​of two adjacent read voltages differ by a fixed offset;

[0022] The memory controller is configured to:

[0023] When performing a read operation on the target storage page, a read voltage in the read voltage table is selected by binary selection to perform a read operation on data in the target storage page.

[0024] In the above solution, the memory system includes a memory card or a solid state drive.

[0025] In the above solution, the memory device includes a memory array and a peripheral circuit coupled to the memory array; the peripheral circuit is configured as follows:

[0026] receiving the first command sent from the memory controller;

[0027] The first value and the second value read from the target memory page are sent to the memory controller.

[0028] According to a second aspect of an embodiment of the present disclosure, a method for operating a memory system is provided, the method comprising:

[0029] Sending a first command, wherein the first command instructs to perform a read operation on data in a target storage page using a first read voltage;

[0030] Acquire a first value and a second value read from the target storage page; when the threshold voltage of the storage cell is less than the first read voltage, the read data is the first value; when the threshold voltage of the storage cell is greater than the first read voltage, the read data is the second value;

[0031] Obtaining a quantitative difference between the first value and the second value;

[0032] Whether the first read voltage is a target read voltage is determined according to a quantitative difference between the first value and the second value.

[0033] In the above solution, determining whether the first read voltage is a target read voltage according to the difference between the first value and the second value includes:

[0034] When the absolute value of the difference between the first value and the second value is greater than a preset value, determining that the first read voltage is a non-target read voltage;

[0035] When the absolute value of the quantity difference between the first value and the second value is less than or equal to the preset value, the first read voltage is determined to be the target read voltage.

[0036] In the above solution, the preset value ranges from 100 to 300.

[0037] In the above scheme, the method further comprises:

[0038] When the absolute value of the difference between the first value and the second value is greater than a preset value, and the number of the first value is greater than the number of the second value, sending a second command instructing to read the data in the target storage page with a second read voltage; the second read voltage is less than the first read voltage;

[0039] When the absolute value of the difference between the first value and the second value is greater than a preset value, and the number of the first value is less than the number of the second value, a third command is sent, wherein the third command instructs a read operation to be performed on the data in the target storage page with a third read voltage; the third read voltage is greater than the first read voltage.

[0040] In the above solution, the step of obtaining the first value and the second value read from the target storage page and obtaining the quantitative difference between the first value and the second value includes:

[0041] temporarily storing the first value and the second value read from the target storage page in a register in a memory controller;

[0042] The register is used to count the number of the first value and the second value.

[0043] In the above solution, the storage page corresponds to a read voltage table, the read voltage table includes a plurality of read voltages arranged in ascending order, and the values ​​of two adjacent read voltages differ by a fixed offset;

[0044] The method further comprises:

[0045] When performing a read operation on the target storage page, a read voltage in the read voltage table is selected by binary selection to perform a read operation on data in the target storage page.

[0046] In the above scheme, the operation method further includes:

[0047] receiving the first command sent from a memory controller of the memory system;

[0048] The first value and the second value read from the target memory page are sent to the memory controller.

[0049] The disclosed embodiment provides an operation method of a memory system, the method comprising: sending a first command, the first command instructing to read data in a target storage page with a first read voltage; obtaining a first value and a second value read from the target storage page; when the threshold voltage of a storage cell is less than the first read voltage, the read data is the first value; when the threshold voltage of a storage cell is greater than the first read voltage, the read data is the second value; obtaining the quantitative difference between the first value and the second value; and determining whether the first read voltage is a target read voltage according to the quantitative difference between the first value and the second value. In the disclosed embodiment, after performing a read operation on the target storage page with the first read voltage, determining whether the first read voltage is a target read voltage according to the quantitative difference between the first value and the second value can quickly, efficiently and accurately determine the position of the target voltage, thereby improving the error correction capability of the low-density parity check code and improving the reading efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0051] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0052] Figure 2bA schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0053] Figure 3a A schematic diagram of the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0054] Figure 3b is a schematic diagram of an exemplary memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0055] Figure 4 is a cross-sectional schematic diagram of a memory array including memory strings according to an embodiment of the present disclosure;

[0056] Figure 5 A schematic diagram of an exemplary memory including a memory array and a peripheral circuit according to an embodiment of the present disclosure;

[0057] Figure 6 A schematic diagram of the framework structure of a memory system according to an embodiment of the present disclosure;

[0058] Figure 7 A schematic diagram of an implementation flow of an operating method of a memory system according to an embodiment of the present disclosure;

[0059] Figure 8 A schematic diagram of threshold voltage distribution of a memory cell according to an embodiment of the present disclosure;

[0060] Fig. 9 A block diagram of an operating method of a memory system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0062] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0063] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0064] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0065] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0066] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0067] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0068] Figure 1 1 shows a block diagram of an exemplary system 100 having a memory according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , the system 100 may include a host device 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host device 108 may be a processor (e.g., a central processing unit) or a system on a chip (e.g., an application processor) of an electronic device. The host device 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0069] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host-side device 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host-side device 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital card, a compact flash card, a universal serial bus flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment SSD or embedded multimedia card, which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0070] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host-side device 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect protocol, a peripheral component interconnect high-speed protocol, an advanced technology attachment protocol, a serial advanced technology attachment protocol, a parallel advanced technology attachment protocol, a minicomputer small interface protocol, an enhanced small disk interface protocol, an integrated drive electronics protocol, a firmware protocol, etc.

[0071] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an embedded multimedia card package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2a In one example shown in FIG. 1 , the memory controller 106 and the single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a compact flash card, a smart media card, a memory stick, a multimedia card, a secure digital card, UFS, etc. The memory card 202 may also include a method of connecting the memory card 202 to a host device (e.g., Figure 1 The memory card connector 204 is coupled to the host device 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a processor that connects the SSD 206 to a host device (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of SSD206 is greater than the storage capacity and / or operating speed of memory card 202.

[0072] Figure 3a A schematic diagram of the structure of a memory array of a three-dimensional NAND memory is given as an example. Figure 3aAs shown, the memory array of the three-dimensional NAND memory is composed of several parallel and staggered rows of memory cells parallel to the gate isolation structure, and every four rows of memory cells are separated by the gate isolation structure and the upper selection gate isolation structure, and each memory cell row includes a plurality of memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure divides the memory array into a plurality of memory blocks (expressed in English as Blocks), the plurality of second gate isolation structures may divide the memory blocks into a plurality of finger storage areas (expressed in English as Finger), and the upper selection gate isolation structure provided in the middle of each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Figure 3a A memory block shown in FIG. 1 includes 6 memory slices. In practical applications, the number of memory slices in a memory block is not limited thereto. A memory cell in a memory slice coupled to a word line may be associated with a memory page (expressed in English as Page), where the memory page is a physical page.

[0073] It should be noted that Figure 3a The number of memory cell rows between the gate isolation structure and the upper selection gate isolation structure given in the disclosure is only an exemplary demonstration and is not used to limit the number of memory cell rows contained in a finger storage area of ​​the three-dimensional NAND memory in the present disclosure. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0074] Figure 3b 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1 300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. The memory array 301 is taken as a three-dimensional NAND type memory array for illustration, wherein the memory cells 306 are NAND memory cells, and the memory cells 306 are provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0075] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible memory states and can therefore store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed to take one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value may be used for an erased state.

[0076] like Figure 3b As shown in , each memory string 308 may include a bottom select transistor (BST) 310 at its source terminal and a top select transistor (TST) 312 at its drain terminal. BST 310 and TST 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TST 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read or written from the bit line 316 via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TST312) or a deselection voltage (e.g., 0 V) ​​to the corresponding TST312 via one or more TSLs (Top selected lines) 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BST310) or a deselection voltage (e.g., 0 V) ​​to the corresponding BST310 via one or more BSLs (Bottom Selected lines) 315.

[0077] like Figure 3bAs shown in , the memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in a selected memory block, the source lines 314 coupled to the selected memory block and the unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at the half-memory block level, at the quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of memory cells 306. The size of a memory page 320 in bits may be related to the number of memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 in a corresponding memory page 320 and a gate line coupling the control gates. Figure 3a A memory page 320 includes a plurality of memory cells 306, wherein the plurality of memory cells are isolated by an upper selection gate isolation structure and a gate isolation structure, and the plurality of memory cells between the upper selection gate isolation structure and the gate isolation structure are arranged into a plurality of memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper selection gate isolation structure. The memory cells in the memory slices sharing the same word line form a programmable (read / write) page.

[0078] Figure 4 2 shows a cross-sectional schematic diagram of an exemplary memory array 301 including memory strings 308 according to some aspects of the present disclosure. Figure 4 As shown, the memory string 308 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a memory string 308 that vertically penetrates the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412. The number of memory cells included in the memory array 301 is mainly related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0079] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0080] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0081] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0082] Return to reference Figure 3b, the peripheral circuit 302 may be coupled to the memory array 301 through the bit line 316, the word line 318, the source line 314, the BSL 315, and the TSL 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSL 315, and the TSL 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0083] The page buffer / sense amplifier 504 may be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to a control signal from the control logic unit 512. In one example, the page buffer / sense amplifier 504 may store a page of programming data (write data) to be programmed into one page 320 of the memory array 301. In another example, the page buffer / sense amplifier 504 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic unit 512, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0084] The row decoder / word line driver 508 may be configured to be controlled by the control logic unit 512 and select / deselect the memory block 304 of the memory array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSL 315 and the TSL 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word line 318. The voltage generator 510 may be configured to be controlled by the control logic unit 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 301.

[0085] The control logic unit 512 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic unit 512 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic unit 512 and act as a control buffer to buffer control commands received from a host-side device (not shown) and relay them to the control logic unit 512, as well as buffer status information received from the control logic unit 512 and relay them to the host-side device. The interface 516 may also be coupled to the column decoder / bit line driver 506 via a data bus 518 and act as a data I / O interface and a data buffer to buffer data and relay them to the memory array 301 or relay or buffer data from the memory array 301.

[0086] Figure 6A block diagram of a memory system 601 is shown. The memory system 601 includes: a memory controller 602 and a memory device 603. The memory controller 602 is used to control the memory device 603 to perform read and write operations. Here, the memory controller 602 and the memory device 603 can be coupled in any suitable manner. The memory controller 602 includes a control unit (CPU) 608, a buffer 609, an error correction unit 606, a host I / F 605, a memory I / F 607, a wear leveling unit 611, and a garbage collection unit 612. In the embodiment of the present disclosure, the memory device 603 can be a semiconductor memory for storing data in a non-volatile manner, such as a NAND type memory. The memory system 601 is connected to a host 604. Among them, the host I / F 605 outputs the command received from the host 604, the valid data (write data), etc. to the internal bus 610, and sends the valid data (read data) read from the memory device 603, the response from the control unit 608, etc. to the host 604.

[0087] The memory I / F 607 controls the process of writing data to the memory device 603 and the process of reading data from the memory device 603 based on the instruction of the control unit 608. The control unit 608 controls the memory system 601 as a whole, and the control unit 608 is, for example, a central processing unit (CPU), a microprocessor (MPU), etc. When the control unit 608 receives a command from the host 604 via the host I / F 605, it performs control according to the command. For example, the control unit 608 instructs the memory I / F 607 to write data to the memory device 603 according to the command from the host 604. In addition, the control unit 608 instructs the memory I / F 607 to read data from the memory device 603 according to the command from the host 604.

[0088] The buffer 609 temporarily stores data received from the host 604 before storing it in the memory device 603 , and temporarily stores data read from the storage device 603 before sending it to the host 604 .

[0089] The error correction unit 606 is a data encoding and decoding unit. Since flash memory storage has an inherent bit error rate, for the correctness of the data, error checking and correction (ECC) should be added to the original data during the data writing operation. This is an encoding process. When reading data, it is also necessary to detect and correct errors through decoding. If the number of erroneous bits exceeds the ECC error correction capability, the data will be uploaded to the host in an "uncorrectable" form. The ECC encoding and decoding process here is completed by the error correction unit 606.

[0090] Increased erase and write times will cause storage unit aging, long storage time will lead to loss of storage unit electrons, many read times will lead to threshold voltage shift, interference between storage units, write errors, etc. will all lead to read errors, affecting the integrity and reliability of data storage in the storage device.

[0091] The general process of reading data includes: first, using the first mechanism, the default read voltage can be used to read the data in the target storage page, and the low-density parity-check code (LDPC) hard decoding strategy is applied to data decoding; if the first mechanism fails to read the data, the second mechanism can be implemented to read the data in the target storage page. The second mechanism can use a read voltage table, which manages multiple groups of read voltage offset values ​​(ReadOffset). When the read fails using the default read voltage, the entire read voltage table is traversed, and the read voltage is changed to perform a read retry (RR, Read Retry); if the second mechanism still fails to read the data, the third mechanism can be implemented to read the data in the target storage page. The third mechanism can use a set of offset read voltages to read the data in the target storage page, such as applying the LDPC soft decoding strategy to data decoding; if the third mechanism also fails to read, the fourth mechanism can be implemented to use the RAID data recovery strategy to handle the read error; if the fourth mechanism also fails to read, the data loss of the target storage page is reported to the host.

[0092] In some embodiments, the single-level cell soft decoding basically follows the soft decoding algorithm of the multi-level cell, but due to the different threshold voltage offsets of the single-level cell and the multi-level cell, if the read retry of the single-level cell fails, the voltage offset will be greater when entering the LDPC stage, and the range of the digital signal processor (DSP) of the multi-level cell is very small, so it is not suitable to use the DSP algorithm of the multi-level cell to find the target read voltage, and it is more difficult to correct. How to improve the error correction capability of LDPC decoding has become an urgent problem to be solved.

[0093] Based on one or more of the above problems, the present disclosure provides an operating method of a memory system, such as Figure 7 As shown, the method includes:

[0094] Step S1001: sending a first command, wherein the first command instructs to perform a read operation on data in a target storage page using a first read voltage;

[0095] Step S1002: acquiring a first value and a second value read from the target storage page; when the threshold voltage of the storage cell is less than the first read voltage, the read data is the first value; when the threshold voltage of the storage cell is greater than the first read voltage, the read data is the second value;

[0096] Step S1003: obtaining a quantity difference between the first value and the second value;

[0097] Step S1004: determining whether the first read voltage is a target read voltage according to a difference between the first value and the second value.

[0098] In some specific examples, a memory system includes a memory device and a memory controller coupled to the memory device; the memory device includes a plurality of memory pages, and memory cells in memory slices sharing a same word line in the memory device form a memory page.

[0099] In some specific examples, the execution subject of the above embodiments may be a memory controller, and specifically may be a control unit of the memory controller.

[0100] The target read voltage here is also called the valley voltage, which indicates the read voltage that can correctly read the data in the target storage page. The target storage page here can be understood as the storage page that needs to perform a data read operation. Exemplarily, the target storage page can store data of (4KB+512B) size, that is, data of (4096B+512B) size.

[0101] In some embodiments, each of the memory pages includes a plurality of memory cells, each of the memory cells storing one bit of data.

[0102] In some specific examples, the memory cell may be a single-level cell or a multi-level cell used as a single-level cell, that is, one bit of data is stored in each memory cell. Each memory cell has two possible memory states including a first memory state and a second memory state. The first memory state may be an erased state, the data corresponding to the first memory state is a first value "0", the threshold voltage of the memory cell corresponding to the first value may be a first threshold voltage, and the first threshold voltage is less than the valley voltage; the second memory state may be a programmed state, the data corresponding to the second memory state is a second value "1", the threshold voltage of the memory cell corresponding to the second value may be a second threshold voltage, and the second threshold voltage is greater than the valley voltage.

[0103] like Figure 8 , which is a schematic diagram of the threshold voltage distribution of the memory cells, the memory cells in the target memory page include a first memory state E0 and a second memory state E1, and the threshold voltage corresponding to E0 is smaller than the threshold voltage corresponding to E1.

[0104] Here, when the threshold voltage of the memory cell is less than the first read voltage, the read data is a first value; when the threshold voltage of the memory cell is greater than the first read voltage, the read data is a second value. It can be understood that when the threshold voltage of the memory cell is less than the first read voltage, the read operation is performed with the first read voltage, and the data read from the memory cell is displayed as 0; when the threshold voltage of the memory cell is greater than the first read voltage, the read operation is performed with the first read voltage, and the data read from the memory cell is displayed as 1.

[0105] It is understandable that when one bit of data is stored in each storage cell, the number of "0" and "1" in the target storage page is close. When the first read voltage is a valley voltage, the data can be read correctly, so the number of data 0 and 1 read out is similar. When the first read voltage is significantly different from the valley voltage, part of the data will be misread, resulting in a larger difference in the number of read 0 and 1. The disclosed embodiment determines whether the first read voltage is the target read voltage based on the difference in the number of the first value "0" and the second value "1", and can quickly and efficiently find the valley voltage.

[0106] In some embodiments, determining whether the first read voltage is a target read voltage according to a quantitative difference between the first value and the second value includes:

[0107] When the absolute value of the difference between the first value and the second value is greater than a preset value, determining that the first read voltage is a non-target read voltage;

[0108] When the absolute value of the quantity difference between the first value and the second value is less than or equal to the preset value, the first read voltage is determined to be the target read voltage.

[0109] It can be understood that when the absolute value of the difference between the first value and the second value is greater than the preset value, it means that the first read voltage has a large difference with the valley voltage, resulting in a higher error rate in reading data, and therefore the first read voltage is not a valley voltage, and the read voltage needs to be changed to perform the reading operation again; when the absolute value of the difference between the first value and the second value is less than or equal to the preset value, it means that the first read voltage has a small difference with the valley voltage, resulting in a lower error rate in reading data, and therefore the first read voltage is a valley voltage.

[0110] In some embodiments, the preset value ranges from 100 to 300.

[0111] It should be noted that the range of preset values ​​given above is only for illustrative purposes and is not intended to limit the range of preset values ​​in the embodiments of the present disclosure. In some specific examples, the preset values ​​may be set accordingly based on the actual acceptable error rate of the read data.

[0112] In some embodiments, the method further comprises:

[0113] When the absolute value of the difference between the first value and the second value is greater than a preset value, and the number of the first value is greater than the number of the second value, sending a second command instructing to read the data in the target storage page with a second read voltage; the second read voltage is less than the first read voltage;

[0114] When the absolute value of the difference between the first value and the second value is greater than a preset value, and the number of the first value is less than the number of the second value, a third command is sent, wherein the third command instructs a read operation to be performed on the data in the target storage page with a third read voltage; the third read voltage is greater than the first read voltage.

[0115] It can be understood that the absolute value of the difference between the first value and the second value that is greater than the preset value may include two situations: 1. The first read voltage is less than the valley voltage; 2. The first read voltage is greater than the valley voltage. When the first read voltage is biased to the right relative to the valley voltage, that is, the first read voltage is greater than the valley voltage, some 1s in the storage cells to the left of the first read voltage will also be misread as 0s, so that the number of 0s is greater than the number of 1s, and therefore a voltage smaller than the first read voltage needs to be added for reading again; when the first read voltage is biased to the left relative to the valley voltage, that is, the first read voltage is less than the valley voltage, some 0s in the storage cells to the right of the first read voltage will be misread as 1s, so that the number of 1s is greater than the number of 0s, and therefore a voltage larger than the first read voltage needs to be added for reading again.

[0116] In some embodiments, obtaining the first value and the second value read from the target storage page and obtaining the quantitative difference between the first value and the second value include:

[0117] temporarily storing the first value and the second value read from the target storage page in a register in a memory controller;

[0118] The register is used to count the number of the first value and the second value.

[0119] In some specific examples, the memory controller includes a register, and the register is used to count the number of the first value and the second value read from the target memory page.

[0120] In some embodiments, the storage page corresponds to a read voltage table, the read voltage table includes a plurality of read voltages arranged in ascending order, and the values ​​of two adjacent read voltages differ by a fixed offset;

[0121] The method further comprises:

[0122] When performing a read operation on the target storage page, a read voltage in the read voltage table is selected by binary selection to perform a read operation on data in the target storage page.

[0123] In some specific examples, the binary method can be used to continuously switch the read voltage until the number of the read first value and the second value is in a balanced state, so that it can be determined that the current read voltage is the target read voltage.

[0124] It can be understood that the embodiment of the present disclosure uses the binary method to select a read voltage from the read voltage table to perform a read operation on the target storage page, which can improve the read efficiency and reduce the number of read times.

[0125] It should be noted that the method for selecting the read voltage includes but is not limited to the dichotomy method described in the above embodiments. In some specific examples, the method for selecting the read voltage may also be the ergodic method.

[0126] In some embodiments, the operating method further includes:

[0127] receiving the first command sent from a memory controller of the memory system;

[0128] The first value and the second value read from the target memory page are sent to the memory controller.

[0129] In some specific examples, the memory device includes a peripheral circuit, and the execution subject of receiving the first command and sending the data read from the target storage page to the memory controller in the above embodiment may be the peripheral circuit of the memory device.

[0130] Fig. 9 A block diagram of an operating method of a memory system provided by an embodiment of the present disclosure. Fig. 9As shown, it specifically includes: initialization; sending a command to perform a read operation on the target storage page with a first read voltage, the first read voltage can be a default read voltage, that is, a voltage without an offset, and setting the size of the data to be sent, for example, (4096B+512B) of data; next, obtaining the quantitative difference between the first value and the second value, and determining whether the quantitative difference between the first value and the second value is less than a preset value; when the quantitative difference between the first value and the second value is less than the preset value, determining that the current read voltage is the target read voltage; when the quantitative difference between the first value and the second value is greater than the preset value, offsetting a certain voltage offset on the basis of the first read voltage to obtain a new read voltage, performing the read operation again, and checking the quantitative difference between the first value and the second value in the read data again, and determining again whether the quantitative difference between the first value and the second value is less than the preset value, if the quantitative difference between the first value and the second value is greater than the preset value, then changing the read voltage again for reading until it is determined that the quantitative difference between the first value and the second value is less than the preset value.

[0131] The disclosed embodiment provides an operation method of a memory system, the method comprising: sending a first command, the first command instructing to read data in a target storage page with a first read voltage; obtaining a first value and a second value read from the target storage page; when the threshold voltage of a storage cell is less than the first read voltage, the read data is the first value; when the threshold voltage of a storage cell is greater than the first read voltage, the read data is the second value; obtaining the quantitative difference between the first value and the second value; and determining whether the first read voltage is a target read voltage according to the quantitative difference between the first value and the second value. In the disclosed embodiment, after performing a read operation on the target storage page with the first read voltage, determining whether the first read voltage is a target read voltage according to the quantitative difference between the first value and the second value can quickly, efficiently and accurately determine the position of the target voltage, thereby improving the error correction capability of the low-density parity check code and improving the reading efficiency.

[0132] Based on the operating method of the above-mentioned memory system, an embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the operating method described in any of the above-mentioned embodiments is executed.

[0133] Here, all or part of the processes in the above-mentioned embodiment method can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk (HDD), or a solid state drive, etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0134] Based on the above-mentioned operating method of the memory system, an embodiment of the present disclosure further provides a memory system, the memory system comprising a memory device and a memory controller coupled to the memory device; the memory device comprises a plurality of memory pages, and the memory controller is configured as follows:

[0135] Sending a first command, wherein the first command instructs to perform a read operation on data in a target storage page using a first read voltage;

[0136] Acquire a first value and a second value read from the target storage page; when the threshold voltage of the storage cell is less than the first read voltage, the read data is the first value; when the threshold voltage of the storage cell is greater than the first read voltage, the read data is the second value;

[0137] Obtaining a quantitative difference between the first value and the second value;

[0138] Whether the first read voltage is a target read voltage is determined according to a quantitative difference between the first value and the second value.

[0139] In some embodiments, the memory controller is configured to:

[0140] When the absolute value of the difference between the first value and the second value is greater than a preset value, determining that the first read voltage is a non-target read voltage;

[0141] When the absolute value of the quantity difference between the first value and the second value is less than or equal to the preset value, the first read voltage is determined to be the target read voltage.

[0142] In some embodiments, the preset value ranges from 100 to 300.

[0143] In some embodiments, each of the memory pages includes a plurality of memory cells, each of the memory cells storing one bit of data.

[0144] In some embodiments, the memory controller is configured to:

[0145] When the absolute value of the difference between the first value and the second value is greater than a preset value, and the number of the first value is greater than the number of the second value, sending a second command instructing to read the data in the target storage page with a second read voltage; the second read voltage is less than the first read voltage;

[0146] When the absolute value of the difference between the first value and the second value is greater than a preset value, and the number of the first value is less than the number of the second value, a third command is sent, wherein the third command instructs a read operation to be performed on the data in the target storage page with a third read voltage; the third read voltage is greater than the first read voltage.

[0147] In some embodiments, the memory controller includes a register, the memory controller being configured to:

[0148] temporarily storing the first value and the second value read from the target storage page in the register;

[0149] The register is used to count the number of the first value and the second value.

[0150] In some embodiments, the storage page corresponds to a read voltage table, the read voltage table includes a plurality of read voltages arranged in ascending order, and the values ​​of two adjacent read voltages differ by a fixed offset;

[0151] The memory controller is configured to:

[0152] When performing a read operation on the target storage page, a read voltage in the read voltage table is selected by binary selection to perform a read operation on data in the target storage page.

[0153] In some embodiments, the memory system includes a memory card or a solid state drive.

[0154] In some embodiments, the memory device includes a memory array and a peripheral circuit coupled to the memory array; the peripheral circuit is configured to:

[0155] receiving the first command sent from the memory controller;

[0156] The first value and the second value read from the target memory page are sent to the memory controller.

[0157] Here, the specific structure and composition of the memory system can be referred to in the above Figure 1 , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4 , Figure 5 , Figure 6 The detailed description of the memory system is as follows, and other details about the memory system are similar to those in the aforementioned operation method of the memory system, and are not repeated here for the sake of brevity.

[0158] Based on the above memory system, an embodiment of the present disclosure further provides an electronic device, including the memory system as described in any of the above embodiments, and a host coupled to the memory system.

[0159] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0160] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0161] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory system, characterized in that: The memory system includes a memory device and a memory controller coupled to the memory device; the memory device includes a plurality of memory pages, and the memory controller is configured to: Sending a first command, wherein the first command instructs to perform a read operation on data in a target storage page using a first read voltage; Acquire a first value and a second value read from the target storage page; when the threshold voltage of the storage cell is less than the first read voltage, the read data is the first value; when the threshold voltage of the storage cell is greater than the first read voltage, the read data is the second value; Obtaining a quantitative difference between the first value and the second value; Whether the first read voltage is a target read voltage is determined according to a quantitative difference between the first value and the second value.

2. The memory system according to claim 1, wherein: The memory controller is configured to: When the absolute value of the difference between the first value and the second value is greater than a preset value, determining that the first read voltage is a non-target read voltage; When the absolute value of the quantity difference between the first value and the second value is less than or equal to the preset value, the first read voltage is determined to be the target read voltage.

3. The memory system according to claim 2, wherein: The preset value ranges from 100 to 300.

4. The memory system according to claim 1, wherein: Each of the memory pages includes a plurality of memory cells, and each of the memory cells stores one bit of data.

5. The memory system according to claim 1, wherein: The memory controller is configured to: When the absolute value of the difference between the first value and the second value is greater than a preset value, and the number of the first value is greater than the number of the second value, sending a second command instructing to read the data in the target storage page with a second read voltage; the second read voltage is less than the first read voltage; When the absolute value of the difference between the first value and the second value is greater than a preset value, and the number of the first value is less than the number of the second value, a third command is sent, wherein the third command instructs a read operation to be performed on the data in the target storage page with a third read voltage; the third read voltage is greater than the first read voltage.

6. The memory system according to claim 1, wherein: The memory controller comprises a register, and the memory controller is configured to: temporarily storing the first value and the second value read from the target storage page in the register; The register is used to count the number of the first value and the second value.

7. The memory system according to claim 1, wherein: The storage page corresponds to a read voltage table, wherein the read voltage table includes a plurality of read voltages arranged in ascending order, and the values ​​of two adjacent read voltages differ by a fixed offset; The memory controller is configured to: When performing a read operation on the target storage page, a read voltage in the read voltage table is selected by binary selection to perform a read operation on data in the target storage page.

8. The memory system according to claim 1, wherein: The memory system includes a memory card or a solid state drive.

9. The memory system according to claim 1, wherein: The memory device includes a memory array and a peripheral circuit coupled to the memory array; the peripheral circuit is configured to: receiving the first command sent from the memory controller; The first value and the second value read from the target memory page are sent to the memory controller.

10. A method for operating a memory system, characterized in that: The operation method comprises: Sending a first command, wherein the first command instructs to perform a read operation on data in a target storage page using a first read voltage; Acquire a first value and a second value read from the target storage page; when the threshold voltage of the storage cell is less than the first read voltage, the read data is the first value; when the threshold voltage of the storage cell is greater than the first read voltage, the read data is the second value; Obtaining a quantitative difference between the first value and the second value; Whether the first read voltage is a target read voltage is determined according to a quantitative difference between the first value and the second value.

11. The operating method according to claim 10, characterized in that: The determining, according to the difference between the first value and the second value, whether the first read voltage is a target read voltage comprises: When the absolute value of the difference between the first value and the second value is greater than a preset value, determining that the first read voltage is a non-target read voltage; When the absolute value of the quantity difference between the first value and the second value is less than or equal to the preset value, the first read voltage is determined to be the target read voltage.

12. The operating method according to claim 11, characterized in that: The preset value ranges from 100 to 300.

13. The operating method according to claim 10, characterized in that: The method further comprises: When the absolute value of the difference between the first value and the second value is greater than a preset value, and the number of the first value is greater than the number of the second value, sending a second command instructing to read the data in the target storage page with a second read voltage; the second read voltage is less than the first read voltage; When the absolute value of the difference between the first value and the second value is greater than a preset value, and the number of the first value is less than the number of the second value, a third command is sent, wherein the third command instructs a read operation to be performed on the data in the target storage page with a third read voltage; the third read voltage is greater than the first read voltage.

14. The operating method according to claim 10, characterized in that: The obtaining of the first value and the second value read from the target storage page and obtaining the quantitative difference between the first value and the second value includes: temporarily storing the first value and the second value read from the target storage page in a register in a memory controller; The register is used to count the number of the first value and the second value.

15. The operating method according to claim 10, characterized in that: The storage page corresponds to a read voltage table, wherein the read voltage table includes a plurality of read voltages arranged in ascending order, and the values ​​of two adjacent read voltages differ by a fixed offset; The method further comprises: When performing a read operation on the target storage page, a read voltage in the read voltage table is selected by binary selection to perform a read operation on data in the target storage page.

16. The operating method according to claim 10, characterized in that: The operation method also includes: receiving the first command sent from a memory controller of the memory system; The first value and the second value read from the target memory page are sent to the memory controller.

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