Method for preparing dielectric layer of field effect transistor device and method for preparing field effect transistor device by using dielectric layer

Abstract

The invention belongs to the technical field of field effect transistor devices, and discloses a preparation method of a dielectric layer of a field effect transistor device and a method for preparing the field effect transistor device by using the dielectric layer. The preparation method of the field effect transistor device dielectric layer comprises the following steps: stripping hafnium sulfide to obtain thin hafnium sulfide; and then transferring the thin hafnium sulfide layer to a polydimethylsiloxane seal, and carrying out thermal oxidation treatment to prepare the hafnium oxide dielectric layer. The dielectric layer of the field effect transistor device prepared by the method has the characteristics of no wrinkle on the surface, uniform distribution and atomic-scale flatness, is a high-k dielectric layer in good natural oxide contact, and can remarkably improve the performances such as the sub-threshold swing of the field effect transistor device when being used as the high-k dielectric layer. The field effect transistor device prepared by the invention is simple in structure, excellent in performance and simple in manufacturing method.

Description

Technical Field

[0001] The present invention belongs to the technical field of field effect transistor devices, and in particular relates to a method for preparing a dielectric layer of a field effect transistor device and a method for preparing a field effect transistor device using the same. Background Art

[0002] The history of electronics is usually composed of three major electronic devices - vacuum tubes, bipolar junction transistors (BJTs), and metal oxide semiconductor field effect transistors (MOSFETs). The first two devices have played an important role in advancing modern computing, but it is the metal oxide semiconductor field effect transistor (MOSFET) that has really enabled the explosive development of information technology in the past 60 years, especially the rise of complementary metal oxide semiconductor (CMOS) technology, which has been a powerful engine of contemporary human technological civilization. For very large scale integrated circuit (VLSI) applications, the most attractive advantage of metal oxide semiconductor field effect transistors (MOSFETs) is that their continuous reduction in physical size has driven every important indicator - cost, performance, energy consumption, etc. - towards efficiency. In addition, the "field effect" nature of complementary metal oxide semiconductors (CMOS) and the complementary circuit (including n-type and p-type MOSFET) topology give them ultra-low leakage power, which makes them very advantageous in low-power applications. Therefore, after the early major bottleneck silicon (Si) / silicon dioxide (SiO2) interface (defect) problem was solved, complementary metal oxide semiconductor (CMOS) technology quickly replaced bipolar transistors in the growing digital market, paving the way for the information technology era based on very large scale integration (VLSI).

[0003] The function of a typical metal oxide semiconductor field effect crystal (MOSFET) is similar to that of a general faucet. In a faucet, the flow of water is controlled by using a mechanical knob, while in a metal oxide semiconductor field effect crystal (MOSFET), the charge carriers (electrons or holes) are controlled through the channel from the source to the drain by using a "field effect" or capacitively coupled electric gate. From the perspective of the semiconductor energy band, the gate bias is used to modulate the energy band of the channel under the gate. The performance of a metal oxide semiconductor field effect crystal (MOSFET) is usually judged by data such as the switching ratio and the subthreshold swing. At room temperature (T = 300k), the MOS type subthreshold swing (Swing) satisfies:

[0004]

[0005] Where V G is the gate voltage, I D is the drain current, is the surface potential, k is the relative dielectric constant, T is the temperature, q is the charge, Cox is the dielectric layer capacitance, C D is the drain capacitance.

[0006] Therefore, the theoretical minimum is:

[0007] log(10)·kT / q=59.6mV / dec≈60mV / dec

[0008] In a FET device, the closer the actual measured subthreshold swing is to 60mV / dec, the stronger the gate's control over the channel, and vice versa. Based on this, the subthreshold swing of the device can be reduced and its performance can be improved by selecting a high-k dielectric layer. The current mainstream dielectric layer is a nanoscale hafnium oxide (HfO2) film obtained by atomic layer deposition (ALD), but the hafnium oxide film obtained by atomic layer deposition has atomic defects, the surface flatness cannot be guaranteed, and there is a contact problem between the dielectric layer and the two-dimensional material. Therefore, the dielectric layer of the FET device prepared by atomic layer deposition has more room for optimization in theory. Moreover, the process of completing the preparation of hafnium oxide by atomic layer deposition is very cumbersome. If there is no atomic layer deposition equipment in the experimental environment, the experiment will not be realized. Therefore, a simple, economical and effective method for obtaining high-quality hafnium oxide as a dielectric layer of a field effect transistor device is needed. Summary of the invention

[0009] The present invention aims to solve at least one of the technical problems existing in the above-mentioned prior art. To this end, the present invention provides a method for preparing a dielectric layer of a field effect transistor device and a method for preparing a field effect transistor device using the same. The preparation method provided by the present invention can simply, economically and effectively obtain a high-quality hafnium oxide dielectric layer, and the field effect transistor device prepared using the same has excellent performance and a significantly reduced subthreshold swing.

[0010] The invention provides a method for preparing a dielectric layer of a field effect transistor device.

[0011] Specifically, a method for preparing a dielectric layer of a field effect transistor device comprises the following steps:

[0012] The hafnium sulfide is peeled off to obtain a thin layer of hafnium sulfide; then the thin layer of hafnium sulfide is transferred to a polydimethylsiloxane (PMDS) stamp and subjected to thermal oxidation treatment to obtain a hafnium oxide dielectric layer, namely a dielectric layer of a field effect transistor device.

[0013] Preferably, the stripping method is to use a mechanical method to strip, such as using a blue tape to use a mechanical stripping method to strip the hafnium sulfide (HfS2).

[0014] Preferably, the thickness of the thin layer of hafnium sulfide is 20-30 nm.

[0015] Preferably, the temperature of the thermal oxidation treatment is 130-170° C., and the time of the thermal oxidation treatment is 1.5-3.0 hours. More preferably, the temperature of the thermal oxidation treatment is 140-160° C., and the time of the thermal oxidation treatment is 2-2.5 hours.

[0016] Preferably, before the step of thermal oxidation treatment, the method further comprises the steps of cleaning and cutting, wherein the cleaning process is to clean the uneven thickness of hafnium sulfide on the polydimethylsiloxane stamp except the thin layer of hafnium sulfide. The cutting process is to cut the polydimethylsiloxane stamp with the thin layer of hafnium sulfide to the target size.

[0017] The invention also provides a method for preparing a field effect transistor device.

[0018] A method for preparing a field effect transistor device comprises the following steps:

[0019] peeling off the hafnium sulfide to obtain a thin layer of hafnium sulfide; then transferring the thin layer of hafnium sulfide to a polydimethylsiloxane stamp and performing a thermal oxidation treatment to obtain a hafnium oxide dielectric layer;

[0020] The hafnium oxide dielectric layer is transferred to the carbon nanotube substrate, and then a transistor channel is made; a source electrode, a drain electrode and a gate are prepared to obtain a field effect transistor device;

[0021] The hafnium oxide dielectric layer includes a hafnium sulfide layer and a hafnium oxide layer; the carbon nanotube substrate includes a carbon nanotube layer, and during the transfer process, the hafnium oxide layer in the hafnium oxide dielectric layer is disposed on the carbon nanotube layer.

[0022] Preferably, the carbon nanotube substrate comprises a silicon layer, a silicon dioxide layer and a carbon nanotube layer (CNT) in sequence.

[0023] Preferably, the silicon dioxide layer has a thickness of 200-400 nm.

[0024] Preferably, the source electrode and the drain electrode are prepared by using photoresist, patterning by laser direct writing lithography technology and electron beam evaporation to prepare the source electrode and the drain electrode at the left and right ends of the carbon nanotube substrate.

[0025] Preferably, the source electrode and the drain electrode are Pd.

[0026] Preferably, the gate is prepared by using photoresist, patterning by laser direct writing technology and electron beam evaporation to prepare the gate on the hafnium sulfide layer of the hafnium oxide dielectric layer.

[0027] Preferably, the gate is Ti or Au.

[0028] The present invention aims to solve the problem of uneven hafnium oxide and contact between the hafnium oxide dielectric layer and the two-dimensional material when preparing the hafnium oxide dielectric layer by atomic layer deposition. The high-k dielectric layer gate MOS structure of hafnium sulfide-hafnium oxide (HfS2-HfO2) is formed by oxidizing the surface of hafnium sulfide to obtain hafnium oxide with dense interlayer connection and atomically flat surface as the dielectric layer of the carbon nanotube-field effect transistor device, which significantly solves the contact problem. The field effect transistor device prepared by the present invention has excellent performance, and the subthreshold swing is greatly reduced to 73mV / dec, and the on-off also meets the requirements of high-performance FET, reaching 10 6 .

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] (1) The hafnium oxide dielectric layer (i.e., the dielectric layer of the field effect transistor device) prepared by the present invention has a wrinkle-free surface, is evenly distributed, and has the characteristics of atomic-level flatness. It is a high-k dielectric layer with good natural oxide contact. When used as a high-k dielectric layer, it can significantly improve the subthreshold swing and other performance of the field effect transistor device.

[0031] (2) The present invention only needs thermal oxidation to prepare a high-quality hafnium oxide dielectric layer (i.e., a dielectric layer of a field effect transistor device), without the need for atomic layer deposition equipment, which not only ensures economic efficiency but also achieves significant results and can effectively reduce the preparation cost. At the same time, the structure of the prepared field effect transistor device is simple and the manufacturing method is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is the surface morphology of hafnium sulfide;

[0033] Figure 2 A schematic structural plan view of the field effect transistor device prepared in Example 1;

[0034] Figure 3 A flow chart of the production of a field effect transistor device prepared in Example 1;

[0035] Figure 4 A cross-sectional TEM image of the dielectric layer of the field effect transistor device prepared in Example 1;

[0036] Figure 5 The transfer characteristic curve of the field effect transistor device prepared in Example 1;

[0037] Figure 6 This is a full-view optical display of the field effect transistor prepared in Example 1;

[0038] Figure 7 The transfer characteristic curve of the field effect transistor device prepared in Example 2;

[0039] Figure 8 This is a full optical display of the field effect transistor device prepared in Example 2;

[0040] Fig. 9 This is the transfer characteristic curve of the field effect transistor device prepared in Comparative Example 1.

[0041] Description of Figure Numbers:

[0042] A thin layer of hafnium sulfide-100, a hafnium oxide layer-200, a carbon nanotube substrate-300, a carbon nanotube layer (CNT)-310, a silicon dioxide layer-320, a silicon layer-330, a drain electrode-400, a source electrode-500, and a gate-600. DETAILED DESCRIPTION

[0043] In order to make the technical scheme of the present invention more clearly understood by those skilled in the art, the following embodiments are listed for illustration. It should be pointed out that the following embodiments do not limit the protection scope of the present invention.

[0044] Unless otherwise specified, the raw materials, reagents or devices used in the following examples and comparative examples can be obtained from conventional commercial sources or by existing known methods.

[0045] An embodiment of the present invention provides a method for preparing a dielectric layer of a field effect transistor device, comprising the following steps: peeling off hafnium sulfide to obtain a thin layer of hafnium sulfide; then transferring the thin layer of hafnium sulfide to a polydimethylsiloxane (PMDS) stamp, performing thermal oxidation treatment, and obtaining a hafnium oxide dielectric layer.

[0046] In some embodiments of the present invention, mechanical methods are used to peel off hafnium sulfide. For example, blue tape is used to use a mechanical peeling method to peel off hafnium sulfide (HfS2), and after peeling, the hafnium sulfide is transferred to a polydimethylsiloxane (PMDS) stamp. Hafnium sulfide is a two-dimensional transition metal sulfide that has the nano-thin layer characteristics of a two-dimensional material and excellent light transmittance. The surface morphology of hafnium sulfide is scanned using an atomic force microscope (AFM), and it can be seen that the surface roughness of the sample is extremely low (e.g. Figure 1 As shown in FIG. 1 , since hafnium sulfide is obtained by a mechanical stripping method, the thin layer of hafnium sulfide obtained by this method can maintain a high surface flatness.

[0047] In some embodiments of the present invention, the thickness of the thin layer of hafnium sulfide obtained after stripping is 20-30 nm. By controlling the thickness of the thin layer of hafnium sulfide and the temperature and time of thermal oxidation treatment, a dielectric layer of a field effect transistor device with excellent performance can be prepared.

[0048] Furthermore, during the transfer process, a large-area thin layer of polydimethylsiloxane (PMDS) stamp can be used to adhere to a slightly larger glass slide as needed. The large-area thin layer of polydimethylsiloxane stamp makes it easier to obtain a large-area thin layer of hafnium sulfide, and a glass slide slightly larger than the polydimethylsiloxane stamp can ensure that the stress generated by the polydimethylsiloxane stamp during the peeling process is avoided. The influence of the stress on the material can be avoided, thereby minimizing the damage to the thin layer of material when transferring the material. This method can significantly reduce the wrinkles of the sample material.

[0049] In some embodiments of the present invention, before the step of performing thermal oxidation treatment, the steps of cleaning and cutting are also included. The cleaning process is: cleaning the uneven thickness of hafnium sulfide other than the thin layer of hafnium sulfide on the polydimethylsiloxane stamp. The cutting process is: cutting the polydimethylsiloxane stamp with a thin layer of hafnium sulfide attached to the target size. More specifically, after obtaining the hafnium sulfide on the large-area thin layer polydimethylsiloxane stamp, the polydimethylsiloxane-assisted transfer method is used to clean the HfS2 with uneven thickness other than the thin layer of hafnium sulfide on the large-area thin layer polydimethylsiloxane stamp using a microscope system and a transfer table. Since the thin layer polydimethylsiloxane stamp has strong adhesion and extremely thin thickness, cleaning other materials with uneven thickness can avoid the entry of air bubbles caused by excessively thick materials during the subsequent transfer process to interfere with the transfer. After cleaning, use a blade to cut the large-area thin-layer polydimethylsiloxane stamp into small areas where only the target thin-layer hafnium sulfide is retained, to avoid excessive adhesion between the subsequent carbon nanotube (CNT) sample substrate and the polydimethylsiloxane stamp, resulting in the inability to lift the polydimethylsiloxane stamp during transfer.

[0050] In some embodiments of the present invention, the temperature of the thermal oxidation treatment is 130-170°C, and the time of the thermal oxidation treatment is 1.5-3.0 hours. Furthermore, the temperature of the thermal oxidation treatment is 140-160°C, and the time of the thermal oxidation treatment is 2-2.5 hours. The obtained sample is placed on a clean room heating table for thermal oxidation treatment. During the thermal oxidation treatment, a controllable hafnium oxide oxide layer (dielectric layer) can be obtained by controlling the stable thermal oxidation treatment temperature and the thermal oxidation treatment time. Furthermore, in order to obtain a more perfect hafnium oxide dielectric layer, HfS2 with a thickness of about 20-30 nm is selected and thermally oxidized for 2h-2.5h. If the oxidation time is too short, the hafnium oxide dielectric layer formed by thermal oxidation will be too thin, which will reduce its breakdown voltage and affect the capacitance characteristics of the field effect transistor (FET). If the oxidation time is too long, the hafnium oxide dielectric layer will be too thick, which will weaken the gate's control over the channel electric field, reduce the effect of the gate voltage on the charge carriers in the channel, and further affect the switching speed and performance of the field effect transistor. Therefore, the thickness of the hafnium oxide dielectric layer is crucial.

[0051] The present invention also provides a method for preparing a field effect transistor device, comprising the following steps:

[0052] The hafnium sulfide is peeled off to obtain a thin layer of hafnium sulfide; the thin layer of hafnium sulfide is then transferred to a polydimethylsiloxane stamp and subjected to thermal oxidation treatment to obtain a hafnium oxide dielectric layer;

[0053] The hafnium oxide dielectric layer is transferred to the carbon nanotube substrate, and then a transistor channel is made; a source electrode, a drain electrode and a gate are prepared to make a field effect transistor device;

[0054] The hafnium oxide dielectric layer includes a hafnium sulfide layer and a hafnium oxide layer; the carbon nanotube substrate includes a carbon nanotube layer, and during the transfer process, the hafnium oxide layer in the hafnium oxide dielectric layer is arranged on the carbon nanotube layer.

[0055] In some embodiments of the present invention, the carbon nanotube substrate includes a silicon layer, a silicon dioxide layer and a carbon nanotube layer in sequence.

[0056] In some embodiments of the present invention, the thickness of the silicon dioxide layer is 200-400 nm, such as 300 nm.

[0057] In some embodiments of the present invention, the source electrode and the drain electrode are prepared by using photoresist, patterning by laser direct writing lithography technology and electron beam evaporation to prepare the source electrode and the drain electrode at the left and right ends of the carbon nanotube substrate.

[0058] In some embodiments of the present invention, the source electrode and the drain electrode are Pd.

[0059] In some embodiments of the present invention, the gate is prepared by using a photoresist (such as photoresist AZ5214) to prepare a gate on the hafnium sulfide layer of the hafnium oxide dielectric layer through patterning processing using laser direct writing technology and electron beam evaporation.

[0060] In some embodiments of the present invention, the gate is Ti or Au.

[0061] Example 1

[0062] A method for preparing a dielectric layer of a field effect transistor device and a field effect transistor device, and a process flow chart of the field effect transistor device is shown in Figure 3 As shown, the following steps are included:

[0063] (1) The hafnium sulfide is peeled off by mechanical peeling to obtain a thin layer of hafnium sulfide; then the thin layer of hafnium sulfide is transferred to a polydimethylsiloxane stamp to obtain hafnium sulfide on a large area of ​​the polydimethylsiloxane stamp, and then the polydimethylsiloxane-assisted transfer method is used to clean the HfS2 with uneven thickness on the large area of ​​the polydimethylsiloxane stamp except for the thin layer of hafnium sulfide using a microscope system and a transfer table. After the cleaning is completed, the polydimethylsiloxane stamp is cut into a small area with a blade to retain only the target thin layer of hafnium sulfide, so as to avoid excessive adhesion between the subsequent carbon nanotube substrate and the polydimethylsiloxane stamp, which may cause the polydimethylsiloxane stamp to be unable to be lifted during transfer. After cleaning and cutting, the larger glass slide with the dimethylsiloxane stamp is placed on a heating table in a clean room for thermal oxidation treatment. The heating temperature is set to 150°C and the thermal oxidation treatment is performed for 2 hours to obtain a hafnium oxide dielectric layer (i.e., a field effect transistor device dielectric layer). The obtained hafnium oxide dielectric layer includes a hafnium sulfide layer and a hafnium oxide layer. The hafnium oxide in this structure is obtained by oxidizing hafnium sulfide layers in a sandwich structure.

[0064] (2) Take a carbon nanotube substrate, which includes a silicon layer (525 micrometers thick), a silicon dioxide layer (300 nm thick) and a carbon nanotube layer (2-3 nm thick). Use a transfer station to transfer the hafnium oxide dielectric layer to the carbon nanotube substrate, so that the hafnium oxide layer in the hafnium oxide dielectric layer is disposed on the carbon nanotube layer.

[0065] (3) Through plasma surface treatment, the transistor channel is fabricated; then, using photoresist AZ5214, laser direct writing lithography technology is used for patterning and electron beam evaporation (e-beam) is used to prepare palladium electrodes on the left and right ends of the carbon nanotube substrate as its source electrode and drain electrode. Then, annealing and cleaning are performed, and finally, photolithography nesting technology is used, using photoresist AZ5214, laser direct writing technology is used to pattern the gate electrode, and then electron beam evaporation is used to evaporate titanium gate electrode in the gate overlay pattern to obtain a field effect transistor device. The structural schematic diagram of the field effect transistor device is shown in Figure 2 , the overall picture of the optical display of field effect transistor devices can be seen Figure 6 .

[0066] The hafnium oxide dielectric layer (i.e., the dielectric layer of the field effect transistor device) was microdissected using a focused ion beam microscope (FIB). A focused ion beam microscope is a microdissecting instrument that uses an electric lens to focus an ion beam into a very small size. It usually uses an ion beam generated by a liquid metal (such as gallium) ion source, which is accelerated and focused by an ion gun and irradiated on the sample surface. After obtaining the cross section, the sample is characterized using a transmission electron microscope (TEM), which uses an accelerated and focused electron beam as an illumination source. When the electron beam is projected onto a very thin sample, the electrons collide with the atoms in the sample and change direction, resulting in three-dimensional angular scattering. The size of the scattering angle is related to the density and thickness of the sample, so different bright and dark images can be formed. These images are magnified and focused, and finally displayed on the imaging device. In the semiconductor industry, TEM is widely used to observe and analyze the microstructure and composition of semiconductor materials. Test results such as Figure 4 As shown, it can be clearly observed that the entire sample is divided into two layers. The upper layer is standard hafnium sulfide, and its lattice spacing is 0.59-0.61nm; while the lower layer shows a color difference that is obviously different from the upper layer, and its lattice spacing is 0.53-0.54nm, showing lattice characteristics different from hafnium sulfide, and is confirmed to be hafnium oxide. It can be observed that the hafnium oxide formed by thermal oxidation is clearly layered, and the surface is wrinkle-free, uniformly distributed, and has the characteristics of atomic-level flatness. The present invention obtains a high-k dielectric layer with good native oxide contact by thermal oxidation, which can be used as a high-k dielectric layer of FET devices to improve performance such as subthreshold swing.

[0067] The transfer characteristic curve of the field effect transistor device obtained using the 4200 electrical test platform, such as Figure 5 As shown. Figure 5 It can be seen that the subthreshold swing of the field effect transistor device prepared by thermal oxidation for 2 h in this embodiment is 94 mV / dec.

[0068] Example 2

[0069] The difference between Example 2 and Example 1 is that when preparing the dielectric layer of the field effect transistor device in Example 2, the thermal oxidation treatment time is 2.5 hours, and the rest of the preparation process is the same as in Example 1. The optical display of the field effect transistor device prepared in Example 2 is as follows: Figure 8 shown.

[0070] The transfer characteristic curve of the field effect transistor device obtained using the 4200 electrical test platform, such as Figure 7 As shown. Figure 7 It can be seen that the subthreshold swing of the field effect transistor device prepared by thermal oxidation for 2.5 hours in this embodiment is 73 mV / dec.

[0071] Comparative Example 1

[0072] The difference between Comparative Example 1 and Example 1 is that when the dielectric layer of the field effect transistor device is prepared in Comparative Example 1, the thermal oxidation treatment time is 1 hour, and the rest of the preparation process is the same as Example 1.

[0073] The transfer characteristic curve of the field effect transistor device obtained using the 4200 electrical test platform, such as Fig. 9 As shown. Fig. 9 It can be seen that the subthreshold swing of the field effect transistor device prepared by thermal oxidation for 1 h in this comparative example is 347 mV / dec.

[0074] In the process of preparing the hafnium oxide dielectric layer (i.e., the dielectric layer of the field effect transistor device), if the oxidation time is too short, the obtained hafnium oxide dielectric layer will be too thin, which will make its breakdown voltage too small, and the obtained hafnium oxide will be uneven. During the thermal oxidation process, the surface hafnium sulfide will react with O2 in the air and gradually oxidize to a hafnium sulfide-hafnium oxide structure. Depending on the oxidation time, the subthreshold swing exhibited by the device will also be different. By comparing Examples 1 and 2 with Comparative Example 1, it can be seen that the subthreshold swings of the devices thermally oxidized for 2 to 2.5 hours are 94mV / dec and 73mV / dec, respectively, which are significantly better than the device with a subthreshold swing of 347mV / dec after thermal oxidation for 1 hour. The difference in oxidation time causes the thickness of the hafnium oxide dielectric layer obtained by oxidation to be different, which in turn affects the gate capacitance, and miniaturized devices require higher gate capacitance to improve device performance and reduce power consumption.

[0075] In summary, the field effect transistor device prepared in the embodiment of the present invention exhibits excellent subthreshold swing and 10 6 The high on-off performance is achieved because the hafnium oxide in the hafnium oxide dielectric layer obtained by thermal oxidation is a two-dimensional semiconductor as an insulating natural oxide, which is crucial to further achieve simplified manufacturing processes and good interface quality. It ensures excellent contact with the dielectric layer, that is, the natural insulating oxide layer obtained by thermal oxidation, avoiding damage to the transistor performance due to voids or atomic defects in the dielectric layer contact.

[0076] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a dielectric layer of a field effect transistor device, characterized in that: The following steps are involved: The hafnium sulfide is peeled off to obtain a thin layer of hafnium sulfide; then the thin layer of hafnium sulfide is transferred to a polydimethylsiloxane stamp and subjected to thermal oxidation treatment to obtain a hafnium oxide dielectric layer.

2. The method for preparing a dielectric layer of a field effect transistor device according to claim 1, characterized in that: The thickness of the thin layer of hafnium sulfide is 20-30 nm.

3. The method for preparing a dielectric layer of a field effect transistor device according to claim 1 or 2, characterized in that: The temperature of the thermal oxidation treatment is 130-170° C., and the time of the thermal oxidation treatment is 1.5-3.0 hours.

4. A method for preparing a field effect transistor device, characterized in that: The following steps are involved: peeling off the hafnium sulfide to obtain a thin layer of hafnium sulfide; then transferring the thin layer of hafnium sulfide to a polydimethylsiloxane stamp and performing a thermal oxidation treatment to obtain a hafnium oxide dielectric layer; transferring the hafnium oxide dielectric layer onto a carbon nanotube substrate, and then fabricating a transistor channel; Then, a source electrode, a drain electrode and a gate are prepared to obtain a field effect transistor device; The hafnium oxide dielectric layer includes a hafnium sulfide layer and a hafnium oxide layer; the carbon nanotube substrate includes a carbon nanotube layer, and during the transfer process, the hafnium oxide layer in the hafnium oxide dielectric layer is disposed on the carbon nanotube layer.

5. The method for preparing a field effect transistor device according to claim 4, characterized in that: The carbon nanotube substrate comprises a silicon layer, a silicon dioxide layer and a carbon nanotube layer in sequence.

6. The method for preparing a field effect transistor device according to claim 5, characterized in that: The thickness of the silicon dioxide layer is 200-400 nm.

7. The method for preparing a field effect transistor device according to any one of claims 4 to 6, characterized in that: The source electrode and the drain electrode are prepared by using photoresist, patterning by laser direct writing lithography technology and electron beam evaporation to prepare the source electrode and the drain electrode at the left and right ends of the carbon nanotube substrate.

8. The method for preparing a field effect transistor device according to claim 7, characterized in that: The source electrode and the drain electrode are Pd.

9. The method for preparing a field effect transistor device according to any one of claims 4 to 6, characterized in that: The preparation process of the gate is: using photoresist, through patterning processing of laser direct writing technology and electron beam evaporation, to prepare the gate on the hafnium sulfide layer of the hafnium oxide dielectric layer.

10. The method for preparing a field effect transistor device according to claim 9, characterized in that: The gate is Ti or Au.

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