Method for manufacturing a chip

Abstract

This application discloses a chip fabrication method applicable to the semiconductor technology field. The method includes attaching a wafer to a dicing tape. The dicing tape includes a first surface near the wafer and a barrier layer disposed on the first surface. The barrier layer extends from the first surface into the dicing tape, and the surface of the barrier layer near the wafer is flush with the first surface. The wafer includes dicing tracks, and the orthographic projection of the dicing tracks on the first surface is located within the area where the barrier layer is located. The dicing tracks of the wafer are then cut to divide the wafer into multiple chips. The technical solution of this application improves the precision of chip fabrication.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method for fabricating a chip. Background Technology

[0002] During the process of dicing wafers to form chips, dicing tape needs to be attached to the back of the wafer to fix it in place.

[0003] However, during the wafer dicing process, the dicing tape is easily cut incorrectly, which can cause defects such as air bubbles in the dicing tape, affecting the chip fabrication accuracy and subsequent chip bonding. Summary of the Invention

[0004] This application provides a method for fabricating a chip, which aims to improve the fabrication accuracy of the chip.

[0005] To achieve the above objectives, embodiments of this application provide the following technical solutions:

[0006] This application provides a method for fabricating a chip. The method includes attaching a wafer to a dicing tape. The dicing tape includes a first surface near the wafer and a barrier layer disposed on the first surface. The barrier layer extends from the first surface into the dicing tape, and the surface of the barrier layer near the wafer is flush with the first surface. The wafer includes dicing tracks, and the orthographic projection of the dicing tracks on the first surface is located within the area where the barrier layer is located. The dicing tracks of the wafer are then cut to diced the wafer into multiple chips.

[0007] The chip fabrication method provided in this application involves attaching a wafer to a dicing tape, and then cutting the wafer along the dicing path to divide it into multiple chips. A barrier layer is provided on the first surface of the dicing tape, with the surface of the barrier layer closest to the wafer flush with the first surface to ensure a tight fit between the wafer and the dicing tape, facilitating wafer fixation. Furthermore, the orthogonal projection of the dicing path onto the first surface lies within the area of ​​the barrier layer, thus protecting the dicing tape during the cutting process and preventing air bubbles caused by cutting from the dicing tape below the dicing path. This improves the chip fabrication accuracy and, consequently, the reliability of subsequent chip bonding.

[0008] In some embodiments, a plasma etching process is used to cut the dicing channels of the wafer, and the material of the barrier layer includes a conductive material.

[0009] In some embodiments, the material of the barrier layer includes at least one of copper, iron, or chromium.

[0010] In some embodiments, the width of the barrier layer is greater than the width of the cutting channel.

[0011] In some embodiments, along the width direction of the cutting channel, the boundaries of the opposite sides of the blocking layer extend beyond the boundaries of the opposite sides of the cutting channel.

[0012] In some embodiments, the ratio of the distance by which the boundary of the barrier layer extends beyond the boundary of the cutting channel to the width of the cutting channel ranges from 0.05 to 0.1.

[0013] In some embodiments, the orthographic projection of the wafer dicing paths on the first surface is a mesh shape, and the orthographic projection of the barrier layer on the first surface is a mesh shape.

[0014] In some embodiments, the above preparation method further includes attaching a frame to a dicing tape, the frame being disposed around the wafer, and a gap region being provided between the frame and the wafer. A barrier layer of the dicing tape is also disposed in the gap region.

[0015] In some embodiments, the shape of the barrier layer's orthographic projection on the first surface is a mesh. The mesh-like barrier layer includes a first barrier line extending along a first direction and a second barrier line extending along a second direction, the first and second directions intersecting and being parallel to the first surface, respectively. Both the first and second barrier lines extend into the gap region. Attached Figure Description

[0016] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0017] Figure 1 A flowchart illustrating a chip fabrication method provided in an embodiment of this application;

[0018] Figures 2-5 for Figure 1 The preparation method shown in the diagrams illustrates each step.

[0019] Figure 6 for Figure 5 A magnified view of the wafer at point M;

[0020] Figure 7 A schematic diagram of the structure of the cutting tape provided in an embodiment of this application;

[0021] Figure 8 This is a schematic diagram of the structure of the wafer, frame, and dicing tape provided for embodiments of this application. Detailed Implementation

[0022] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0023] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0024] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0025] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0026] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0027] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0028] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0029] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0030] In traditional chip packaging, dicing tape is applied to the back of the wafer before it is cut into chips along the dicing lines. Common dicing methods include plasma dicing, laser dicing, and mechanical dicing.

[0031] Plasma dicing, similar to plasma etching, uses high-temperature plasma to etch the chips apart, thus achieving the purpose of dicing the wafer. After the plasma etches the wafer apart, the silicon near the dicing tape around the dicing track may be over-etched by the plasma, resulting in bottom notching morphology defects.

[0032] Laser cutting, also known as laser ablation, is a non-contact processing method that uses a high-temperature, high-power laser to perform laser ablation cutting. The high-power laser used in laser ablation cutting generates significant heat during operation, which can affect the structure of the cutting tape used to hold the wafer at the bottom, causing the tape to deform.

[0033] Mechanical cutting is a method of cutting chips off wafers using blades; it is a contact-type separation process. However, mechanical cutting is prone to accidentally cutting the cutting tape, causing air bubbles to form in the tape.

[0034] Since the wafer at this stage is already a thinned wafer, the silicon thickness, roughness, and other parameters have been reduced to a very precise level to ensure the successful completion of the subsequent die-to-wafer hybrid bonding process. Issues such as the micro-displacement of the chip due to tape deformation, lateral etching of the silicon bottom, and contamination from the reaction of the tape with plasma all affect the chip fabrication precision, consequently impacting the bonding precision of the subsequent die-to-wafer hybrid bonding process.

[0035] To address the aforementioned issues, embodiments of this application provide a method for fabricating a chip that achieves high cleanliness and accuracy. Figure 1 A flowchart illustrating a chip fabrication method provided in an embodiment of this application; Figures 2-5 for Figure 1 The preparation method is illustrated with diagrams of each step. (See diagram for example.) Figure 1 As shown, the preparation method includes the following steps S1 to S2:

[0036] Step S1: As Figure 2As shown, wafer 1 is aligned and adhered to dicing tape 2. Dicing tape 2 includes a first surface 21 near wafer 1 and a barrier layer 3 disposed on the first surface 21. The barrier layer 3 extends from the first surface 21 into the dicing tape 2, and the surface of the barrier layer 3 near wafer 1 is flush with the first surface 21. That is, along the Z direction, the upper surface of the barrier layer 3 is neither higher nor lower than the first surface 21, to ensure a tight fit between wafer 1 and dicing tape 2, which is beneficial for fixing wafer 1 and protecting dicing tape 2.

[0037] The wafer includes a dicing track 10, which serves as the area for dicing wafer 1. During the process of aligning and attaching wafer 1 to the dicing tape 2, the dicing track 10 needs to be aligned with the barrier layer 3 on the dicing tape 2. The orthographic projection of the dicing track 10 onto the first surface 21 lies within the area where the barrier layer 3 is located. It can be understood that, along the X direction, the width of the barrier layer 3 is greater than or equal to the width of the dicing track 2, so as to protect the dicing tape 2 during the dicing process. Furthermore, a mask layer 4 is formed on the side of wafer 1 away from the dicing tape 2.

[0038] Step S2: As Figures 3-5 As shown, the dicing channel 10 of wafer 1 is cut to divide wafer 1 into multiple chips.

[0039] For example, wafer 1 can be cut using a plasma etching process, such as... Figure 3 As shown, on the side of the mask layer 4 away from the wafer 1, a photoresist layer 5 with a first opening 51 is formed by exposure and development. Along the Z direction, the first opening 51 is located directly above the dicing track 10. Then as... Figure 4 As shown, plasma etching is performed on the mask layer 4 and wafer 1 along the first opening 51 until the silicon at the bottom of the wafer is etched, forming a second opening 11 within wafer 1. Finally, as shown... Figure 5 As shown, by changing the process parameters of plasma etching, the silicon at the bottom of wafer 1 is etched through mask layer 4 until wafer 1 is completely cut to form multiple chips.

[0040] The chip fabrication method provided in this application involves attaching a wafer 1 to a dicing tape 2, and then dicing the dicing groove 10 of the wafer 1 to cut the wafer 1 into multiple chips. A barrier layer 3 is provided on the first surface 21 of the dicing tape 2. The surface of the barrier layer 3 closest to the wafer 1 is flush with the first surface 21 to ensure a tight fit between the wafer 1 and the dicing tape 2, which is beneficial for fixing the wafer 1. Furthermore, the orthogonal projection of the dicing groove 10 onto the first surface 21 lies within the area where the barrier layer 3 is located, preventing air bubble defects caused by cutting from occurring on the dicing tape 2 located below the dicing groove 10, thereby improving the chip fabrication accuracy and, consequently, the reliability of subsequent chip bonding.

[0041] In the above embodiments, such as Figures 2-5 As shown, a plasma etching process is used to cut the dicing path 10 of wafer 1. The material of the barrier layer 3 includes a conductive material. For example, the material of the barrier layer 3 includes at least one of the chemically stable copper (Cu), the inert metal iron (Fe) or chromium (Cr) with high conductivity and hardness. The conductive material does not include soft metals with high activity such as aluminum (Al) or tungsten (W).

[0042] In the above steps, the barrier layer 3 remains grounded. After the silicon at the bottom of wafer 1 is etched by plasma, the plasma comes into contact with the barrier layer 3 on the dicing tape 2. The plasma will not come into contact with the dicing tape 2, thus avoiding the dicing tape 2 being cut, which would cause bubble defects and changes in chemical properties. At the same time, since the plasma is guided away along the grounded metal barrier layer 3, it will not over-etch the silicon outside the dicing track 10 inside wafer 1, that is, there will be no lateral etching, which improves the reliability of the internal structure of wafer 1.

[0043] In some embodiments, laser cutting can be used to cut the dicing groove 10 of wafer 1. Optionally, in this case, the material of the barrier layer 3 is a heat-resistant material. Alternatively, mechanical cutting can be used to cut the dicing groove 10 of wafer 1. Optionally, in this case, the material of the barrier layer 3 is a material with higher strength. The barrier layer 3 provided in the above embodiments can protect the cutting tape 2 and prevent the cutting tape 2 located below the dicing groove 10 from generating bubble defects.

[0044] Figure 6 for Figure 5 A magnified view of the wafer at point M.

[0045] In some embodiments, such as Figure 6 As shown, along direction X, the width d1 of the barrier layer 3 is greater than the width d of the cutting channel 10. For example, the left boundary of the barrier layer 3 may extend beyond the left boundary of the cutting channel 10, and the right boundary of the barrier layer 3 may be flush with the right boundary of the cutting channel 10; or, the right boundary of the barrier layer 3 may extend beyond the right boundary of the cutting channel 10, and the left boundary of the barrier layer 3 may be flush with the left boundary of the cutting channel 10; or both boundaries of the barrier layer 3 may extend beyond both boundaries of the cutting channel 10.

[0046] The embodiments provided in this application are illustrated by taking the example that both sides of the barrier layer 3 extend beyond the two sides of the cutting path 10, that is, the projection of the cutting path 10 on the first surface 21 is completely located inside the barrier layer 3, so as to ensure the process window during the plasma etching process.

[0047] In some embodiments, such as Figure 6As shown, along direction X, the ratio of the distance d2 by which the boundary of the barrier layer 3 extends beyond the boundary of the dicing channel 10 to the width d of the dicing channel 10 ranges from 0.05 to 0.1. For example, the range of d2:d can be 0.05, 0.0625, 0.075, 0.0875, or 0.1. Setting the width ratio of the two in the range of 0.05 to 0.1 ensures that, during the plasma etching process on wafer 1, the plasma cannot come into contact with the dicing tape 2, further achieving the purpose of protecting the dicing tape 2.

[0048] Figure 7 This is a schematic diagram of the structure of the cutting tape provided in an embodiment of this application.

[0049] In some embodiments, such as Figure 7 As shown, the orthographic projection of the dicing track 10 on the first surface 21 of the wafer 1 is a mesh shape, and the orthographic projection of the barrier layer 3 on the first surface 21 is also a mesh shape. It can be understood that the morphology of the barrier layer 3 is consistent with the morphology of the dicing track 10. The dicing track 10 and the barrier layer 3 are aligned and set to achieve full protection of the cutting tape 2 located below the dicing track 10.

[0050] Figure 8 This is a schematic diagram of the structure of the wafer, frame, and dicing tape provided for embodiments of this application.

[0051] In some embodiments, such as Figure 8 As shown, the above-described fabrication method further includes attaching the frame 6 to the dicing tape 2 to fix the wafer 1. The frame 6 surrounds the wafer 1, protecting it from potential external damage. A gap region exists between the frame 6 and the wafer 1, and the barrier layer 3 of the dicing tape 2 is also disposed in this gap region. When the dicing paths 10 of the wafer 1 are etched using plasma etching, the gap region will also be etched by the plasma. Since the barrier layer 3 is also disposed within the dicing tape 2 in the gap region, the plasma can be conducted away by grounding the barrier layer 3, ensuring that the dicing tape 2 is not damaged. Furthermore, this ensures that the inner edge of the wafer 1 is not over-etched, improving the chip fabrication accuracy.

[0052] In some embodiments, such as Figure 7As shown, the shape of the barrier layer 3 projected onto the first surface 21 is a mesh. The mesh barrier layer 3 includes a first barrier line 31 extending along a first direction X and a second barrier line 32 extending along a second direction Y. The first direction X and the second direction Y intersect and are parallel to the first surface 21, respectively. The embodiment provided in this application is illustrated with the first direction X and the second direction Y being perpendicular as an example. Both the first barrier line 31 and the second barrier line 32 extend to the gap region. It can be understood that along the first direction X, the first barrier line 31 penetrates the cutting tape 2, and along the second direction Y, the second barrier line 32 also penetrates the cutting tape 2. The mesh barrier layer 3 can be easily aligned with the cutting track 10, improving process accuracy.

[0053] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating a chip, characterized in that, include: A wafer is attached to a dicing tape, the dicing tape including a first surface near the wafer and a barrier layer disposed on the first surface, the barrier layer extending from the first surface into the dicing tape, and the surface of the barrier layer near the wafer being flush with the first surface; the barrier layer is made of a conductive material and is grounded; the wafer includes dicing tracks, the orthographic projection of the dicing tracks on the first surface being located within the area where the barrier layer is located; The wafer is cut into multiple chips by using a plasma etching process to cut the dicing channels.

2. The preparation method according to claim 1, characterized in that, The material of the barrier layer includes at least one of copper, iron, or chromium.

3. The preparation method according to claim 1, characterized in that, The width of the barrier layer is greater than the width of the cutting channel.

4. The preparation method according to claim 3, characterized in that, Along the width direction of the cutting channel, the boundaries of the opposite sides of the blocking layer extend beyond the boundaries of the opposite sides of the cutting channel.

5. The preparation method according to claim 4, characterized in that, The ratio of the distance by which the boundary of the blocking layer extends beyond the boundary of the cutting channel to the width of the cutting channel ranges from 0.05 to 0.

1.

6. The preparation method according to claim 1, characterized in that, The dicing paths of the wafer are projected onto the first surface in a mesh-like shape, and the barrier layer is also projected onto the first surface in a mesh-like shape.

7. The preparation method according to claim 1, characterized in that, The preparation method further includes: The frame is attached to the cutting tape, the frame is arranged around the wafer, and there is a gap area between the frame and the wafer; The blocking layer of the cutting tape is also provided in the gap area.

8. The preparation method according to claim 7, characterized in that, The shape of the barrier layer projected onto the first surface is a mesh; The mesh-like barrier layer includes a first barrier line extending in a first direction and a second barrier line extending in a second direction, the first direction and the second direction intersecting and being parallel to the first surface, respectively; Both the first blocking line and the second blocking line extend into the gap region.

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