One-to-eight power division network based on ceramic packaging

Abstract

The invention discloses a one-to-eight power division network based on ceramic packaging, which adopts a Wilkinson power divider in a three-stage framework strip line form, and comprises a top metal layer, a middle strip wiring metal layer, a bottom metal layer and a ball mounting metal layer from top to bottom, and a dielectric substrate is clamped between every two metal layers. The top metal layer is provided with an input end and a plurality of isolation resistors, the middle strip-shaped wiring metal layer is provided with power divider network wiring, the input end and the plurality of isolation resistors are respectively connected with the power divider network wiring through metalized through holes, and the ball mounting metal layer is provided with a plurality of output ends. And each output end is connected with the power divider network routing through a metalized through hole. Through the multi-layer structure design, the Wilkinson power divider design, the metalized through hole and isolation resistor design and the optimization of packaging and connecting modes, the problems of miniaturization, high integration level, high reliability and low manufacturing cost of the power division network are successfully solved, and the power division network is suitable for various ceramic packaging applications.

Description

Technical Field

[0001] The present application relates to the field of radio frequency communication technology, and in particular to a one-to-eight power division network based on ceramic packaging. Background Art

[0002] With the development of miniaturization and multifunctionality of electronic devices, the demand for highly integrated packaging technology is increasing. A technology called "System in Package" (SIP) is widely used in mobile devices, wireless communications, aerospace and other fields because it can integrate multiple semiconductor chips or passive devices in one package. By eliminating the connection lines and space required between different components, SIP technology not only reduces the overall size of the system, but also reduces the cost of assembly and connection, and reduces the use of system-level connectors, cables and printed circuit boards, thereby effectively reducing the total cost of the system. As the market's requirements for the size and performance of electronic products continue to increase, SIP technology is moving towards higher integration, greater flexibility, customization and greater cost-effectiveness, and its application areas are also expanding.

[0003] However, in the field of RF communication, especially when it comes to the design of microstrip power splitter networks, existing solutions still face many challenges. Microstrip power splitter networks are multi-port passive microwave networks that are mainly used to evenly distribute the power of input signals to multiple output ports. Traditional microstrip power splitter networks are laid out on the circuit board of the RF module in the form of microstrip lines. This layout method is limited by the dielectric constant of the circuit board material, resulting in a relatively large network size, and the network routing is easily affected by the device layout. In addition, in order to adapt to complex circuit designs, it is often necessary to increase the number of layers of the circuit board, which undoubtedly increases the processing difficulty and process complexity of multi-layer microstrip boards. Although chip-level power splitters are easy to install and use, they are difficult to package and integrate with other devices due to the limitations of their packaging form. In particular, for power splitter networks that need to achieve one-to-eight or more branches, if chip-level power splitters are used, multiple power splitter chips need to be combined, which not only increases the implementation size, reduces the integration, but also increases the cost of the device.

[0004] Therefore, developing a new power division network that can be flexibly adjusted according to the size of the packaging shell and integrates passive microwave networks and active devices has become a technical problem that urgently needs to be solved. Summary of the invention

[0005] The purpose of this application is to overcome the existing technical defects and provide a one-to-eight power division network based on ceramic packaging. Through multi-layer structure design, Wilkinson power divider design, metallized through-hole and isolation resistor design, and optimization of packaging and connection methods, the problems of miniaturization, high integration, high reliability and low manufacturing cost of the power division network are successfully solved.

[0006] The purpose of this application is achieved through the following technical solutions:

[0007] In the first aspect, the present application proposes a one-to-eight power division network based on ceramic packaging, wherein the one-to-eight power division network is a Wilkinson power divider in the form of a three-level stripline architecture, which includes a top metal layer, an intermediate stripline metal layer, a bottom metal layer, and a ball-planting metal layer from top to bottom, and a dielectric substrate is sandwiched between every two metal layers;

[0008] An input terminal and a plurality of isolation resistors are arranged on the top metal layer, a power divider network routing is arranged on the middle strip routing metal layer, and the input terminal and the plurality of isolation resistors are respectively connected to the power divider network routing through metallized through holes;

[0009] A plurality of output terminals are arranged on the ball planting metal layer, and each output terminal is connected to a power divider network wiring through a metallized through hole.

[0010] In a possible implementation manner, the input terminal is connected to the external chip through gold wire bonding.

[0011] In a possible implementation manner, the dielectric substrate is an alumina ceramic substrate having a dielectric constant of 9.8.

[0012] In a possible implementation manner, the thickness of the first dielectric substrate and the second dielectric substrate from top to bottom is 0.75 mm, and the thickness of the third dielectric substrate is 0.5 mm.

[0013] In a possible implementation manner, a kovar frame is welded to the upper surface of the second dielectric substrate and a kovar cover plate is sealed and welded in parallel.

[0014] In a possible implementation, a high lead ball is implanted at the bottom of the third dielectric substrate, and high and low frequency interconnections are performed with external circuits in the form of BGA.

[0015] In a possible implementation manner, a solder resist layer is disposed on the lower surface of the metallized through hole.

[0016] In a possible implementation manner, the number of isolation resistors is 7.

[0017] In a possible implementation manner, the number of output terminals is 8.

[0018] The above-mentioned main scheme of the present application and its further options can be freely combined to form multiple schemes, all of which are schemes that can be adopted and claimed for protection in the present application; and in the present application, (non-conflicting options) options and other options can also be freely combined. After understanding the scheme of the present application, those skilled in the art can understand that there are multiple combinations based on the prior art and common knowledge, all of which are technical schemes to be protected by the present application, and they are not exhaustively listed here.

[0019] The present application discloses a one-to-eight power splitter network based on ceramic packaging, which adopts a three-level stripline Wilkinson power splitter, which includes a top metal layer, an intermediate stripline metal layer, a bottom metal layer, and a ball-planting metal layer from top to bottom, and a dielectric substrate is sandwiched between every two metal layers. An input terminal and multiple isolation resistors are arranged on the top metal layer, and a power splitter network routing is arranged on the intermediate stripline metal layer. The input terminal and multiple isolation resistors are respectively connected to the power splitter network routing through metallized through holes, and multiple output terminals are arranged on the ball-planting metal layer, and each output terminal is respectively connected to the power splitter network routing through metallized through holes. Through the multi-layer structure design, Wilkinson power splitter design, metallized through hole and isolation resistor design, and the optimization of packaging and connection methods, the problems of miniaturization, high integration, high reliability and low manufacturing cost of the power splitter network are successfully solved, and it is suitable for a variety of ceramic packaging applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A schematic diagram of a one-to-eight power division network based on ceramic packaging proposed in an embodiment of the present application is shown.

[0022] Figure 2 A side view of a one-to-eight power division network proposed in an embodiment of the present application is shown.

[0023] Figure 3 A top view of a one-to-eight power division network proposed in an embodiment of the present application is shown.

[0024] Figure 4 A schematic structural diagram of a multi-layer dielectric substrate is shown.

[0025] Figure 5 A schematic diagram of welding the isolation resistor proposed in an embodiment of the present application is shown.

[0026] Figure 6A schematic diagram of the top metal layer proposed in an embodiment of the present application is shown.

[0027] Figure 7 A schematic diagram of the intermediate strip routing metal layer proposed in an embodiment of the present application is shown.

[0028] Figure 8 A schematic diagram of a ball implanting metal layer proposed in an embodiment of the present application is shown.

[0029] Figure numerals: 1-input terminal; 2-isolation resistor; 3-power divider network wiring; 4-output terminal. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0031] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0032] In the prior art, the traditional microstrip power splitter network is laid out on the circuit board of the RF module in the form of microstrip lines. This layout method is limited by the dielectric constant of the circuit board material, resulting in a relatively large network size, and the network routing is easily affected by the device layout. In addition, in order to adapt to complex circuit designs, it is often necessary to increase the number of layers of the circuit board, which undoubtedly increases the processing difficulty and process complexity of the multi-layer microstrip board. Although the chip-level power splitter is easy to install and use, it is difficult to achieve packaging integration with other devices due to the limitations of its packaging form. In particular, for power splitter networks that need to achieve one-to-eight or more branches, if a chip-level power splitter is used, it needs to be composed of multiple power splitter chips, which not only increases the implementation size and reduces the integration, but also increases the cost of the device.

[0033] In order to solve the above-mentioned technical problems, an embodiment of the present application proposes a one-to-eight power division network based on ceramic packaging, which can be applied to miniaturized ceramic packaging. Through multi-layer structure design, Wilkinson power divider design, metallized through-hole and isolation resistor design, and optimization of packaging and connection methods, the problems of miniaturization, high integration, high reliability and low manufacturing cost of the power division network are successfully solved, which will be described in detail below.

[0034] Please refer to Figure 1 , Figure 1A schematic diagram of a one-to-eight power division network based on ceramic packaging proposed in an embodiment of the present application is shown. The network is applied to the technical field of miniaturized ceramic packaging. The one-to-eight power division network is a Wilkinson power divider in the form of a three-level architecture stripline, which includes a top metal layer, an intermediate stripline metal layer, a bottom metal layer, and a ball-planting metal layer from top to bottom, and a dielectric substrate is sandwiched between every two metal layers;

[0035] An input terminal 1 and a plurality of isolation resistors 2 are arranged on the top metal layer, a power divider network routing 3 is arranged on the middle strip routing metal layer, and the input terminal 1 and the plurality of isolation resistors 2 are respectively connected to the power divider network routing 3 through metallized through holes;

[0036] A plurality of output terminals 4 are arranged on the ball implanting metal layer, and each output terminal 4 is connected to a power divider network wiring 3 through a metallized through hole.

[0037] Figure 2 FIG. 4 shows a side view of a one-to-eight power division network proposed in an embodiment of the present application, and FIG. Figure 3 A top view of the one-to-eight power division network proposed in an embodiment of the present application is shown, the number of isolation resistors 2 is 7, the number of output terminals 4 is 8, the input terminal 1 is located on the top metal layer, and can be connected to other chips through gold wire bonding, the isolation resistor 2 pad is located on the top metal layer, and is connected to the power divider network routing 3 through metallized through holes, there are 7 isolation resistors 2 in total, which are located on the top metal layer and are connected to the power divider network routing 3 through metallized through holes.

[0038] It is set in the middle strip routing metal layer for signal transmission. Each power divider adopts a one-to-two equal-division in-phase design. According to the dielectric constant and thickness of the substrate, the required quarter-wavelength length of each power divider is calculated. The microstrip routing of the two branches has the same width and length.

[0039] In the bottom metal layer, metallized isolation holes are arranged near the transmission path to improve the shielding effect. The output terminals 4 of the ball implantation metal layer are 8 in total, which are connected to the power divider network wiring 3 through metallized through holes to achieve interconnection with external circuits.

[0040] The input terminal 1 and the isolation resistor 2 are connected to the power divider network routing 3 of the middle strip routing metal layer through the metallized through hole, and the output terminal 4 is connected to the power divider network routing 3 of the middle strip routing metal layer through the metallized through hole, and finally leads to the ball implantation metal layer to realize the interconnection with the external circuit. Figure 6 A schematic diagram of the top metal layer proposed in an embodiment of the present application is shown, Figure 7 A schematic diagram of the intermediate strip-shaped routing metal layer proposed in an embodiment of the present application is shown. Figure 8 A schematic diagram of a ball implanting metal layer proposed in an embodiment of the present application is shown.

[0041] Each level of network routing adopts at least 3 S-bends to further reduce the size while ensuring good matching and amplitude consistency. The isolation resistor 2 does not use an embedded resistor, but places the pad on the top metal layer through a metallized through-hole to facilitate welding of the isolation resistor 2, which can reduce processing costs and process complexity. Figure 5 A welding schematic diagram of the isolation resistor proposed in an embodiment of the present application is shown, in which a resistor is welded to a circuit board, surrounded by multiple pins and connecting wires, and the two ends of the resistor are respectively welded to two pads, which are metal contact points on the circuit board. The two ends of the resistor are connected to the pads through pins, and the surrounding gray lines represent the connecting wires on the circuit board, which are used to connect different components.

[0042] The input terminal 1 is connected to the external chip through gold wire bonding.

[0043] The dielectric substrate is an alumina ceramic substrate with a dielectric constant of 9.8.

[0044] The dielectric substrate material is an alumina ceramic substrate with a dielectric constant of 9.8, which has good thermal conductivity and chemical stability and a low thermal expansion coefficient.

[0045] Figure 4 A schematic diagram of the structure of a multi-layer dielectric substrate is shown, in which five via holes (Via01 to Via05) are marked. These holes are used to connect metal layers between different layers. The position of each via hole and the connected metal layer are clearly marked in the figure.

[0046] The thickness of the first dielectric substrate and the second dielectric substrate from top to bottom is 0.75 mm, the thickness of the third dielectric substrate is 0.5 mm, and the total thickness of the substrate is 2 mm.

[0047] A ferrous frame is welded to the upper surface of the second dielectric substrate and a ferrous cover plate is sealed and welded in parallel.

[0048] The Kovar enclosure frame and the cover plate are welded to the upper surface of the second dielectric substrate to achieve airtight packaging. They are welded to the L03 alumina ceramic substrate using silver-copper to ensure a large temperature gradient during welding.

[0049] A high-lead ball is implanted at the bottom of the third-layer dielectric substrate, which is interconnected with the external circuit in high and low frequency through BGA.

[0050] The high-lead ball is implanted at the bottom of the third-layer dielectric substrate and is interconnected with the external circuit in high and low frequency form through BGA. The welding condition is that the plating of the welding area can meet the 183℃ low-lead reflow soldering.

[0051] The metallized through hole is provided with a solder resist layer on the lower surface floor.

[0052] Metallized through holes are set on the lower surface floor to avoid short circuits and a solder resist layer is provided.

[0053] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0054] First, through multi-layer structure design and optimized layout, the size of the entire power division network is significantly reduced, meeting the demand for miniaturization of modern electronic equipment. At the same time, multiple functional modules are integrated on a ceramic substrate, reducing the complexity of external connections and assembly, and improving overall integration.

[0055] Second, the alumina ceramic substrate with a dielectric constant of 9.8 is selected, which has good high-frequency characteristics and is suitable for RF applications. In addition, the low loss characteristics of the alumina ceramic substrate help maintain signal integrity and transmission efficiency.

[0056] Third, the design structure is simple, avoiding complex processes and difficult processing, reducing manufacturing costs and production difficulties. At the same time, it is adapted to modern surface mounting technology, can be mass-produced, and improves production efficiency and consistency.

[0057] Fourth, by welding the ferrite frame and parallel sealing the ferrite cover, the airtight packaging is achieved to protect the internal circuit from the external environment. The alumina ceramic substrate with good thermal conductivity and chemical stability is selected to improve the reliability and life of the entire power division network.

[0058] In summary, the present application discloses a one-to-eight power division network based on ceramic packaging, which adopts a three-level structure stripline form Wilkinson power divider, which includes a top metal layer, an intermediate stripline routing metal layer, a bottom metal layer, and a ball-planting metal layer from top to bottom, and a dielectric substrate is sandwiched between every two metal layers. An input terminal and multiple isolation resistors are arranged on the top metal layer, and a power divider network routing is arranged on the intermediate stripline routing metal layer. The input terminal and multiple isolation resistors are respectively connected to the power divider network routing through metallized through holes, and multiple output terminals are arranged on the ball-planting metal layer, and each output terminal is respectively connected to the power divider network routing through metallized through holes. Through the multi-layer structure design, Wilkinson power divider design, metallized through hole and isolation resistor design, and the optimization of packaging and connection methods, the problems of miniaturization, high integration, high reliability and low manufacturing cost of the power division network are successfully solved, and it is suitable for a variety of ceramic packaging applications.

[0059] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A one-to-eight power division network based on ceramic packaging, characterized in that: The one-to-eight power division network is a Wilkinson power divider in the form of a three-level stripline architecture, which includes a top metal layer, a middle stripline metal layer, a bottom metal layer, and a ball-planting metal layer from top to bottom, and a dielectric substrate is sandwiched between every two metal layers; An input terminal and a plurality of isolation resistors are arranged on the top metal layer, a power divider network routing is arranged on the middle strip routing metal layer, and the input terminal and the plurality of isolation resistors are respectively connected to the power divider network routing through metallized through holes; A plurality of output terminals are arranged on the ball planting metal layer, and each output terminal is connected to a power divider network wiring through a metallized through hole.

2. The one-to-eight power division network according to claim 1, characterized in that: The input terminal is connected to the external chip through gold wire bonding.

3. The one-to-eight power division network according to claim 1, characterized in that: The dielectric substrate is an alumina ceramic substrate with a dielectric constant of 9.

8.

4. The one-to-eight power division network according to claim 1, characterized in that: The thickness of the first dielectric substrate and the second dielectric substrate from top to bottom is 0.75 mm, and the thickness of the third dielectric substrate is 0.5 mm.

5. The one-to-eight power division network as claimed in claim 4, characterized in that: A ferrous frame is welded to the upper surface of the second dielectric substrate and a ferrous cover plate is sealed and welded in parallel.

6. The one-to-eight power division network according to claim 4, characterized in that: A high-lead ball is implanted at the bottom of the third-layer dielectric substrate, which is interconnected with the external circuit in high and low frequency through BGA.

7. The one-to-eight power division network according to claim 1, characterized in that: The metallized through hole is provided with a solder resist layer on the lower surface floor.

8. The one-to-eight power division network according to claim 1, characterized in that: The number of isolation resistors is 7.

9. The one-to-eight power division network according to claim 1, characterized in that: The number of output terminals is 8.

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