A multi-modal sequential switch shunt circuit and its fault handling method

Abstract

The application provides a kind of including power switch MOS tube Q1, power switch MOS tube Q2, first drive module, second drive module, enable and fault monitoring module, enable and voltage limiting control module, solar cell, line parasitic inductance L x And bus capacitor C.The application also provides a fault response method of a multi-modal sequential switch shunt circuit.The beneficial effects of the application are as follows: it has multiple working modes, can work in S2R mode, high-efficiency S3R mode, voltage-limited S2R mode and forced power supply mode according to setting or control signals, responds to different solar cell configurations and changes in space environment, and is suitable for more scenarios.

Description

Technical Field

[0001] This invention relates to spacecraft, and more particularly to a multimodal sequential switching shunt circuit and its fault handling method. Background Technology

[0002] With the growing demand for broadband low-Earth orbit (LEO) satellites, commercial satellites have become a hot topic in satellite development. Compared to traditional aerospace power supplies, commercial satellite power supplies are characterized by small size, modularity, standardization, mass production capability, shorter lifespan, and greater flexibility. In the early stages of commercial satellite development, the number of satellites deployed was small, and the main design goals were light weight, small size, and low price. A power supply architecture based on sequential shunt switching circuits (S3R) was generally adopted. However, the design still needed to consider issues such as short-circuit faults in the switching transistors, large instantaneous current during shunt switching, and heat dissipation. Driven by the development of third-generation semiconductors, switching transistors have higher voltage withstand capabilities, and sequential switching circuits (S2R) have gradually returned to prominence. However, due to the inductance of the conductors in the circuit, the voltage stress on the switching transistors during turn-off is significant. Simultaneously, with the continuous deployment of commercial satellites, tens of thousands of satellites will bring risks such as collisions and obstructions. Even in LEO, the output voltage of solar cells will fluctuate. Therefore, a power supply circuit that can adapt to voltage fluctuations and is suitable for a wider range of applications is needed. Summary of the Invention

[0003] To address the problems in the prior art, this invention provides a multimodal sequential switching shunt circuit and a fault handling method thereof.

[0004] This invention provides a multi-mode sequential switching shunt circuit, including power switching MOSFETs Q1 and Q2, a first driving module, a second driving module, an enable and fault monitoring module, an enable and voltage limiting control module, a solar cell, and a line parasitic inductance L. x And bus capacitor C, the line parasitic inductance L x One end of the circuit is connected to the positive electrode of the solar cell, and the parasitic inductance L of the circuit is... x The other end is connected to the drain of the power switch MOSFET Q1, and the source of the power switch MOSFET Q1 is connected to the bus voltage U. BUS The positive terminal of the bus capacitor C is connected to the source of the power switch MOSFET Q1, and the other end of the bus capacitor C is connected to the bus voltage U. BUSThe negative terminal of the power switch MOSFET Q1 is connected to the output terminal of the first driving module. The input terminal of the first driving module is connected to the first driving signal. The input terminal of the first driving module is connected to the output terminal of the enable and fault monitoring module. The input terminal of the enable and fault monitoring module is connected to the first enable signal. The input terminal of the enable and fault monitoring module is connected to the input terminal of the enable and voltage limiting control module and the output terminal of the second driving module, respectively. The input terminal of the enable and voltage limiting control module is connected to the drain of the power switch MOSFET Q1. The input terminal of the enable and voltage limiting control module is connected to the second enable signal. The output terminal of the enable and voltage limiting control module is connected to the input terminal of the second driving module. The input terminal of the second driving module is connected to the second driving signal. The output terminal of the second driving module is connected to the gate of the power switch MOSFET Q2. The drain of the power switch MOSFET Q2 is connected to the drain of the power switch MOSFET Q1. The source of the power switch MOSFET Q2 is grounded.

[0005] As a further improvement of the present invention, the first driving module is controlled by the enable and fault monitoring module and the first driving signal, the enable and fault monitoring module is controlled by the first enable signal and the fault monitoring signal, the enable and voltage limiting control module is controlled by the second enable signal and the voltage limiting signal, and the fault monitoring signal is determined by the voltage U at the power transistor connection point. SA and the gate-source voltage U of the power switching MOSFET Q2 GS2 The judgment logic is generated by the voltage limiting signal, which is determined by the voltage U at the connection point of the power transistor. SA Its threshold voltage is determined and generated.

[0006] As a further improvement of the present invention, the first driving signal and the second driving signal can operate in PWM state, and the pulse width is controlled by the output signal of the bus error method, so that the bus voltage or current can achieve closed-loop control.

[0007] This invention also provides a fault handling method for a multi-mode sequential switch shunt circuit, which provides the multi-mode sequential switch shunt circuit as described above. The multi-mode sequential switch shunt circuit has four operating modes: S2R mode, high-efficiency S3R mode, voltage-limited S2R mode, and forced power supply mode. Any one of the S2R mode, high-efficiency S3R mode, voltage-limited S2R mode, and forced power supply mode can be selected according to the input quantity.

[0008] As a further improvement of the present invention, the input quantities include any one or any combination thereof of orbital parameters, on-orbit data, and solar cell configuration.

[0009] As a further improvement of the present invention, in the S2R mode, the second drive signal is low, the second enable signal is set to "disable", the power switch MOSFET Q2 is in the off state and is not controlled by the output signal of the bus error detector, the first drive signal is PWM, the first enable signal is set to "disable", the power switch MOSFET Q1 is in the PWM state and is controlled by the first drive signal, the first drive signal is controlled by the output signal of the bus error detector;

[0010] During monitoring, the voltage detection circuit determines the voltage U at the connection point of the power transistor in the first voltage detection step. SA To determine if the power switch MOSFET Q2 has a short circuit fault, if the voltage at the connection point of the power transistor U... SA Less than the threshold voltage U th1 If so, it is considered that the power switch MOSFET Q2 has a short circuit fault;

[0011] The solution is to disconnect the power switch MOSFET Q1 controlled by the enable and fault monitoring module to prevent the power switch MOSFET Q2 from pulling down the bus voltage.

[0012] As a further improvement of the present invention, in the high-efficiency S3R mode, the second drive signal is PWM, the second enable signal is set to "disable", the power switch MOSFET Q2 is in PWM state and is controlled by the second drive signal. The second drive signal is controlled by the output signal of the bus error method device. The first drive signal is PWM, the first enable signal is set to "disable", the power switch MOSFET Q1 is also in PWM state and is controlled by the first drive signal. The switching logic of the first drive signal and the switching logic of the second drive signal are mutually "NOT" logic, realizing the function of an ideal diode.

[0013] During monitoring, when the drive voltage of the power switch MOSFET Q2 is low, i.e., the gate-source voltage U of the power switch MOSFET Q2 is low... GS2 Less than the threshold voltage U th2 At this time, the drain-source voltage of the power switch MOSFET Q2 is still low, that is, the voltage U at the connection point of the power transistor is low. SA Less than the threshold voltage U th1 If so, it is determined that a short circuit fault has occurred in the power switch MOSFET Q2;

[0014] The solution is to disconnect the power switch MOSFET Q1 controlled by the enable and fault monitoring module to prevent the power switch MOSFET Q2 from short-circuiting the bus and thus achieve fault isolation.

[0015] As a further improvement of the present invention, in the voltage-limited S2R mode, the second drive signal is low, the second enable signal is set to "enable", the first drive signal is PWM, and the first enable signal is set to "disable".

[0016] During monitoring, when the gate-source voltage U of the power switch MOSFET Q2... GS2 Less than the threshold voltage U th3 Furthermore, the voltage U at the power transistor connection point SA Less than the threshold voltage U th1 When this occurs, it is determined that a short circuit fault has occurred in the power switch MOSFET Q2;

[0017] The solution is to disconnect the power switch MOSFET Q1 controlled by the enable and fault monitoring module.

[0018] As a further improvement of the present invention, in the voltage-limited S2R mode, the voltage U at the connection point of the power transistor is detected by a second voltage detector. SA If there is a voltage exceeding the threshold voltage U th1 In such cases, the enable and voltage limiting control module enables the power switch MOSFET Q2 to operate in the linear region, which is equivalent to a variable resistor, reducing the input voltage and preventing overvoltage stress damage to the power switch MOSFETs Q1 and Q2.

[0019] As a further improvement of the present invention, in the forced power supply mode, the second drive signal is low, the second enable signal is set to "disable", the first drive signal is arbitrary, and the first enable signal is set to "enable". When the control circuit or protection circuit fails, causing the control signal to be unable to control the switching transistor, the control power switch MOS transistor Q1 is turned on to control the forced power supply of the solar cell in that circuit, thereby avoiding solar energy loss in that circuit due to control circuit failure.

[0020] The beneficial effects of this invention are:

[0021] 1. It has multiple operating modes and can operate in S2R mode, high-efficiency S3R mode, voltage-limited S2R mode and forced power supply mode according to the setting or control signal, so as to cope with different solar cell configurations and space environment changes and be suitable for more scenarios.

[0022] 2. It has monitoring and fault response strategies for short-circuit faults in switches, which improves the reliability of functional circuits. Moreover, the detection circuits are all voltage detection circuits, which are simple and have low losses.

[0023] 3. Fewer components, higher efficiency. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other solutions can be obtained based on these drawings without creative effort.

[0025] Figure 1(a) is a diagram of the multi-mode sequential switch shunt circuit of the present invention.

[0026] Figure 1(b) shows the modal control logic.

[0027] Figure 2(a) shows the S2R mode of the multimode sequential switching shunt circuit.

[0028] Figure 2(b) shows the S2R modal fault monitoring and response strategy.

[0029] Figure 3(a) shows the efficient S3R mode of the multimode sequential switching shunt circuit.

[0030] Figure 3(b) shows the efficient S3R modal fault monitoring and response strategy.

[0031] Figure 4(a) shows the voltage-limiting S2R mode of the multi-mode sequential switching shunt circuit.

[0032] Figure 4(b) shows the monitoring and response strategy for the voltage-limited S2R mode fault.

[0033] Figure 5 It is the forced power supply mode of the multi-mode sequential switching shunt circuit. Detailed Implementation

[0034] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0035] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting the scope of protection of this invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0036] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0037] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0038] As shown in Figure 1(a), a multi-mode sequential switching shunt circuit includes a power switch MOSFET Q1, a power switch MOSFET Q2, a first drive module 102, a second drive module 202, an enable and fault monitoring module 101, an enable and voltage limiting control module 201, a solar cell 300, and a line parasitic inductance L. x And bus capacitor C, the line parasitic inductance L x One end of the circuit is connected to the positive electrode of the solar cell, and the parasitic inductance L of the circuit is... x The other end is connected to the drain of the power switch MOSFET Q1, and the source of the power switch MOSFET Q1 is connected to the bus voltage U. BUS The positive terminal of the bus capacitor C is connected to the source of the power switch MOSFET Q1, and the other end of the bus capacitor C is connected to the bus voltage U. BUS The negative terminal of the power switch MOSFET Q1 is connected to the output terminal of the first driving module 102. The input terminal of the first driving module 102 is connected to the first driving signal. The input terminal of the first driving module 102 is connected to the output terminal of the enable and fault monitoring module 101. The input terminal of the enable and fault monitoring module 101 is connected to the first enable signal. The input terminal of the enable and fault monitoring module 101 is connected to the input terminal of the enable and voltage limiting control module 201 and the output terminal of the second driving module 202, respectively. The input terminal of the power switch MOSFET Q1 is connected to the drain of the power switch MOSFET Q1. The input terminal of the enable and voltage limiting control module 201 is connected to the second enable signal. The output terminal of the enable and voltage limiting control module 201 is connected to the input terminal of the second drive module 202. The input terminal of the second drive module 202 is connected to the second drive signal. The output terminal of the second drive module 202 is connected to the gate of the power switch MOSFET Q2. The drain of the power switch MOSFET Q2 is connected to the drain of the power switch MOSFET Q1. The source of the power switch MOSFET Q2 is grounded.

[0039] Furthermore, the first drive module 102 is controlled by the enable and fault monitoring module 101 and the first drive signal; the enable and fault monitoring module 101 is controlled by the first enable signal and the fault monitoring signal; the enable and voltage limiting control module 201 is controlled by the second enable signal and the voltage limiting signal; and the fault monitoring signal is determined by the voltage U at the power transistor connection point. SA and the gate-source voltage U of the power switching MOSFET Q2 GS2 The judgment logic is generated by the voltage limiting signal, which is determined by the voltage U at the connection point of the power transistor. SA Its threshold voltage is determined and generated.

[0040] Furthermore, the first and second drive signals can operate in PWM (Pulse Width Modulation) mode, with the pulse width controlled by the output signal of the bus error controller, enabling closed-loop control of the bus voltage or current.

[0041] Furthermore, the control signals corresponding to the mode settings are given in Figure 1(b), and the mode settings can be made according to inputs such as orbit parameters, on-orbit data, and solar cell configuration. For example, the S2R mode is more suitable for high-voltage, low-current solar cell configurations; the voltage-limited S2R mode can be selected for low-orbit applications with frequent shadow entry and exit; the high-efficiency S3R mode is more reliable for low-voltage, high-current solar cell configurations; and the forced power supply mode can be used to ensure that the power supply of this circuit is not lost in case of faults such as overvoltage protection malfunction.

[0042] This invention also provides a fault handling method for a multi-mode sequential switch shunt circuit. Based on the aforementioned multi-mode sequential switch shunt circuit, as shown in Figure 1(b), this multi-mode sequential switch shunt circuit has four operating modes: S2R mode, high-efficiency S3R mode, voltage-limited S2R mode, and forced power supply mode, as shown in Figures 2(a), 3(a), and 4(a) respectively. Figure 5 The diagram provides the key signals for fault monitoring, with modules and signals not involved in control highlighted in gray. Fault monitoring methods and corresponding strategies are presented in Figures 2(b), 3(b), and 4(b).

[0043] Furthermore, as shown in Figure 1(b), the control logic for each mode is as follows:

[0044] High-efficiency S3R mode: The first drive signal is PWM, the first enable signal is "disable", the second drive signal is PWM, and the second enable signal is "disable".

[0045] S2R mode: The first drive signal is PWM, the first enable signal is "disable", the second drive signal is low, and the second enable signal is "disable".

[0046] Forced power supply mode: The first drive signal is arbitrary, the first enable signal is "enable", the second drive signal is low, and the second enable signal is "disable".

[0047] Voltage-limited S2R mode: The first drive signal is PWM, the first enable signal is "disable", the second drive signal is low, and the second enable signal is "enable".

[0048] Furthermore, as shown in Figure 2(a), in the S2R mode, the second power signal is set to "disable," and control Q2 is in the off state, unaffected by the output signal of the bus error detector. The power switch MOSFET Q1 is in PWM mode, controlled by the first drive signal, which is controlled by the output signal of the bus error detector. The voltage detection circuit determines the voltage U detected by the second voltage detector. SA To determine if the power switch MOSFET Q2 has a short circuit fault, i.e., if the voltage U SA Less than the judgment threshold voltage U th1 If a short circuit fault is detected in power switch MOSFET Q2, the enable and fault monitoring module 101 will control power switch MOSFET Q1 to disconnect, preventing power switch MOSFET Q2 from pulling the bus low (bus de-energizing). Threshold voltage U th1 The voltage stress of power switching MOSFETs Q1 and Q2 should not exceed the voltage stress of power switching MOSFETs Q1 and Q2, with a certain margin.

[0049] Furthermore, as shown in Figure 3(a), the high-efficiency S3R mode operates in PWM mode, controlled by a second drive signal, which in turn is controlled by the output signal of the bus error converter. Power switch MOSFET Q1 also operates in PWM mode, controlled by a first drive signal. Its switching logic is NOT of the second drive signal, achieving the function of an ideal diode. This mode uses an ideal diode instead of a traditional single diode, resulting in lower conduction losses and thus achieving high-efficiency power transfer.

[0050] Furthermore, Figure 3(b) shows the efficient S3R mode fault monitoring and response strategy. When the drive voltage of the power switch MOSFET Q2 is low (U GS2 th2 When ), the drain-source voltage U of the power switch MOSFET Q2 SA If the value remains low, it is determined that a short-circuit fault has occurred in power switch MOSFET Q2. The appropriate response is to set the enable and fault monitoring module 101 output low, effectively disconnecting power switch MOSFET Q1 and preventing power switch MOSFET Q2 from short-circuiting the bus, thus achieving fault isolation. Threshold voltage U th2 It can be determined based on the turn-on threshold of the power switch MOSFET Q2.

[0051] Furthermore, due to the parasitic inductance L of the line​x The presence of this voltage means that at the instant the power switch MOSFET Q1 of S2R is turned off, the voltage U SA This will generate voltage spikes, causing overvoltage stress and damage to the power switch MOSFET Q1. Figure 4(a) shows the voltage-limiting S2R mode, where the voltage U is detected by the second voltage sensor. SA If the voltage exceeds the threshold, the enable and voltage limiting control module 101 will make the power switch MOSFET Q2 work in the linear region, which is equivalent to a variable resistor, reducing the input voltage (the solar cell output is an IV curve, and its open circuit voltage decreases as the output load increases), thus avoiding overvoltage stress damage to the power switch MOSFETs Q1 and Q2.

[0052] Furthermore, Figure 4(b) shows the fault monitoring and response strategy for the voltage-limited S2R mode. Its judgment logic is similar to that of the fault monitoring and response strategy for the efficient S3R mode, the difference being U th3 The threshold voltage needs to be increased according to the voltage range of the linear region, as follows:

[0053] In the voltage-limited S2R mode, the second drive signal is low, the second enable signal is set to "enable", the first drive signal is PWM, and the first enable signal is set to "disable".

[0054] During monitoring, when the gate-source voltage U of the power switch MOSFET Q2... GS2 Less than the threshold voltage U th3 Furthermore, the voltage U at the power transistor connection point SA Less than the threshold voltage U th1 When this occurs, it is determined that a short circuit fault has occurred in the power switch MOSFET Q2;

[0055] The solution is to disconnect the power switch MOSFET Q1 controlled by the enable and fault monitoring module 101.

[0056] Furthermore, Figure 5 A forced power supply mode is given. In this mode, when the control circuit or protection circuit fails and the control signal cannot control the switching transistor, the power switch MOSFET Q1 is turned on to force power supply to the solar cell of that circuit, thus avoiding solar energy loss due to control circuit failure.

[0057] The present invention provides a multi-mode sequential switching shunt circuit, which provides a power supply circuit that can adapt to voltage fluctuations and is suitable for more application scenarios.

[0058] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A multi-mode sequential switching shunt circuit, characterized in that: Includes power switching MOSFET Q1, power switching MOSFET Q2, first drive module, second drive module, enable and fault monitoring module, enable and voltage limiting control module, solar cell, and line parasitic inductance L. x And bus capacitor C, the line parasitic inductance L x One end of the circuit is connected to the positive electrode of the solar cell, and the parasitic inductance L of the circuit is... x The other end is connected to the drain of the power switch MOSFET Q1, and the source of the power switch MOSFET Q1 is connected to the bus voltage U. BUS The positive terminal of the bus capacitor C is connected to the source of the power switch MOSFET Q1, and the other end of the bus capacitor C is connected to the bus voltage U. BUS The negative terminal of the power switch MOSFET Q1 is connected to the output terminal of the first driving module. The first input terminal of the first driving module is connected to the first driving signal. The second input terminal of the first driving module is connected to the output terminal of the enable and fault monitoring module. The first input terminal of the enable and fault monitoring module is connected to the first enable signal. The second and third input terminals of the enable and fault monitoring module are respectively connected to the first input terminal of the enable and voltage limiting control module and the output terminal of the second driving module. The first input terminal of the enable and voltage limiting control module is connected to the drain of the power switch MOSFET Q1. The second input terminal of the enable and voltage limiting control module is connected to the second enable signal. The output terminal of the voltage control module is connected to the first input terminal of the second drive module. The second input terminal of the second drive module is connected to the second drive signal. The output terminal of the second drive module is connected to the gate of the power switch MOSFET Q2. The drain of the power switch MOSFET Q2 is connected to the drain of the power switch MOSFET Q1. The source of the power switch MOSFET Q2 is grounded. The first drive module is controlled by the enable and fault monitoring module and the first drive signal. The enable and fault monitoring module is controlled by the first enable signal and the fault monitoring signal. The enable and voltage limiting control module is controlled by the second enable signal and the voltage limiting signal. The fault monitoring signal is determined by the voltage at the connection point of the power transistor. U SA and the gate-source voltage of power switching MOSFET Q2 U GS2 The logic for generating the judgment is composed of the voltage at the connection point of the power transistor. U SA It is the drain voltage of the power switching MOSFET Q2, and the voltage limiting signal is the voltage at the connection point of the power transistor. U SA Its threshold voltage is determined and generated.

2. The multi-mode sequential switching shunt circuit according to claim 1, characterized in that: The first and second drive signals can operate in PWM mode, and the pulse width is controlled by the output signal of the bus error controller, so that the bus voltage or current can achieve closed-loop control.

3. A fault handling method for a multi-mode sequential switching shunt circuit, characterized in that: A multi-mode sequential switching shunt circuit as described in any one of claims 1 to 2 is provided, wherein the multi-mode sequential switching shunt circuit has four operating modes, namely S2R mode, high-efficiency S3R mode, voltage-limited S2R mode and forced power supply mode, and any one of the S2R mode, high-efficiency S3R mode, voltage-limited S2R mode and forced power supply mode is selected according to the input quantity.

4. The fault handling method for the multi-mode sequential switching shunt circuit according to claim 3, characterized in that: The input quantities include any one or any combination of orbital parameters, on-orbit data, and solar cell configuration.

5. The fault handling method for the multi-mode sequential switching shunt circuit according to claim 3, characterized in that: In the S2R mode, the second drive signal is low, the second enable signal is set to "disable", and the power switch MOSFET Q2 is in the off state and is not controlled by the output signal of the bus error detector. The first drive signal is PWM, the first enable signal is set to "disable", and the power switch MOSFET Q1 is in PWM state and is controlled by the first drive signal. The first drive signal is controlled by the output signal of the bus error detector. During monitoring, the voltage detection circuit determines the voltage at the connection point of the power transistor by judging the first voltage detection. U SA To determine if the power switch MOSFET Q2 has a short circuit fault, if the voltage at the power transistor connection point is... U SA Less than the threshold voltage U th1 If so, it is considered that the power switch MOSFET Q2 has a short circuit fault; The solution is to disconnect the power switch MOSFET Q1 controlled by the enable and fault monitoring module to prevent the power switch MOSFET Q2 from pulling down the bus voltage.

6. The fault handling method for the multimodal sequential switching shunt circuit according to claim 3, characterized in that: In the high-efficiency S3R mode, the second drive signal is PWM, the second enable signal is set to "disable", the power switch MOSFET Q2 is in PWM state and is controlled by the second drive signal. The second drive signal is controlled by the output signal of the bus error method. The first drive signal is PWM, the first enable signal is set to "disable", the power switch MOSFET Q1 is also in PWM state and is controlled by the first drive signal. The switching logic of the first drive signal and the switching logic of the second drive signal are mutually "NOT" logic, realizing the function of an ideal diode. During monitoring, when the drive voltage of the power switch MOSFET Q2 is low, i.e., the gate-source voltage U of the power switch MOSFET Q2 is low... GS2 Less than the threshold voltage U th2 At this time, the drain-source voltage of the power switch MOSFET Q2 is still low, that is, the voltage at the connection point of the power transistor is low. U SA Less than the threshold voltage U th1 If so, it is determined that a short circuit fault has occurred in the power switch MOSFET Q2; The solution is to disconnect the power switch MOSFET Q1 controlled by the enable and fault monitoring module to prevent the power switch MOSFET Q2 from short-circuiting the bus and thus achieve fault isolation.

7. The fault handling method for the multimodal sequential switching shunt circuit according to claim 3, characterized in that: In the voltage-limited S2R mode, the second drive signal is low, the second enable signal is set to "enable", the first drive signal is PWM, and the first enable signal is set to "disable". During monitoring, when the gate-source voltage U of the power switch MOSFET Q2... GS2 Less than the threshold voltage U th3 Furthermore, the voltage at the power transistor connection point U SA Less than the threshold voltage U th1 When this occurs, it is determined that a short circuit fault has occurred in the power switch MOSFET Q2; The solution is to disconnect the power switch MOSFET Q1 controlled by the enable and fault monitoring module.

8. The fault handling method for the multi-mode sequential switching shunt circuit according to claim 3, characterized in that: In the voltage-limited S2R mode, the voltage at the power transistor connection point is detected by a second voltage sensor. U SA If there is a voltage exceeding the threshold voltage U th1 In such cases, the enable and voltage limiting control module enables the power switch MOSFET Q2 to operate in the linear region, which is equivalent to a variable resistor, reducing the input voltage and preventing overvoltage stress damage to the power switch MOSFETs Q1 and Q2.

9. The fault handling method for the multi-mode sequential switching shunt circuit according to claim 3, characterized in that: In the forced power supply mode, the second drive signal is low, the second enable signal is set to "disable", the first drive signal is arbitrary, and the first enable signal is set to "enable". When the control circuit or protection circuit fails, causing the control signal to be unable to control the switching transistor, the control power switch MOS transistor Q1 is turned on to control the solar cell to supply power in a forced manner, so as to avoid solar energy loss in this circuit due to the failure of the control circuit.

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