Filtering algorithm implementation method based on RISC-V architecture, coprocessor and computer equipment

Abstract

The invention relates to the technical field of filtering algorithms, and discloses a filtering algorithm implementation method based on an RISC-V architecture, a coprocessor, computer equipment and a computer readable storage medium in order to solve the problem that an implementation mode of an existing filtering algorithm is low in execution efficiency. The method comprises the following steps: obtaining a filtering algorithm, wherein the filtering algorithm comprises a 128-order FIR module, an EQ module and a mute module; defining a first instruction, a second instruction and a third instruction for a filtering algorithm; a first instruction, a second instruction and a third instruction are called, corresponding operation in a filtering algorithm is executed, the first instruction is used for achieving multiplication and addition operation in the FIR module, the EQ module and the mute module, the second instruction is used for achieving multiplication and subtraction operation in the EQ module, and the third instruction is used for achieving multiplication and subtraction operation in the EQ module. The third instruction is used for carrying out zero clearing on a register used for caching the multiply-add operation and multiply-subtract operation results before each calculation. By adopting the method, the execution capability of the processor on the filtering algorithm can be improved on the basis of increasing the richness of the instruction set of the processor.

Description

Technical Field

[0001] The present application relates to the field of filtering algorithm technology, and more specifically, to a filtering algorithm implementation method based on RISC-V architecture, a coprocessor, a computer device, and a computer-readable storage medium. Background Art

[0002] The filtering algorithms mainly include FIR (Finite Impulse Response) filter, EQ (Equalizer) and mute algorithm. Among them, FIR filter is a commonly used filter in digital signal processing.

[0003] An equalizer (EQ) is a device used to adjust the gain of each frequency band of an audio signal. It is widely used in audio processing, sound engineering, music production and other fields. The 10-level equalizer contains 10 different frequency bands, and the gain of each frequency band can be adjusted individually to achieve precise adjustment of the frequency response of the audio signal. The equalizer changes the spectral content of the audio signal by adjusting the gain of different frequency bands. Each frequency band usually corresponds to a bandpass filter or a peak filter. The equalizer can accurately control the spectral content of the audio signal to adapt it to different audio systems and auditory environments. By adjusting the gain of each frequency band, the audio signal can be beautified to make it more in line with the user's auditory preferences. It can also be used to suppress feedback noise in the audio signal and improve the clarity and quality of the sound.

[0004] At present, the implementation methods of the above filtering algorithms are mainly focused on hardware logic implementation or software programming implementation. Hardware logic implementation can achieve relatively high operating efficiency, but the demand for hardware resource overhead is relatively large. Although software programming implementation has relatively higher flexibility, it is relatively low in execution efficiency. Summary of the invention

[0005] In order to solve the problems that the current implementation method of the filtering algorithm has a large demand for hardware resource overhead and low execution efficiency, the present invention provides a filtering algorithm implementation method, a coprocessor, a computer device and a computer-readable storage medium based on the RISC-V architecture, which will increase the richness of the processor instruction set and improve the processor's execution capability of the filtering algorithm.

[0006] To achieve the above object, according to a first aspect of the present invention, a method for implementing a filtering algorithm based on a RISC-V architecture is provided, the method comprising:

[0007] Get the filtering algorithm, which includes 128-order FIR module, EQ module and mute module;

[0008] Define a first instruction, a second instruction, and a third instruction for a filtering algorithm;

[0009] Call the first instruction, the second instruction, and the third instruction to execute corresponding operations in the filtering algorithm, wherein the first instruction is used to implement multiplication and addition operations in the FIR module, the EQ module, and the mute module, the second instruction is used to implement multiplication and subtraction operations in the EQ module, and the third instruction is used to clear the registers used to cache the results of multiplication and addition operations and multiplication and subtraction operations before each calculation.

[0010] Furthermore, the encoding format of the first instruction is that the range from the 0th to the 6th bit of the instruction is the opcode field, whose value is 0110011, which is used to indicate the use of the custom-0 instruction group; the range from the 7th to the 11th bit of the instruction is the rd field, whose value is the destination register rd corresponding to the destination operand, and the corresponding calculation result is stored in the destination operand; the range from the 12th to the 14th bit of the instruction is the funct3 field, whose value is 000, which is used as the grouping code of the three extended instructions; the range from the 15th to the 19th bit of the instruction is the rs1 word The segment, whose value is the corresponding index of the source register rs1, is used to store the multiplier A of the current execution stage; the interval from the 20th to the 24th bit of the instruction is the rs2 field, whose value is the corresponding index of the source register rs2, which is used to store the multiplier B of the current execution stage; the interval from the 25th to the 31st bit of the instruction is the funct7 field, and the encoding format of the 25th to the 29th bit is 01111, where the 1 of the 30th bit is used to indicate that the value is encoded as the first instruction; the binary number corresponds to the decimal number 01111, which is used to calculate the execution stage of the multiplication.

[0011] Furthermore, the first instruction is a filterwkA instruction, and the method of calling the first instruction includes filterwkA(EQ_DataIn(n), t1_EQ_b0), wherein the instruction is defined to have a write-back result, and the instruction execution result is added to the internal special register to update the value of the internal calculator, and the instruction needs to read the value of the source register rs1 and the value of the source register rs2.

[0012] Furthermore, the encoding format of the second instruction includes the 0th to 6th bit interval of the instruction as the opcode field, whose value is 0110011, which is used to mark the use of the custom-0 instruction group; the 7th to 11th bit interval of the instruction is the rd field, whose value is the destination operand corresponding to the destination register rd, and the corresponding calculation result is stored in the destination operand; the 12th to 14th bit interval of the instruction is the funct3 field, whose value is 000, which is used as the group code for the three extended instructions; the 15th to 19th bit interval of the instruction is the rs1 field, whose value is the corresponding index of the source register rs1, which is used to store the multiplier A of the current execution stage; the 20th to 24th bit interval of the instruction is the rs2 field, whose value is the corresponding index of the source register rs2, which is used to store the multiplier B of the current execution stage.

[0013] Furthermore, the second instruction is a filterwkS instruction, and the method of calling the second instruction includes filterwkS(EQ_DataIn(n), t1_EQ_b0), wherein the instruction is defined to have a write-back result, and the instruction execution result is subtracted from the internal special register to update the value of the internal calculator, and the instruction needs to read the value of the source register rs1 and the value of the source register rs2.

[0014] Furthermore, the encoding format of the third instruction includes the range from the 0th to the 6th bit of the instruction as the opcode field, whose value is 0001011, used to indicate the use of the custom-0 instruction group; the range from the 7th to the 11th bit of the instruction as the rd field, whose value is the corresponding index of the destination register rd, used to write back the calculation result generated when the instruction is executed; the range from the 12th to the 14th bit of the instruction as the funct3 field, whose value is 000, used as the group code for three extended instructions; the range from the 15th to the 19th bit of the instruction as the rs1 field, whose value is 00000; the range from the 20th to the 24th bit of the instruction as the rs2 field, whose value is 00000; the range from the 25th to the 31st bit of the instruction as the funct7 field, the encoding format is 0000111, used to indicate that the value is encoded as the third instruction.

[0015] Furthermore, the third instruction is a filterwr instruction, and the method of calling the third instruction includes filterwr(0,0), wherein the instruction is defined to clear the internal special register, and the instruction does not need to read the value of the source register rs1, the value of the source register rs2, and the value of the destination register rd.

[0016] According to a second aspect of the present invention, there is also provided a coprocessor comprising a controller, an arithmetic logic unit, an internal memory and a computer program stored in the internal memory, wherein the controller calls the arithmetic logic unit to execute the computer program to implement the steps of any of the above methods.

[0017] According to the third aspect of the present invention, a computer device is also provided, which includes a coprocessor, the coprocessor includes a controller, an arithmetic logic unit, an internal memory and a computer program stored in the internal memory, and the controller calls the arithmetic logic unit to execute the computer program to implement the steps of any of the above methods.

[0018] According to a fourth aspect of the present invention, there is also provided a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a coprocessor, the steps of any of the above methods are implemented.

[0019] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0020] The filtering algorithm implementation method based on the RISC-V architecture provided by the present invention adds the first instruction, the second instruction, and the third instruction as an extended instruction set to the hardware logic structure of the processor, so that the processor based on the RISC-V architecture can call the extended instruction set at the instruction set level, thereby improving the processor's execution ability for the filtering algorithm on the basis of increasing the richness of the processor instruction set. In addition, the RISC-V extended instruction set for the filtering algorithm provided by the present application has high flexibility, and developers can decide whether to add the extended instruction set to the hardware logic structure of the processor according to whether there is a demand for the filtering algorithm, while not changing the hardware logic structure of other parts of the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A flowchart of a filtering algorithm implementation method based on the RISC-V architecture provided in an embodiment of the present application;

[0023] Figure 2 A schematic diagram of the pipeline structure of the RISC-V architecture provided in the embodiment of the present application;

[0024] Figure 3 A schematic diagram of the RV32R-type and filtering algorithm extended instruction format provided in an embodiment of the present application;

[0025] Figure 4 A calculation flow chart of the FIR filter provided in the embodiment of the present application;

[0026] Figure 5A A schematic diagram of the first round of FIR input data and sliding window provided in an embodiment of the present application;

[0027] Figure 5B A schematic diagram of the second round of FIR input data and sliding window provided in an embodiment of the present application;

[0028] Fig. 6A A schematic diagram of the 128th round of FIR input data and sliding window provided in an embodiment of the present application;

[0029] Figure 6B A schematic diagram of the 129th round of FIR input data and sliding window provided in an embodiment of the present application;

[0030] Figure 7A schematic diagram of the internal structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0032] The terms "first", "second", "third", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0033] like Figure 1 As shown, a filtering algorithm implementation method based on the RISC-V architecture is provided. RISC-V is an open source instruction set architecture (ISA) based on the reduced instruction set (RISC) principle.

[0034] The method is implemented based on the VexRiscv processor, which is an open source processor based on the RISC-V architecture and uses SpinalHDL for hardware description. The RV32 processor is also the general processor basis for the extended instruction set of the filtering algorithm processing implemented in this application. Figure 2 As shown, the VexRiscv processor has a five-stage pipeline structure. The life cycle of an instruction in the pipeline includes five stages: instruction fetch, decoding, execution, memory access, and write back.

[0035] The method can be executed by a terminal or by a server communicating with the terminal through a network. The terminal can be, but is not limited to, various personal computers, laptops, etc. The server can be an independent server or a server cluster composed of multiple servers. The method is described by taking the application of the method to a terminal as an example, and includes the following steps:

[0036] Step 101, obtaining a filtering algorithm, the filtering algorithm includes a 128-order FIR module, an EQ module and a mute module.

[0037] The filtering algorithm includes a 128-level FIR module configured as a low-pass filter with a cutoff frequency of 20k, a 10-level EQ module configured as a low-frequency filter with a cutoff frequency of 1k-10k, and a mute module.

[0038] Step 102, defining a first instruction, a second instruction, and a third instruction for a filtering algorithm.

[0039] Among them, the main operations in the 128-order FIR module, EQ module and mute module are multiplication and addition and multiplication and subtraction. Therefore, three filter processing extension instructions are proposed for the operation requirements of the three modules: the first instruction, the second instruction and the third instruction. The first instruction is the filterwkA instruction, the second instruction is the filterwkS instruction, and the third instruction is the filterwr instruction. FilterwkA and filterwkS operate on internal registers, and can perform addition and subtraction on all symbolic 32-bit algorithms in the filter algorithm, and store the calculation results in the internal registers. The filterwr instruction is an access to the internal registers, such as the initialization process at the beginning and the result of accessing the register at the end.

[0040] Step 103, calling the first instruction, the second instruction, and the third instruction to execute corresponding operations in the filtering algorithm, wherein the first instruction is used to implement the multiplication and addition operations used by the FIR module, the EQ module, and the mute module, the second instruction is used to implement the multiplication and subtraction operations in the EQ module, and the third instruction is used to clear the registers used to cache the results of the multiplication and addition operations and the multiplication and subtraction operations before each calculation.

[0041] In the above-mentioned filtering algorithm implementation method based on RISC-V architecture, the first instruction, the second instruction, and the third instruction are added as extended instruction sets to the hardware logic structure of the VexRiscv processor by utilizing the characteristics of fast operation speed of the hardware logic structure and high flexibility of software programming, so that the VexRiscv processor can call the extended instruction set at the instruction set level, thereby achieving the purpose of improving the processor's execution ability for the filtering algorithm on the basis of increasing the richness of the processor instruction set. In addition, the RISC-V extended instruction set for the filtering algorithm provided by the present application has high flexibility, and developers can decide whether to add the extended instruction set to the hardware logic structure of the processor based on whether there is a demand for the filtering algorithm, while not changing the hardware logic structure of other parts of the processor.

[0042] Figure 3 A schematic diagram of the RV32R-type and filtering algorithm extended instruction format provided in an embodiment of the present application, wherein the encoding formats of the first instruction, the second instruction, and the third instruction all satisfy the following Figure 3 The common encoding format of the RISC-V instruction set shown.

[0043] In one embodiment, the encoding format of the first instruction is:

[0044] The 0th to 6th bit of the instruction is the opcode field, whose value is 0110011, which is used to indicate the use of the custom-0 instruction group;

[0045] The interval from the 7th to the 11th bit of the instruction is the rd field, whose value is the destination register rd corresponding to the destination operand, and the corresponding calculation result is stored in the destination operand;

[0046] The interval from the 12th bit to the 14th bit of the instruction is the funct3 field, whose value is 000, and is used as the grouping code of the three extended instructions (i.e., the first instruction, the second instruction, and the third instruction);

[0047] The 15th to 19th bit interval of the instruction is the rs1 field, whose value is the corresponding index of the source register rs1, which is used to store the multiplier A of the current execution stage;

[0048] The 20th to 24th bits of the instruction are the rs2 field, whose value is the corresponding index of the source register rs2, which is used to store the multiplier B of the current execution stage;

[0049] The range from the 25th to the 31st bit of the instruction is the funct7 field, and the encoding format of the 25th to the 29th bit is 01111, where the 1 of the 30th bit is used to indicate that the value is encoded as the first instruction; the binary number corresponds to the decimal number 01111, which is used to calculate the execution stage of multiplication.

[0050] In one embodiment, the first instruction is called as filterwkA(EQ_DataIn(n), t1_EQ_b0), wherein the instruction is defined to have a write-back result, and the instruction execution result is added to the internal special register to update the value of the internal calculator. The instruction needs to read the value of the source register rs1 and the value of the source register rs2.

[0051] In one embodiment, the encoding format of the second instruction is:

[0052] The 0th to 6th bit of the instruction is the opcode field, whose value is 0110011, which is used to indicate the use of the custom-0 instruction group;

[0053] The interval from the 7th to the 11th bit of the instruction is the rd field, whose value is the destination register rd corresponding to the destination operand, and the corresponding calculation result is stored in the destination operand;

[0054] The interval from the 12th bit to the 14th bit of the instruction is the funct3 field, whose value is 000, and is used as the grouping code of the three extended instructions (i.e., the first instruction, the second instruction, and the third instruction);

[0055] The 15th to 19th bit interval of the instruction is the rs1 field, whose value is the corresponding index of the source register rs1, which is used to store the multiplier A of the current execution stage;

[0056] The range from the 20th to the 24th bit of the instruction is the rs2 field, whose value is the corresponding index of the source register rs2, and is used to store the multiplier B of the current execution stage.

[0057] In one embodiment, the second instruction is called as filterwkS(EQ_DataIn(n), t1_EQ_b0), wherein the instruction is defined to have a write-back result, and the instruction execution result is subtracted from the internal special register to update the value of the internal calculator. The instruction needs to read the value of the source register rs1 and the value of the source register rs2.

[0058] In one embodiment, the encoding format of the third instruction is:

[0059] The 0th to 6th bit of the instruction is the opcode field, whose value is 0001011, which is used to indicate the use of the custom-0 instruction group;

[0060] The 7th to 11th bit of the instruction is the rd field, whose value is the corresponding index of the destination register rd, which is used to write back the calculation result generated when the instruction is executed;

[0061] The interval from the 12th bit to the 14th bit of the instruction is the funct3 field, whose value is 000, and is used as the grouping code of the three extended instructions (i.e., the first instruction, the second instruction, and the third instruction);

[0062] The range from bit 15 to bit 19 of the instruction is the rs1 field, and its value is 00000;

[0063] The range from bit 20 to bit 24 of the instruction is the rs2 field, and its value is 00000;

[0064] The interval from the 25th to the 31st bit of the instruction is the funct7 field, and the encoding format is 0000111, which is used to mark that the value is encoded as the third instruction.

[0065] In one embodiment, the third instruction is called as filterwr(0,0), wherein the instruction is defined to clear the internal special register, and the instruction does not need to read the value of the source register rs1, the value of the source register rs2, and the value of the destination register rd.

[0066] In one embodiment, the above step 101, obtaining the filtering algorithm includes loading and initializing the data in the filtering algorithm, and the specific steps are as follows:

[0067] S1, the filtering operation of digital signals is actually a weighted operation. After the input signal is multiplied and added with coefficients of different weights, the target signal can be retained and the interference signal can be attenuated. FIR filters have the characteristics of linear phase. Within the effective frequency input range, the absolute phase of the signal passing through the system may change, but the relative phase between each signal remains unchanged. The coefficients of this type of filter have a symmetrical relationship.

[0068] The principle of N-1 order FIR filter is as follows Figure 4 As shown in formula (1), it can be seen that a filter with N taps needs to calculate N multiplications and N-1 additions to complete a filtering operation.

[0069]

[0070] The filter needs to continuously perform weighted processing on the input signal FIR_in(n) and obtain the filtered signal FIR_out(n) after accumulation.

[0071] The number of taps and coefficients of the FIR filter used in this embodiment are both even numbers, and the filter coefficients are symmetrical. When the number of taps is 128, formula (2) is satisfied:

[0072] h[0]=h

[127] , h[1]=h

[126] …h

[63] =h

[64] (2)

[0073] Furthermore, formula (1) is transformed into formula (3):

[0074]

[0075] From formula (3), it can be seen that when the number of taps is 128, only 64 filter coefficients need to be input, thus saving calculation time. Formula (4) gives the calculation process of the first few levels:

[0076] y[0]=h[0]·x[0]

[0077] y[1]=h[0]·x[1]+h[1]·x[0]

[0078] y[2]=h[0]·x[2]+h[1]·x[1]+h[2]·x[0]

[0079] …

[0080] y

[127] =h[0]·x

[127] +h[1]·x

[126] +.....+h

[126] ·x[1]+h

[127] ·x[0]

[0081] y

[128] =h[0]·x

[128] +h[1]·x

[127] +.....+h

[126] ·x[2]+h

[127] ·x[1](4)

[0082] FIR filters often use a circular buffer to process input data because the input needs to be circularly shifted right to calculate the output. As shown in the last two equations of formula (4), the input required for two calculations is shifted back one position. The benefit of a circular buffer is that it is easy to manage a sliding window for calculation without having to move the data in the entire array every time new data is input.

[0083] A filtering algorithm implementation method based on the RISC-V architecture provided in an embodiment of the present application adopts a 128-level filter, so a buffer size of 256 is set. Figure 5A and Figure 5B Schematic diagram of FIR input data and sliding window. The first input data is to the 1st and 128th bits of the buffer, such as Figure 5A As shown, the sliding window starts from the second bit and has a size of 128, as shown in the red box in the figure, and is represented by the array firdata. Since the filter coefficients are symmetrical, the two symmetrical data firdata[0] and firdata

[127] in the window can be added and multiplied by the common filter coefficient h[0], a total of 64 multiplications as shown in formula (5). fir_result = (pFirdata[0] + pFirdata

[127] )·h[0]

[0084] +(pFirdata[1]+pFirdata

[126] )·h[1]

[0085] +…+(pFirdata

[63] +pFirdata

[64] )·h

[63] (5)

[0086] After each data entry, the position of the next set of data will move down one position, and the sliding window will also move down one position to complete the update of the input delay in the FIR calculation, such as Figure 5B As shown, the next time data is input into the buffer at the 2nd and 129th bits, the sliding window moves to the third bit.

[0087] S2, stores the new data in two locations in the buffer to simplify the handling of sliding windows. The reason for this is that when the sliding window crosses the boundary of the buffer, the continuity of data access can be guaranteed. Fig. 6A and Figure 6B This is a schematic diagram of the fir buffer processing flow. For example Fig. 6AWhen the sliding window slides to the lower boundary, the result of the calculation is shown as y

[127] in formula (4). The input data returns to the 1st and 128th bits in the next calculation, and the sliding window also starts from the second bit. At this time, the calculation in the sliding window is the same as the output form of y

[128] in formula (2). By storing data in this way, it can be ensured that the data in the sliding window is continuous. Regardless of whether the window crosses the buffer boundary, the data input to the buffer can be correctly calculated.

[0088] The algorithm effectively simplifies and optimizes the calculation process of the FIR filter by creating a buffer of size 256 and storing the input data each time in two fixed interval positions, moving the input data position and sliding the calculation window each time.

[0089] Specifically, this approach ensures data continuity and efficient access by using a circular buffer, thereby avoiding the complexity of handling situations that cross buffer boundaries.

[0090] As an integral part of the software and hardware collaboration process, pipeline design has a key impact on the operating efficiency of instructions. The three extended instructions included in the embodiment of the present application select the instruction hardware logic based on the VexRiscv main processor and adapt to the four-stage pipeline stage. Combined with the actual operation process in the algorithm principle, the memory access stage will be responsible for the value update operation of all internal memory unit registers.

[0091] S3, based on the above-mentioned design of the instruction pipeline logic and the analysis of the four stages of the filtering implementation process, the software end compiles the algorithm instructions in this embodiment into machine-recognizable instruction codes based on C language coding and using inline assembly technology.

[0092] The filtering algorithm FIR is implemented through 3 extended instruction operations. The main process is as follows:

[0093] For FIR filter, firstly, a space is allocated in the memory address to place the fir coefficient Fircoeff

[64] and the fir input buffer FirData

[256] . Then, the input data is stored in the memory at the address where Fircoeff

[64] and FirData

[256] are located through the csr instruction. A pointer pFirdata is established to point to FirData

[256] . That is, at the beginning, pFirdata points to the first address of FirData. Then, the position pointed to by the pointer is moved to complete the operation. Fig. 6A and Figure 6B The transformation of the input data position and the movement of the sliding calculation window.

[0094] S4, pFirdata is incremented by 1 to point to the address of the second position of FirData, which means that the sliding window starts from the second position of the buffer. The LOAD_2_DATA_TO_REGISTERS instruction indicates that two numbers are taken from the memory and put into the register, and the ADD instruction indicates that the numbers in the two registers are added and output to a specified register.

[0095] S5, by applying the LOAD_2_DATA_TO_REGISTERS instruction, the data of FirData in the memory is input into the general register to facilitate the subsequent operation. Next, the ADD instruction is used to add the two symmetrical coefficients in the sliding window, which is convenient for subsequent multiplication by the same fir coefficient. Finally, the filterwkA instruction in the extended instruction set is called to complete the multiplication of the input and the fir coefficient and then add them up.

[0096] Since it takes a little time to load data from memory to registers, the value of the register cannot be used directly and needs to wait for a while. However, through an instruction reordering, we can ensure that the data required for calculation has been loaded into the register and can be used. We first load the fir input from memory, and then load the fir coefficient. In this way, when the fir input is needed for addition, the data in the register can be used directly. Similarly, after the delay of the ADD operation, when calculating the product of the fir input and the fir coefficient, the value of the fir coefficient in the register can also be used directly, thus avoiding the waste of cycles.

[0097] After calculating one round of fir, when the next round of input data is performed, ptr has been incremented by one, and pFirdata also points to the next position of FirData, completing the movement of the input data position. When the input data position moves to the buffer boundary, that is, the 127th and 255th positions, the input data needs to return to the 0th position at the next moment. Here we complete it by judging the ptr value. When pFirdata points to the 128th position of FirData, ptr=128. At this time, ptr is set to 0, and pFirdata points to the 0th position of FirData again.

[0098] After completing the data loading and initialization operations in the filtering algorithm through the above functions, the filtering operation can be performed by calling three instructions for calculation. A single call to the filterwkA instruction can only obtain data with a word length of 32 bits. The acquisition of long data streams can be achieved by loop calls.

[0099] The present application also provides a coprocessor, including a controller, an arithmetic logic unit, an internal memory, and a computer program stored in the internal memory, wherein the controller is configured to receive instructions sent by a main processor, parse the instructions, and call the arithmetic logic unit to execute the computer program according to the parsing results to implement a filtering algorithm implementation method based on the RISC-V architecture, and read and write data to the internal memory; the arithmetic logic unit is connected to the controller and the internal memory, and is configured to execute a function (including a filtering algorithm implementation method based on the RISC-V architecture) on the data in the internal memory, and send the output result of the function to the internal memory to update the data in the internal memory; the internal memory is connected to the arithmetic logic unit, including 16 31-bit wide registers and 2 32-bit wide registers, and is configured to store the data required during the execution of the filtering algorithm and the data generated by the calculation.

[0100] The present application also provides a computer device, whose internal structure diagram can be as follows: Figure 7 As shown. The computer device includes a main processor, a coprocessor, a memory, an input / output interface, a communication interface, a display unit and an input device, and the coprocessor includes a controller, an arithmetic logic unit, an internal memory and a computer program stored in the internal memory. Among them, the main processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. Among them, the main processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium. The non-volatile storage medium stores an operating system and a computer program. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the coprocessor, a filtering algorithm implementation method based on the RISC-V architecture is implemented.

[0101] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0102] like Figure 7As shown, the present application also provides a computer device, which includes a coprocessor, the coprocessor includes a controller, an arithmetic logic unit, an internal memory and a computer program stored in the internal memory, the controller calls the arithmetic logic unit to execute the computer program to implement the steps in the above-mentioned method embodiments.

[0103] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a micro drive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), or any type of medium or device suitable for storing instructions and / or data.

[0104] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0105] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0106] The above is only an exemplary embodiment of the present disclosure, and the scope of the present disclosure cannot be limited thereto. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the specification and practicing the disclosure here, those skilled in the art will easily think of the implementation scheme of the present disclosure. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not recorded in the present disclosure. The description and examples are only regarded as exemplary, and the scope and spirit of the present disclosure are defined by the claims.

[0107] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A filtering algorithm implementation method based on RISC-V architecture, characterized in that: include: Acquire a filtering algorithm, wherein the filtering algorithm includes a 128-order FIR module, an EQ module, and a mute module; defining a first instruction, a second instruction, and a third instruction for the filtering algorithm; The first instruction, the second instruction, and the third instruction are called to execute corresponding operations in the filtering algorithm, wherein the first instruction is used to implement multiplication and addition operations in the FIR module, the EQ module, and the mute module, the second instruction is used to implement multiplication and subtraction operations in the EQ module, and the third instruction is used to clear registers used to cache multiplication and addition operations and multiplication and subtraction operations before each calculation.

2. The method according to claim 1, characterized in that The encoding format of the first instruction is: The 0th to 6th bit of the instruction is the opcode field, whose value is 0110011, which is used to indicate the use of the custom-0 instruction group; The interval from the 7th to the 11th bit of the instruction is the rd field, whose value is the destination register rd corresponding to the destination operand, and the corresponding calculation result is stored in the destination operand; The interval from bit 12 to bit 14 of the instruction is the funct3 field, whose value is 000, and is used as the grouping code for the three extended instructions; The 15th to 19th bit interval of the instruction is the rs1 field, whose value is the corresponding index of the source register rs1, which is used to store the multiplier A of the current execution stage; The 20th to 24th bits of the instruction are the rs2 field, whose value is the corresponding index of the source register rs2, which is used to store the multiplier B of the current execution stage; The range from the 25th to the 31st bit of the instruction is the funct7 field, and the encoding format of the 25th to the 29th bit is 01111, where the 1 of the 30th bit is used to indicate that the value is encoded as the first instruction; the binary number corresponds to the decimal number 01111, which is used to calculate the execution stage of the multiplication.

3. The method according to claim 2, characterized in that The first instruction is a filterwkA instruction, and the method of calling the first instruction includes: filterwkA(EQ_DataIn(n),t1_EQ_b0), where the instruction is defined to have a write-back result. The instruction execution result is added to the internal special register and then the value of the internal calculator is updated. The instruction needs to read the value of the source register rs1 and the value of the source register rs2.

4. The method according to claim 1, characterized in that The encoding format of the second instruction includes: The 0th to 6th bit of the instruction is the opcode field, whose value is 0110011, which is used to indicate the use of the custom-0 instruction group; The interval from the 7th to the 11th bit of the instruction is the rd field, whose value is the destination register rd corresponding to the destination operand, and the corresponding calculation result is stored in the destination operand; The interval from bit 12 to bit 14 of the instruction is the funct3 field, whose value is 000, and is used as the grouping code for the three extended instructions; The 15th to 19th bit interval of the instruction is the rs1 field, whose value is the corresponding index of the source register rs1, which is used to store the multiplier A of the current execution stage; The range from the 20th to the 24th bit of the instruction is the rs2 field, whose value is the corresponding index of the source register rs2, and is used to store the multiplier B of the current execution stage.

5. The method according to claim 4, characterized in that The second instruction is a filterwkS instruction, and the method of calling the second instruction includes: filterwkS(EQ_DataIn(n),t1_EQ_b0), where the instruction is defined to have a write-back result. The instruction execution result is subtracted from the internal special register to update the value of the internal calculator. The instruction needs to read the value of the source register rs1 and the value of the source register rs2.

6. The method according to claim 1, characterized in that The encoding format of the third instruction includes: The 0th to 6th bit of the instruction is the opcode field, whose value is 0001011, which is used to indicate the use of the custom-0 instruction group; The 7th to 11th bit of the instruction is the rd field, whose value is the corresponding index of the destination register rd, which is used to write back the calculation result generated when the instruction is executed; The interval from bit 12 to bit 14 of the instruction is the funct3 field, whose value is 000, and is used as the grouping code for the three extended instructions; The range from bit 15 to bit 19 of the instruction is the rs1 field, and its value is 00000; The range from bit 20 to bit 24 of the instruction is the rs2 field, and its value is 00000; The interval from the 25th to the 31st bit of the instruction is the funct7 field, and the encoding format is 0000111, which is used to mark that the value is encoded as the third instruction.

7. The method according to claim 6, characterized in that The third instruction is a filterwr instruction, and the method of calling the third instruction includes: filterwr(0,0), wherein the instruction is defined to clear the internal special register to zero, and the instruction does not need to read the value of the source register rs1, the value of the source register rs2, and the value of the destination register rd.

8. A coprocessor, characterized in that: The invention comprises a controller, an arithmetic logic unit, an internal memory and a computer program stored in the internal memory, wherein the controller calls the arithmetic logic unit to execute the computer program to implement the steps of the method according to any one of claims 1 to 7.

9. A computer device, characterized in that: The coprocessor comprises a controller, an arithmetic logic unit, an internal memory and a computer program stored in the internal memory, wherein the controller calls the arithmetic logic unit to execute the computer program to implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by the coprocessor, the steps of the method according to any one of claims 1 to 7 are implemented.

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