A driving circuit for high voltage PMOS

Abstract

The invention relates to the technical field of electronic circuit design, in particular to a driving circuit for a high-voltage PMOS, comprising a reference potential point GND, and further comprising: a source of a first N-type MOS tube NM1, a source of a sixth N-type MOS tube NM6, a source of a fourth N-type MOS tube NM4, a source of a second N-type MOS tube NM2, a source of a fifth N-type MOS tube NM5, and a source of a third N-type MOS tube NM3 are connected to GND; a negative end of a Zener diode D1, a resistor R1, a source of a first P-type MOS tube PM1, a negative end of a Zener diode D2, a resistor R2, a source of a second P-type MOS tube PM2, a negative end of a Zener diode D3, a resistor R3, and a drain of a third N-type MOS tube NM3 are connected to VIN; a driving control is used for controlling the conduction and disconnection of the first P-type MOS tube PM1 and the second P-type MOS tube PM2; through a reasonably designed circuit structure and control logic, effective control of a gate-source voltage of a high-voltage PMOS power tube is achieved, driving capability is improved, conduction impedance is reduced, and performance of the high-voltage PMOS power tube is optimized.

Description

Technical Field

[0001] The invention relates to the field of electronic circuit design, and in particular to a driving circuit for a high-voltage PMOS. Background Art

[0002] DC-DC converters have high conversion efficiency, high integration and high cost performance, and are widely used in power supply systems. For higher efficiency, power tubes in DC-DC converters usually use NMOS tubes or PMOS tubes. NMOS tubes have smaller on-resistance, and in order to make them conduct, they need a higher gate voltage than the source to drive them. Therefore, it is of great significance to design a driving circuit for PMOS tubes.

[0003] At present, many circuits use NMOS tubes as power tubes instead of PMOS tubes. This is because NMOS tubes have higher carrier mobility than PMOS tubes. Under the same on-resistance and gate-source voltage, NMOS power tubes require a smaller area. However, the use of NMOS tubes requires bootstrap boosting technology to solve the problem of gate voltage drive. Otherwise, the gate-source voltage drive is insufficient, resulting in an increase in the on-resistance of the power tube, thereby increasing the conduction loss.

[0004] When a PMOS tube is used as a power tube, when the source voltage high voltage minus the gate voltage is higher than the threshold voltage, the PMOS tube is turned on, and there is no need to use the bootstrap boost technology. This is an advantage of the PMOS tube. However, the PMOS tube also has some problems: although its source voltage and drain-gate voltage can withstand high voltage, the gate-source voltage tolerance is usually 5V, and there is a risk of breakdown if it exceeds 5V.

[0005] To address these issues, it is necessary to design a driving circuit for the high-voltage PMOS power tube, which can stabilize the gate-source voltage at 5V when the PMOS tube is turned on, ensuring safety and reducing the on-resistance. At the same time, it is also necessary to reduce the delay time from the control signal to the high-voltage PMOS power tube switch to improve the driving capability.

[0006] The driving circuit in the prior art has the following defects: it is unable to effectively control the gate-source voltage of the high-voltage PMOS power tube, which easily leads to device damage; the driving capability is insufficient, resulting in a long switching delay time, affecting the circuit performance; it is unable to effectively reduce the on-resistance while ensuring safety; there is a lack of special optimization design for the high-voltage PMOS power tube, making it difficult to give full play to its performance advantages.

[0007] In view of the above problems, the existing technology needs to be improved urgently. Summary of the invention

[0008] The purpose of the present invention is to solve the shortcomings in the prior art and to propose a driving circuit for a high-voltage PMOS.

[0009] The present invention provides a driving circuit for a high-voltage PMOS, comprising a reference potential point GND, and further comprising:

[0010] The source of the first N-type MOS transistor NM1, the source of the sixth N-type MOS transistor NM6, the source of the fourth N-type MOS transistor NM4, the source of the second N-type MOS transistor NM2, the source of the fifth N-type MOS transistor NM5, and the source of the third N-type MOS transistor NM3 are connected to GND;

[0011] The negative end of the Zener diode D1, the resistor R1, the source of the first P-type MOS transistor PM1, the negative end of the Zener diode D2, the resistor R2, the source of the second P-type MOS transistor PM2, the negative end of the Zener diode D3, the resistor R3, and the drain of the third N-type MOS transistor NM3 are connected to VIN;

[0012] The drain of the first N-type MOS transistor NM1, the gate of the first N-type MOS transistor NM1, the gate of the second N-type MOS transistor NM2, and the gate of the third N-type MOS transistor NM3 are connected to the external current source IBIAS;

[0013] The driving control is used to control the on and off of the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2.

[0014] Preferably, the drive control includes four logic signals HS, HSN, HS_SHOT, and HS_SHOTB, wherein HS is a logic signal of a P-type MOS tube switch, HSN is a logic signal of HS after passing through an inverter, HS_SHOT is a logic signal of a rising edge detection of HS, and HS_SHOTB is a logic signal of a falling edge detection of HS;

[0015] The gate of the sixth N-type MOS transistor NM6 is connected to the control signal HS_SHOT, and the drain of the sixth N-type MOS transistor NM6, the positive end of the Zener diode D1, the resistor R1, and the gate of the first P-type MOS transistor PM1 are connected.

[0016] Preferably, it further includes a seventh N-type MOS transistor NM7, a gate of which is connected to the control signal HSN, and a drain of the seventh N-type MOS transistor NM7, a drain of the first P-type MOS transistor PM1, a positive end of the Zener diode D2, a resistor R2, and a gate of the second P-type MOS transistor PM2 are connected.

[0017] Preferably, it further comprises an eighth N-type MOS transistor NM8 and a voltage HS_DRV, wherein the gate of the eighth N-type MOS transistor NM8 is connected to the control signal HS;

[0018] The drain of the eighth N-type MOS tube NM8, the positive end of the Zener diode D3, the resistor R3, and the high-voltage PMOS power tube voltage HS_DRV are connected;

[0019] The source of the seventh N-type MOS transistor NM7, the drain of the fourth N-type MOS transistor NM4, and the drain of the second N-type MOS transistor NM2 are connected;

[0020] The source of the eighth N-type MOS transistor NM8, the drain of the fifth N-type MOS transistor NM5, and the drain of the third N-type MOS transistor NM3 are connected.

[0021] Preferably, the gate of the fourth N-type MOS transistor NM4 is connected to the control signal HS_SHOTB.

[0022] Preferably, the gate of the fifth N-type MOS transistor NM5 is connected to the control signal HS_SHOT.

[0023] Preferably, the sixth N-type MOS transistor NM6, the seventh N-type MOS transistor NM7 and the eighth N-type MOS transistor NM8 are high-voltage NMOS transistors, and the remaining N-type MOS transistors and P-type MOS transistors are normal-voltage transistors.

[0024] Compared with the prior art, the present invention has the following beneficial effects: the present application provides a driving circuit for a high-voltage PMOS, including a reference potential point GND, a connection structure of a plurality of N-type MOS tubes and a P-type MOS tube, and a driving control for controlling the on and off of the P-type MOS tube. Through a reasonably designed circuit structure and control logic, the gate-source voltage of the high-voltage PMOS power tube is effectively controlled, the driving capability is improved, the on-resistance is reduced, and the performance of the high-voltage PMOS power tube is optimized, which has the advantages of effectively controlling the gate-source voltage of the high-voltage PMOS power tube, improving the driving capability, reducing the on-resistance, and optimizing the performance of the high-voltage PMOS power tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic diagram of the driving circuit of the present invention;

[0026] Figure 2 This is a timing diagram of the control signal of the present invention. DETAILED DESCRIPTION

[0027] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art may think of other obvious variations.

[0028] Application scenario: In power supply systems, DC-DC converters are widely used due to their high conversion efficiency, high integration and high cost performance. In order to improve efficiency, NMOS tubes or PMOS tubes are usually selected as power tubes in DC-DC converters. NMOS tubes have smaller on-resistance, but require a higher gate voltage than the source to drive. Therefore, it is of great significance to design a driving circuit for high-voltage PMOS power tubes. In the prior art, although NMOS tubes require a smaller area under the same on-resistance and gate-source voltage, their driving voltage problem needs to be solved by bootstrap boosting technology, otherwise it will lead to increased conduction loss. In contrast, high-voltage PMOS power tubes do not require bootstrap boosting technology, but their gate-source voltage tolerance value is often 5V, and there is a risk of breakdown when it exceeds 5V. The present application proposes a driving circuit for high-voltage PMOS, which can keep the gate-source voltage stable at 5V when the high-voltage PMOS power tube is turned on, ensure safety and reduce on-resistance, while improving driving capability.

[0029] like Figure 1 to Figure 2 A driving circuit for a high-voltage PMOS is shown, comprising a reference potential point GND, and further comprising:

[0030] The source of the first N-type MOS transistor NM1, the source of the sixth N-type MOS transistor NM6, the source of the fourth N-type MOS transistor NM4, the source of the second N-type MOS transistor NM2, the source of the fifth N-type MOS transistor NM5, and the source of the third N-type MOS transistor NM3 are connected to GND;

[0031] The negative end of the Zener diode D1, the resistor R1, the source of the first P-type MOS transistor PM1, the negative end of the Zener diode D2, the resistor R2, the source of the second P-type MOS transistor PM2, the negative end of the Zener diode D3, the resistor R3, and the drain of the third N-type MOS transistor NM3 are connected to VIN; VIN refers to the input voltage, that is, the voltage provided to the circuit from an external power supply or a previous circuit.

[0032] The drain of the first N-type MOS transistor NM1, the gate of the first N-type MOS transistor NM1, the gate of the second N-type MOS transistor NM2, and the gate of the third N-type MOS transistor NM3 are connected to the external current source IBIAS;

[0033] The driving control is used to control the on and off of the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2.

[0034] As an implementation mode of the present invention, the drive control includes four logic signals HS, HSN, HS_SHOT, and HS_SHOTB, wherein HS is a logic signal of a P-type MOS tube switch, HSN is a logic signal of HS passing through an inverter, HS_SHOT is a logic signal of a rising edge detection of HS, and HS_SHOTB is a logic signal of a falling edge detection of HS;

[0035] The gate of the sixth N-type MOS transistor NM6 is connected to the control signal HS_SHOT, and the drain of the sixth N-type MOS transistor NM6, the positive end of the Zener diode D1, the resistor R1, and the gate of the first P-type MOS transistor PM1 are connected; when working, the drive control part realizes the drive control of the high-voltage PMOS power tube through four logic signals HS, HSN, HS_SHOT, and HS_SHOTB. Specifically, the HS_SHOT signal is used to detect the rising edge of the HS signal. When the HS signal changes from a low level to a high level, the HS_SHOT signal generates a pulse to drive the sixth N-type MOS transistor NM6 to turn on. After NM6 is turned on, its drain voltage is transmitted to the gate of the first P-type MOS transistor PM1 through the Zener diode D1 and the resistor R1, reducing the gate voltage of PM1, thereby turning on PM1. At this time, the conduction state of the first P-type MOS transistor PM1 can be controlled by the difference between its source voltage and gate voltage, ensuring the stable operation of the high-voltage PMOS power tube under a high-voltage environment.

[0036] Therefore, the present application realizes precise control of the high-voltage PMOS power tube by using the four logic signals HS, HSN, HS_SHOT, and HS_SHOTB. Compared with the prior art, the driving control part of the present application can effectively transmit the control signal and ensure the stable operation of the high-voltage PMOS power tube under the high-voltage environment, solving the transmission and high-voltage tolerance problems of the control signal when driving the high-voltage PMOS power tube. Furthermore, by using the HS_SHOT signal, a pulse signal can be generated at the rising edge of the HS signal to drive the sixth N-type MOS tube NM6 to turn on, thereby realizing precise control of the first P-type MOS tube PM1 and ensuring the stability and reliability of the high-voltage PMOS power tube.

[0037] As an embodiment of the present invention, it also includes a seventh N-type MOS transistor NM7, the gate of the seventh N-type MOS transistor NM7 is connected to the control signal HSN, the drain of the seventh N-type MOS transistor NM7, the drain of the first P-type MOS transistor PM1, the positive end of the Zener diode D2, the resistor R2, and the gate of the second P-type MOS transistor PM2 are connected; when working, the gate of the seventh N-type MOS transistor NM7 is connected to the control signal HSN, and the purpose of this technical feature is to adjust the on and off state of NM7 through the control signal HSN, and the drain of NM7 is connected to the positive end of the Zener diode D2, and is connected to the gate of the second P-type MOS transistor PM2 through the resistor R2. Specifically, when the HSN signal changes, the on state of NM7 will also change accordingly, thereby changing the voltage applied to the gate of PM2 through the resistor R2. This design can ensure that when the control signal changes, the gate voltage of PM2 can be adjusted in time, thereby realizing accurate drive control of the high-voltage PMOS power tube.

[0038] Through this technical solution, the present application can accurately control the gate voltage of the high-voltage PMOS power tube during high-voltage driving, avoiding the risk of high-voltage PMOS power tube breakdown caused by excessive gate-source voltage. Compared with the prior art, the present application improves the reliability and stability of the circuit, reduces power loss, and enhances driving capability.

[0039] As an implementation mode of the present invention, it also includes an eighth N-type MOS transistor NM8 and a voltage HS_DRV, wherein the gate of the eighth N-type MOS transistor NM8 is connected to the control signal HS;

[0040] The drain of the eighth N-type MOS tube NM8, the positive end of the Zener diode D3, the resistor R3, and the gate voltage HS_DRV of the external high-voltage PMOS power tube are connected;

[0041] The source of the seventh N-type MOS transistor NM7, the drain of the fourth N-type MOS transistor NM4, and the drain of the second N-type MOS transistor NM2 are connected;

[0042] The source of the eighth N-type MOS tube NM8, the drain of the fifth N-type MOS tube NM5, and the drain of the third N-type MOS tube NM3 are connected; when working, the gate of the eighth N-type MOS tube NM8 is connected to the control signal HS, so that it can respond quickly when the HS signal changes, ensuring the rapidity and accuracy of the control. The drain of the eighth N-type MOS tube NM8 is connected to the positive end of the Zener diode D3, the resistor R3, and the gate voltage HS_DRV of the high-voltage PMOS power tube. The Zener diode D3 is used to stabilize the gate voltage to prevent voltage fluctuations from affecting the stable conduction of the high-voltage PMOS power tube. The source of the seventh N-type MOS tube NM7 is connected to the drain of the fourth N-type MOS tube NM4 and the drain of the second N-type MOS tube NM2, and the source of the eighth N-type MOS tube NM8 is connected to the drain of the fifth N-type MOS tube NM5 and the drain of the third N-type MOS tube NM3. These connection methods realize the reasonable distribution of the current path and the effective transmission of the control signal, ensuring the overall stability and reliability of the circuit.

[0043] The present application achieves stable control of the gate-source voltage of the high-voltage PMOS power tube by introducing the eighth N-type MOS tube NM8, the Zener diode D3 and other components into the high-voltage PMOS power tube driving circuit and designing a reasonable circuit connection method. Compared with the prior art, the present application can ensure the stability of the gate voltage when the high-voltage PMOS power tube is turned on, avoid the breakdown risk caused by excessive voltage, and achieve low on-resistance. In addition, through reasonable current path distribution and control signal transmission, the rapid response and stability of the circuit are ensured, and the safety and reliability of the driving circuit are improved.

[0044] As an embodiment of the present invention, the gate of the fourth N-type MOS tube NM4 is connected to the control signal HS_SHOTB; when working, the gate of the fourth N-type MOS tube NM4 is connected to the control signal HS_SHOTB, and the on and off of NM4 is controlled by the change of the control signal HS_SHOTB. When the control signal HS_SHOTB detects that the falling edge signal of HS generates a pulse, NM4 is turned on, thereby ensuring that the high-voltage PMOS power tube is stably turned on. In this way, the gate-source voltage of the high-voltage PMOS power tube can be stabilized when the high-voltage PMOS power tube is turned on, avoiding the risk of exceeding 5V, and ensuring the safety of the circuit. At the same time, this design can also effectively reduce the on-resistance of the high-voltage PMOS power tube, reduce the delay time from the control signal to the high-voltage PMOS power tube switch, and improve the driving capability.

[0045] As an implementation mode of the present invention, the gate of the fifth N-type MOS transistor NM5 is connected to the control signal HS_SHOT; when working, the control signal HS_SHOT is used to control the on and off of the fifth N-type MOS transistor NM5. Through the above technical features, when the control signal HS_SHOT detects the rising edge signal of HS, NM5 is turned on, so that the high-voltage PMOS power tube is quickly turned on; when the control signal HS_SHOT detects the falling edge signal of HS, NM5 is turned off, so that the high-voltage PMOS power tube is quickly turned off, thereby solving the delay time and driving capability problems from the control signal to the high-voltage PMOS power tube switch in the high-voltage PMOS drive circuit.

[0046] As an embodiment of the present invention, the sixth N-type MOS tube NM6, the seventh N-type MOS tube NM7 and the eighth N-type MOS tube NM8 are high-voltage NMOS tubes, and the remaining N-type MOS tubes and P-type MOS tubes are all normal-voltage tubes; when working, the sixth N-type MOS tube NM6, the seventh N-type MOS tube NM7 and the eighth N-type MOS tube NM8 are high-voltage NMOS tubes, which can withstand the working requirements under the high-voltage environment, and the remaining N-type MOS tubes and P-type MOS tubes are normal-voltage tubes, which are suitable for processing control signals with lower voltages. Through this combination design of high-voltage and normal-voltage tubes, the stability and safety of the circuit under high-voltage environments are ensured, while the on-resistance of the high-voltage PMOS power tube is reduced. This design scheme uses high-voltage NMOS tubes to handle the driving requirements under high-voltage environments, ensures that the high-voltage PMOS power tube can work stably under high-voltage environments, and the gate-source voltage is stable at 5V when turned on, avoiding the risk of breakdown. The normal-voltage tube is used for processing control signals, and cooperates with the work of the high-voltage tube to ensure the stability and efficiency of the overall circuit.

[0047] Control principle of the present invention: The present application reasonably designs the driving circuit so that the gate-source voltage of the high-voltage PMOS power tube is stabilized at 5V when it is turned on. Specifically, the source of the first N-type MOS tube NM1 is connected to GND, and its drain and gate are connected to the external current source IBIAS, and the negative end of the Zener diode D1, the resistor R1, and the source of the first P-type MOS tube PM1 are connected to VIN. The driving control part is used to control the on and off of the first P-type MOS tube PM1 and the second P-type MOS tube PM2. Through this design, it is ensured that the gate-source voltage of the high-voltage PMOS power tube is stabilized at 5V when it is turned on, thereby ensuring the safety and reliability of the circuit.

[0048] Specifically, when HS changes from low to high, HSN changes from high to low, HS_SHOT detects the rising edge signal of HS and generates a pulse, so that NM6 is turned on, and a large current passes through the Zener diode D1 to reduce the gate voltage of PM1 to VIN-VD1. At this time, PM1 is turned on, PM2 is turned off, NM8 is turned on, and HS_DRV is VIN-VD3, so that the high-voltage PMOS power tube is turned on. When HS changes from high to low, HSN changes from low to high, HS_SHOTB detects the falling edge signal of HS and generates a pulse, NM4 is turned on, NM7 is turned on, and a large current passes through the Zener diode D2 to reduce the gate voltage of PM2 to VIN-VD2. At this time, PM2 is turned on, NM8 is turned off, and HS_DRV is VIN, so that the high-voltage PMOS power tube is turned off.

[0049] It should be noted that this circuit is applied to high-voltage PMOS power tubes. Through the reasonably designed circuit structure and control logic, the gate-source voltage of the high-voltage PMOS power tube is effectively controlled, and the driving capability is improved. HS_DRV is the gate voltage of the high-voltage PMOS power tube;

[0050] When NM6 is turned on, a large current passes through the Zener diode D1, and the Zener diode D1 generates a fixed voltage drop VD1. VIN-VD1 indicates that the gate voltage of the first P-type MOS transistor PM1 is obtained by subtracting the voltage drop VD1 of the Zener diode D1 from the source voltage. At this time, the source voltage is the input voltage VIN. VIN-VD1 makes the gate voltage of the first P-type MOS transistor PM1 lower than the source voltage, thereby turning on the first P-type MOS transistor PM1.

[0051] When HS changes from high to low, NM4 and NM7 are turned on, and a large current passes through the Zener diode D2. D2 generates a fixed voltage drop VD2. VIN-VD2 indicates that the gate voltage of the second P-type MOS transistor PM2 is obtained by subtracting the voltage drop VD2 of the Zener diode D2 from the source voltage. At this time, the source voltage is the input voltage VIN. VIN-VD2 makes the gate voltage of the second P-type MOS transistor PM2 lower than the source voltage, thereby turning on the second P-type MOS transistor PM2.

[0052] When PM1 is turned on, NM8 is also turned on, and current passes through the Zener diode D3. D3 generates a fixed voltage drop VD3, and the voltage of HS_DRV = VIN - VD3; VIN-VD3 means that the gate voltage of the high-voltage PMOS power tube is obtained by subtracting the voltage drop VD3 of the Zener diode D3 from the source voltage. At this time, the source voltage is the input voltage VIN. VIN - VD3 makes the gate voltage of the high-voltage PMOS power tube lower than the source voltage, thereby turning on the high-voltage PMOS power tube.

[0053] Compared with the prior art, the present application avoids the problem of the NMOS tube needing the self-boosting voltage-boosting technology by reasonably designing the driving circuit, and at the same time ensures that the gate-source voltage of the high-voltage PMOS power tube is stable at 5V when it is turned on, reduces the on-resistance, improves the driving capability, and reduces the delay time when the control signal reaches the switch of the high-voltage PMOS power tube. Through this design, the present application has achieved a technological breakthrough in the design of the driving circuit of the high-voltage PMOS power tube, and has significant innovation and practicality.

[0054] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments, and the above embodiments and descriptions only describe the principles of the present invention. The present invention may be subject to various changes and improvements without departing from the spirit and scope of the present invention, and these changes and improvements fall within the scope of the present invention claimed.

Claims

1. A driving circuit for a high voltage PMOS, comprising a reference potential point GND, characterized in that: Also includes: The source of the first N-type MOS transistor NM1, the source of the sixth N-type MOS transistor NM6, the source of the fourth N-type MOS transistor NM4, the source of the second N-type MOS transistor NM2, the source of the fifth N-type MOS transistor NM5, and the source of the third N-type MOS transistor NM3 are connected to GND; The negative end of the Zener diode D1, the resistor R1, the source of the first P-type MOS transistor PM1, the negative end of the Zener diode D2, the resistor R2, the source of the second P-type MOS transistor PM2, the negative end of the Zener diode D3, the resistor R3, and the drain of the third N-type MOS transistor NM3 are connected to VIN; The drain of the first N-type MOS transistor NM1, the gate of the first N-type MOS transistor NM1, the gate of the second N-type MOS transistor NM2, and the gate of the third N-type MOS transistor NM3 are connected to the external current source IBIAS; Drive control, used to control the on and off of the first P-type MOS transistor PM1 and the second P-type MOS transistor PM2; The drive control includes four logic signals HS, HSN, HS_SHOT, and HS_SHOTB, wherein HS is a logic signal of a P-type MOS tube switch, HSN is a logic signal of HS after passing through an inverter, HS_SHOT is a logic signal of a rising edge detection of HS, and HS_SHOTB is a logic signal of a falling edge detection of HS; The gate of the sixth N-type MOS transistor NM6 is connected to the control signal HS_SHOT, and the drain of the sixth N-type MOS transistor NM6, the positive end of the Zener diode D1, the resistor R1, and the gate of the first P-type MOS transistor PM1 are connected; It also includes a seventh N-type MOS transistor NM7, the gate of which is connected to the control signal HSN, and the drain of which, the drain of the first P-type MOS transistor PM1, the positive end of the Zener diode D2, the resistor R2, and the gate of the second P-type MOS transistor PM2 are connected; It also includes an eighth N-type MOS transistor NM8, wherein the gate of the eighth N-type MOS transistor NM8 is connected to the control signal HS; The drain of the eighth N-type MOS transistor NM8, the drain of the second P-type MOS transistor PM2, the positive end of the Zener diode D3, the resistor R3, and the gate voltage HS_DRV of the external high-voltage PMOS power tube are connected; The source of the seventh N-type MOS transistor NM7, the drain of the fourth N-type MOS transistor NM4, and the drain of the second N-type MOS transistor NM2 are connected; The source of the eighth N-type MOS transistor NM8, the drain of the fifth N-type MOS transistor NM5, and the drain of the third N-type MOS transistor NM3 are connected; The gate of the fourth N-type MOS transistor NM4 is connected to the control signal HS_SHOTB; The gate of the fifth N-type MOS transistor NM5 is connected to the control signal HS_SHOT.

2. A driving circuit for a high voltage PMOS according to claim 1, characterized in that: The sixth N-type MOS transistor NM6, the seventh N-type MOS transistor NM7 and the eighth N-type MOS transistor NM8 are high-voltage NMOS transistors, and the remaining N-type MOS transistors and P-type MOS transistors are normal-voltage transistors.

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