Method for eliminating burrs generated by asynchronous reset, FIFO circuit, chip and electronic equipment
The method addresses asynchronous reset-induced glitches in FIFO circuits by determining and applying necessary delays to reset signals, using multiplexers and logical operations to stabilize outputs, ensuring reliable asynchronous FIFO operation.
Patent Information
- Application Number
- CN202411720422.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-03-21
AI Technical Summary
Asynchronous reset signals in FIFO circuits can cause glitches due to timing differences in the placement of read/write pointers and path delays, leading to competitive and adventurous phenomena, which may result in invalid signal production and potential module hang-ups.
The method involves determining the necessary delay for asynchronous FIFO reset signals using a cycle selection signal, applying this delay through registers, and employing multiplexers to select and process the signals, ultimately performing logical operations to eliminate glitches by stabilizing the output.
This approach ensures stable and accurate output signals by addressing the timing discrepancies and competitive issues in asynchronous FIFO circuits, preventing glitches and ensuring reliable operation.
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Figure CN119675653A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of signal processing technology, and in particular to a method for eliminating burrs generated by asynchronous reset, a FIFO circuit, a chip and an electronic device. Background Art
[0002] Reset signal is an essential and important component of existing chips. Reset can change the chip circuit from an unknown state to a known and certain state. Asynchronous reset does not need to insert additional logic like synchronous reset, which reduces resource consumption and becomes a widely used reset design in digital circuit design. However, since asynchronous reset does not require a clock and has no fixed phase relationship with the clock, it may also cause potential risks. For example, in a typical asynchronous FIFO (First In First Out) design, in order to maximize the FIFO performance, empty signal (empty signal) and full signal (full signal) are usually used as output signals (valid signals). The empty signal and full signal are generated by comparing the FIFO read and write pointers. This is a combinational logic design. If the FIFO depth is deep, the read and write pointers are usually multi-bit signals. When an asynchronous reset occurs, due to the placement of each bit of the read and write pointer register, the path delay, and the possible combinational logic delay, the time to reach the FIFO empty signal and full signal comparison logic is different, which may cause competition and risk, and then cause the valid signal to have a burr risk. If the burr is picked up by the downstream module, it is likely to cause the path to hang. Summary of the invention
[0003] The purpose of the embodiments of the present application is to provide a method for eliminating glitches generated by asynchronous reset, a FIFO circuit, a chip and an electronic device, wherein the method is used to solve the problem that an asynchronous reset signal in an asynchronous FIFO circuit causes glitches in an output signal.
[0004] The embodiment of the present application adopts the following technical solution: a method for eliminating burrs generated by asynchronous reset, applied to an asynchronous FIFO circuit, the method comprising:
[0005] Based on the reset glitch of the asynchronous FIFO reset signal, the glitch duration that needs to be shielded determines the cycle selection signal;
[0006] Based on the cycle selection signal, the asynchronous FIFO reset signal is delayed through the register to obtain a delayed FIFO reset signal corresponding to the current cycle selection signal;
[0007] The first multiplexer selects and outputs the delay FIFO reset signal based on the mask selection signal to obtain a first output signal and a second output signal;
[0008] Determining a transient signal of the asynchronous FIFO based on the first output signal and a generation mechanism of the asynchronous FIFO output signal;
[0009] Based on the mask selection signal, determining a method of performing a first AND logic operation on the second output signal and / or the asynchronous FIFO reset signal to obtain a first AND logic output signal;
[0010] The second multiplexer selects and outputs the first AND logic output signal based on the shielding selection signal to obtain a shielding signal;
[0011] A second AND logic operation is performed on the shielding signal and the transient signal to obtain a glitch-free output signal of the asynchronous FIFO.
[0012] In some embodiments, based on the cycle selection signal, delay processing is performed on the asynchronous FIFO reset signal through a register, including:
[0013] Determining the number of required registers based on the cycle selection signal, wherein the number of registers is the same as the value of the cycle selection signal;
[0014] The asynchronous FIFO reset signal is delayed by determining the number of registers.
[0015] In some embodiments, the first multiplexer selects and outputs the delay FIFO reset signal based on the mask selection signal to obtain the first output signal and the second output signal, including:
[0016] When the reset glitch of the asynchronous FIFO reset signal is a rising edge reset glitch, determining that the shielding selection signal is a first shielding selection signal;
[0017] Selecting and outputting the delay FIFO reset signal based on the first mask selection signal to obtain a third output signal and a fourth output signal, wherein the third output signal is one of the first output signals, and the fourth output signal is one of the second output signals;
[0018] When the reset glitch of the asynchronous FIFO reset signal is a falling edge reset glitch, determining that the shielding selection signal is a second shielding selection signal;
[0019] The delay FIFO reset signal is selectively output based on the second mask selection signal to obtain a fifth output signal and a sixth output signal, wherein the fifth output signal is one of the first output signals, and the sixth output signal is one of the second output signals.
[0020] In some embodiments, based on the mask selection signal, determining a manner of performing a first AND logic operation on the second output signal and / or the asynchronous FIFO reset signal to obtain a first AND logic output signal includes:
[0021] Based on the first shielding selection signal, a first operation is performed, the first operation comprising:
[0022] Performing an AND logic operation on the fourth output signal and the asynchronous FIFO reset signal to obtain a first position shielding signal;
[0023] Based on the second shielding selection signal, a second operation is performed, the second operation comprising:
[0024] Determine that the asynchronous FIFO reset signal is a second position masking signal;
[0025] When the shielding selection signal is a third shielding selection signal, performing a third operation, wherein the third shielding selection signal includes the first shielding selection signal and the second shielding selection signal;
[0026] The third operation includes performing an AND logic operation on the first position mask signal and the asynchronous FIFO reset signal to obtain a third position mask signal.
[0027] In some embodiments, the second multiplexer selects and outputs the first AND logic output signal based on the shielding selection signal to obtain a shielding signal, including:
[0028] The second multiplexer determines the first position shielding signal as the shielding signal based on the first shielding selection signal;
[0029] The second multiplexer determines the second position shielding signal as the shielding signal based on the second shielding selection signal;
[0030] The second multiplexer determines the third position masking signal as the masking signal based on the third masking selection signal.
[0031] In some embodiments, determining the transient signal of the asynchronous FIFO based on the first output signal and a generation mechanism of the asynchronous FIFO output signal includes:
[0032] Determine a transient signal of the asynchronous FIFO based on the first output signal and a comparison result of the asynchronous FIFO read pointer and the asynchronous FIFO write pointer;
[0033] The read pointer and the write pointer are pointers that have crossed the read and write clock domains.
[0034] In some embodiments, the method further comprises:
[0035] Before issuing the asynchronous FIFO reset signal, the cycle selection signal and a manner of performing a first AND logic operation on the second output signal and / or the asynchronous FIFO reset signal are configured.
[0036] The embodiment of the present application further provides a FIFO circuit, including:
[0037] A register, used for receiving an asynchronous FIFO reset signal and a clock signal, and outputting a delayed FIFO reset signal after delay processing respectively;
[0038] a first multiplexer connected to each of the registers, respectively, for receiving a cycle selection signal, a mask selection signal, and an asynchronous FIFO reset signal or a delayed FIFO reset signal after delay processing, and outputting a first output signal and a second output signal;
[0039] A first AND logic operation component, connected to the first multiplexer, configured to receive the second output signal and an asynchronous FIFO reset signal, and output a first AND logic output signal;
[0040] an asynchronous FIFO connected to the first multiplexer, configured to receive the first output signal and output a transient signal;
[0041] a second multiplexer connected to the first AND logic operation component, configured to receive the first AND logic output signal and a shielding selection signal, and output a shielding signal;
[0042] The second AND logic gate is connected to the asynchronous FIFO and the second multiplexer respectively, and performs an AND logic operation on the transient signal and the shielding signal to obtain a glitch-free output signal of the asynchronous FIFO.
[0043] The embodiment of the present application also provides a chip, which eliminates reset burrs of asynchronous reset signals by using any of the methods described in the above embodiments.
[0044] An embodiment of the present application also provides an electronic device, comprising the chip as described in the above embodiment.
[0045] The beneficial effects of the embodiments of the present application are:
[0046] The asynchronous FIFO reset signal is delayed by the register to obtain a delayed FIFO reset signal with a stable state. Then, the delayed FIFO reset signal is selected and output by the first multiplexer based on the shielding selection signal to output the first output signal and the second output signal. The asynchronous FIFO outputs the transient signal of the asynchronous FIFO based on the first output signal and the generation mechanism of its output signal; the second output signal and / or the asynchronous FIFO reset signal are subjected to a first AND logic operation to obtain a first AND logic output signal; the second multiplexer selects and outputs the first AND logic output signal based on the shielding selection signal to obtain a shielding signal, and then performs an AND logic operation on the shielding signal and the transient signal to obtain a glitch-free output signal, thereby ensuring the stability and accuracy of the output signal of the asynchronous FIFO circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0048] Figure 1 Schematic diagram of glitch caused by asynchronous reset FIFO;
[0049] Figure 2 This is a schematic diagram of the structure of the asynchronous FIFO circuit of this application;
[0050] Figure 3 A flow chart of a method for eliminating burrs generated by asynchronous reset for the present application;
[0051] Figure 4 For this application Figure 3 A flowchart of one embodiment of step S20;
[0052] Figure 5 For this application Figure 3 A flowchart of one embodiment of step S30;
[0053] Figure 6 Schematic diagram for eliminating glitches caused by the rising edge of asynchronous FIFO reset for this application;
[0054] Figure 7 Schematic diagram for eliminating glitches caused by the falling edge of asynchronous FIFO reset for this application;
[0055] Figure 8 For this application Figure 3 Flow chart of one embodiment of step S50 in FIG. DETAILED DESCRIPTION
[0056] Various aspects and features of the present application are described herein with reference to the accompanying drawings.
[0057] It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of an embodiment. Other modifications within the scope and spirit of the present application will occur to those skilled in the art.
[0058] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.
[0059] These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.
[0060] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art will be able to readily implement many other equivalent forms of the present application.
[0061] The above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.
[0062] Specific embodiments of the present application are described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments applied for are merely examples of the present application, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that obscure the present application. Therefore, the specific structural and functional details applied for herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present application in a variety of ways with substantially any suitable detailed structure.
[0063] This specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present application.
[0064] The embodiment of the present application provides a method for eliminating burrs caused by asynchronous reset, which is applied to circuit design caused by asynchronous reset, such as asynchronous FIFO reset circuit. Asynchronous FIFO design refers to the implementation of a FIFO buffer with two independent clock domains in digital IC (Integrated Circuit) design. The characteristic of this FIFO is that its read and write operations are respectively performed by two different and independent clock signals (such as Figure 2The write pointer points to the next data unit to be written, and the read pointer points to the data unit to be read. At reset, the read and write pointers usually point to the first data unit (numbered 0). Full signal: When the FIFO is full, it is sent by the FIFO status circuit to prevent further write operations and prevent data overflow. Empty signal: When the FIFO is empty, it is sent by the FIFO status circuit to prevent further read operations and prevent invalid data from being read. The empty and full signals are generated by comparing the read and write pointers. Figure 2 The vld_in in is the data valid input indication signal of the asynchronous FIFO circuit, which is used to indicate the validity of the data input to the FIFO. Due to the influence of the asynchronous reset, its output signal vld_pre may generate glitches, which will affect the next level circuit design if it is not processed. Asynchronous FIFO can be used in scenarios where data needs to be transmitted across clock domains. For example, a system may contain multiple clock domains, and data needs to be exchanged between these clock domains.
[0065] Combination Figure 1 The principle of asynchronous reset FIFO causing glitches is as follows: Normally, in order to maximize FIFO performance, the output valid signal is determined by the FIFO empty and full signals. Normally, in order to cache data, the depth of FIFO is generally not 1, so the read and write pointers are multi-bit signals. Ideally, when the reset signal comes, the read and write pointers jump at the same time, that is, the delay time in the figure is the same. In reality, affected by various factors such as temperature, layout routing, and Gray code decoding, the fan-out of each register of the chip is different, and the time delay (delay) in the figure is different. The time to compare in the combinational logic is different, so the read and write pointers are transient when the reset signal comes. In the design of asynchronous reset FIFO, the data valid indication signal (Valid) output to the next level circuit design is generated by the read and write pointers through the combinational logic comparison. There are competition and risk phenomena in the combinational logic circuit design, which causes glitches on the valid signal.
[0066] To solve the above problems, combined with Figure 2 and Figure 3 The method for eliminating burrs generated by asynchronous reset in the embodiment of the present application includes:
[0067] S10, determining a period selection signal based on the duration of the glitch that needs to be shielded.
[0068] Exemplarily, the cycle selection signal is determined according to the glitch duration that needs to be shielded for the reset glitch of the asynchronous FIFO reset signal (async_rst signal). For example, if the glitch is within one clock cycle, the cycle selection signal is 0. If the glitch may occur in multiple clock cycles, for example, there will be glitches in two clock cycles, the cycle selection signal can be set to 1. Of course, it is understandable that the cycle selection signal can also be other values, which are specifically determined by the glitch duration. The glitch duration can be estimated through gate-level simulation and cross-clock domain analysis.
[0069] S20, based on the cycle selection signal, delay processing is performed on the asynchronous FIFO reset signal through a register to obtain a delayed FIFO reset signal corresponding to the current cycle selection signal.
[0070] Exemplarily, in combination with the above embodiment, when the cycle selection signal is 1, the asynchronous FIFO reset signal can be delayed through a register (DFF) to obtain a delayed FIFO reset signal corresponding to the cycle selection signal 1. When the cycle selection signal is 0, the asynchronous FIFO reset signal can be delayed without the register, and the asynchronous FIFO reset signal is determined to be a delayed FIFO reset signal corresponding to the cycle selection signal 0. That is, the delayed FIFO reset signal does not necessarily have to be delayed by the register.
[0071] The number of registers can be reasonably set according to the cycle selection signal, and the asynchronous FIFO reset signal can be delayed through multiple registers as needed.
[0072] S30, the first multiplexer selects and outputs the delay FIFO reset signal based on the mask selection signal to obtain a first output signal and a second output signal.
[0073] Exemplarily, the first multiplexer (MUX 1) selects and outputs the delay FIFO reset signal based on the mask selection signal (mask_select), and obtains a first output signal (rst_vld) and a second output signal (mask_nxt) corresponding to the current delay FIFO reset signal, and the second output signal is an output signal delayed by a register.
[0074] Inevitably, due to the existence of registers, the asynchronous reset signal will be delayed by several clock cycles compared to before. In order to improve the reset response speed and increase the reset efficiency, a shielding selection signal is designed. The shielding selection signal is used to select and shield the glitches caused by the rising edge, falling edge or double edge of the asynchronous reset signal. In this way, if it is determined that a certain asynchronous reset edge will not cause glitches, it can be set not to be shielded, and the delayed reset effect is consistent with the asynchronous reset signal initially input, reducing the impact of this application on the reset and improving the reset efficiency.
[0075] The first output signal is used as one of the input signals of the asynchronous FIFO, and the second output signal is used to perform subsequent operations according to the mask selection signal.
[0076] S40: Determine a transient signal of the asynchronous FIFO based on the first output signal and a generation mechanism of the asynchronous FIFO output signal.
[0077] Exemplarily, after receiving the first output signal, the asynchronous FIFO outputs a transient signal (vld_pre) of the asynchronous FIFO according to a generation mechanism of the asynchronous FIFO output signal. Here, the generation mechanism of the asynchronous FIFO output signal includes the generation of the output signal by the asynchronous FIFO based on the comparison result of the read pointer and the write pointer. Here, the generation of the transient signal of the asynchronous FIFO also takes into account the first output signal. The transient signal of the asynchronous FIFO is output as a transient output signal, not as a valid signal of the asynchronous FIFO circuit.
[0078] S50, based on the mask selection signal, determining a manner of performing a first AND logic operation on the second output signal and / or the asynchronous FIFO reset signal to obtain a first AND logic output signal.
[0079] Exemplarily, when the shielding selection signal is used to shield the edge glitches of different asynchronous reset signals, the second output signal and / or the asynchronous FIFO reset signal are processed in different ways. Therefore, it is necessary to determine the way to perform the first AND logic operation on the second output signal and / or the asynchronous FIFO reset signal based on the shielding selection signal, and then obtain the first AND logic output signal. Corresponding to different shielding selection signals, the obtained first AND logic output signal is also different.
[0080] S60: The second multiplexer selects and outputs the first AND logic output signal based on the shielding selection signal to obtain a shielding signal.
[0081] Exemplarily, the first AND logic output signal serves as an input signal of the second multiplexer (MUX 2), and the second multiplexer can select and output the first AND logic output signal based on the mask selection signal to obtain a mask signal (mask signal), and the mask signal is used as a glitch mask signal of the vld_pre signal.
[0082] S70, performing a second AND logic operation on the shielding signal and the transient signal to obtain a glitch-free output signal of the asynchronous FIFO.
[0083] Exemplarily, the mask signal and the vld_pre signal are further output through a second AND logic to mask the glitch of the vld_pre signal through the mask signal, and finally generate a clean, glitch-free output signal (vld_out signal) of the asynchronous FIFO.
[0084] The embodiment of the present application delays the asynchronous FIFO reset signal through a register to obtain a delayed FIFO reset signal with a stable state. Then, the first multiplexer selects and outputs the first output signal and the second output signal based on the shielding selection signal for the delayed FIFO reset signal. The asynchronous FIFO outputs the transient signal of the asynchronous FIFO based on the first output signal and the generation mechanism of its output signal; the second output signal and / or the asynchronous FIFO reset signal are subjected to a first AND logic operation to obtain a first AND logic output signal; the second multiplexer selects and outputs the first AND logic output signal based on the shielding selection signal to obtain a shielding signal, and then performs an AND logic operation on the shielding signal and the transient signal to obtain a glitch-free output signal, thereby ensuring the stability and accuracy of the output signal of the asynchronous FIFO circuit.
[0085] In some embodiments, in combination Figure 4 , based on the cycle selection signal, delay processing is performed on the asynchronous FIFO reset signal through a register, including:
[0086] S21, determining the number of required registers based on the cycle selection signal, wherein the number of registers is the same as the value of the cycle selection signal.
[0087] Exemplarily, when the cycle selection signal is 0, the asynchronous FIFO reset signal may not be delayed through the register, and the number of registers may be 0. When the cycle selection signal is 1, the number of registers may be 1, and the asynchronous FIFO reset signal may be delayed through one register. The function of the register is to delay the asynchronous FIFO reset signal for a certain clock cycle, and then transmit the first output signal through the first multiplexer. Several registers select several clocks to shield the valid signal duration. It is also possible to further add the number of registers to increase the valid shielding duration as needed, that is, to estimate the valid glitch duration through gate-level simulation and cross-clock domain analysis.
[0088] The present application uses a typical asynchronous FIFO (Async FIFO) design to generate glitches as an example, and designs applicable to the present application include but are not limited to asynchronous FIFO circuit designs.
[0089] S22, performing delay processing on the asynchronous FIFO reset signal by using a determined number of registers.
[0090] For example, when only one register is required, the asynchronous FIFO reset signal can be delayed by one clock cycle through one register; when multiple registers are required, the asynchronous FIFO reset signal can be delayed by multiple clock cycles through multiple registers.
[0091] In some embodiments, in combination Figure 5 The first multiplexer selects and outputs the delay FIFO reset signal based on the shielding selection signal to obtain a first output signal and a second output signal, including:
[0092] S31, when the reset glitch of the asynchronous FIFO reset signal is a rising edge reset glitch, determining that the mask selection signal is a first mask selection signal.
[0093] S32, based on the first shielding selection signal, the delay FIFO reset signal is selected and output to obtain a third output signal and a fourth output signal, wherein the third output signal is one of the first output signals, and the fourth output signal is one of the second output signals.
[0094] Exemplary, combined Figure 2 and Figure 6 In actual chips, the register value may change when the reset is released. If the register is also used as a combinational logic fan-out or other situations, there may also be a glitch problem caused by asynchronous reset release, that is, the rising edge of the asynchronous reset causes a glitch. The timing diagram for eliminating the glitch is as follows: Figure 6To improve the reset efficiency, when mask_select is to mask the rising edge reset glitch, the async_rst signal is input into the first multiplexer through the path 1 connected to the first multiplexer, and is output as the third output signal of the first multiplexer, that is, the third output signal (i.e. Figure 2 and Figure 6 The rst_vld signal in the async_rst signal is not delayed by the register, so as not to affect the reset falling edge and reduce the impact of the present application on the reset action time. The mask_nxt signal is the fourth output signal after the register delay. Figure 6 In the timing diagram shown, cycle_select is set to 1, that is, the valid masking duration is 1 clock edge, so the mask_nxt signal is the signal output from the first multiplexer (MUX1) after the async_rst signal passes through the first register. The async_rst signal and mask_nxt are ANDed through the first AND gate (&1) and output as the mask_pos signal, which is selected as the mask signal by MUX 2 and used as the glitch masking signal of the vld_pre signal. The mask signal and the vld_pre signal are further outputted through the second AND logic operation, and finally a clean, glitch-free vld_out signal is generated.
[0095] S33, when the reset glitch of the asynchronous FIFO reset signal is a falling edge reset glitch, determining that the mask selection signal is a second mask selection signal.
[0096] S34, based on the second mask selection signal, the delay FIFO reset signal is selected and output to obtain a fifth output signal and a sixth output signal, wherein the fifth output signal is one of the first output signals, and the sixth output signal is one of the second output signals.
[0097] Exemplary, combined Figure 2 and Figure 7 When mask_select is used to mask the falling edge reset glitch, the cycle_select signal is configured as 2. The cycle_select signal selects the 2nd level register to delay the async_rst signal by two clock cycle edges. The purpose is to obtain the reset signal rst_vld that is truly used for reset. At the same time, the asynchronous FIFO reset signal can be synchronized at two levels to avoid unexpected cross-clock domain problems and increase reset stability. The delayed signal is transmitted through Figure 2 The path 3 between the middle register and the first multiplexer is input to the first multiplexer and serves as the fifth output signal (i.e. Figure 2 and Figure 7The rst_vld signal in the output is used as a true asynchronous reset signal.
[0098] In some embodiments, in combination Figure 8 , based on the mask selection signal, determining a method of performing a first AND logic operation on the second output signal and / or the asynchronous FIFO reset signal to obtain a first AND logic output signal, comprising:
[0099] S51: performing a first operation based on the first shielding selection signal, where the first operation includes:
[0100] An AND logic operation is performed on the fourth output signal and the asynchronous FIFO reset signal to obtain a first position masking signal.
[0101] Exemplary, combined Figure 2 and Figure 6 When mask_select is used to mask the rising edge reset glitch, the masking time is selected by the cycle_select signal as needed, and the async_rst signal delayed by the register is output as the fourth output signal ( Figure 2 The mask_nxt signal in the async_rst signal is output as a first position mask signal (mask_pos signal) through a first AND gate.
[0102] S52: performing a second operation based on the second shielding selection signal, where the second operation includes:
[0103] The asynchronous FIFO reset signal is determined to be a second position mask signal.
[0104] Exemplary, combined Figure 2 and Figure 7 , when mask_select is to mask the falling edge reset glitch, the async_rst signal is used as the mask_pre signal, and the mask_pre signal is used as the second position mask signal ( Figure 2 The mask_nge signal in ), which is then selected by the second multiplexer and used as the mask signal ( Figure 2 The mask signal in is used to mask the glitch generated by vld_pre caused by the falling edge of reset.
[0105] S53 , performing a third operation when the shielding selection signal is a third shielding selection signal, wherein the third shielding selection signal includes the first shielding selection signal and the second shielding selection signal.
[0106] The third operation includes performing an AND logic operation on the first position mask signal and the asynchronous FIFO reset signal to obtain a third position mask signal.
[0107] For example, when it is necessary to shield the double-edge reset glitch (rising edge reset glitch and falling edge reset glitch), the original async_rst signal is used as the rst_vld signal after the register delay, and the mask_pre and mask_pos signals are used to perform the AND logic operation through the second AND gate (&2) to output the signal mask_boe as the mask signal, so as to more stably shield the glitches that may be caused by the double edges of the asynchronous FIFO reset signal.
[0108] In some embodiments, the second multiplexer selects and outputs the first AND logic output signal based on the shielding selection signal to obtain a shielding signal, including:
[0109] The second multiplexer determines the first position mask signal as the mask signal based on the first mask selection signal.
[0110] The second multiplexer determines the second position mask signal as the mask signal based on the second mask selection signal.
[0111] The second multiplexer determines the third position masking signal as the masking signal based on the third masking selection signal.
[0112] That is, the second multiplexer (MUX 2) is used to output different position shielding signals as shielding signals in the case of different shielding selection signals, so as to shield the burrs generated by vld_pre.
[0113] In some embodiments, determining the transient signal of the asynchronous FIFO based on the first output signal and a generation mechanism of the asynchronous FIFO output signal includes:
[0114] Based on the first output signal and the comparison result of the asynchronous FIFO read pointer (rd_ptr) and the write pointer (wr_ptr), the transient signal of the asynchronous FIFO is determined, wherein the read pointer and the write pointer are pointers that have been crossed across the read and write clock domains.
[0115] Exemplary, combined Figure 2 , Figure 6 and Figure 7In an asynchronous FIFO, the values of the read and write pointers cannot be determined when reset occurs, and there is a high probability that there is a non-zero value. In general, the reset values of the write pointer (wr_ptr) and the read pointer (rd_ptr) are 0. Due to the influence of temperature, layout routing, Gray code decoding and other factors, transient states will be generated. When the read pointer and the write pointer are inconsistent, a transient vld_pre signal, i.e., a glitch, will be generated. When mask_select is used to shield the falling edge reset glitch, the async_rst signal is used as the mask_nge signal, which is selected as the mask signal by MUX 2. The mask signal and the vld_pre signal are further output through the second AND logic (the third AND gate &3), and finally the glitch generated by the vld_pre signal is shielded, generating a glitch-free vld_out signal.
[0116] This application only addresses the problem of asynchronous reset causing glitches in combinational logic output, and does not consider the problem of asynchronous reset and synchronous release of registers in sequential logic.
[0117] In some embodiments, the method further comprises:
[0118] Before sending the asynchronous FIFO reset signal, configure the cycle selection signal and perform a first AND logic operation on the second output signal and / or the asynchronous FIFO reset signal. The present application provides multiple methods and time intervals for eliminating burrs, and the configuration of the above-mentioned burr elimination method and the corresponding circuit structure needs to be completed before initiating the asynchronous reset.
[0119] The embodiment of the present application further provides a FIFO circuit, including:
[0120] The register is used to receive the asynchronous FIFO reset signal and the clock signal, and respectively output the delayed FIFO reset signal after delay processing.
[0121] The first multiplexer is connected to each of the registers respectively, and is used for receiving a cycle selection signal, a mask selection signal, and an asynchronous FIFO reset signal or a delayed FIFO reset signal after delay processing, and outputting a first output signal and a second output signal.
[0122] The first AND logic operation component is connected to the first multiplexer and is used for receiving the second output signal and an asynchronous FIFO reset signal and outputting a first AND logic output signal.
[0123] Combination Figure 2 The first AND logic operation component includes a first AND logic gate &1 and a second AND logic gate &2.
[0124] An asynchronous FIFO is connected to the first multiplexer and is used for receiving the first output signal and outputting a transient signal.
[0125] The second multiplexer is connected to the first AND logic operation component, and is used for receiving the first AND logic output signal and a mask selection signal, and outputting a mask signal.
[0126] The second AND logic gate is connected to the asynchronous FIFO and the second multiplexer respectively, and performs an AND logic operation on the transient signal and the shielding signal to obtain a glitch-free output signal of the asynchronous FIFO. Figure 2 , the second AND logic gate is the AND logic gate &3 in the figure.
[0127] The embodiment of the present application also provides a chip, which eliminates reset burrs of asynchronous reset signals by using any of the methods described in the above embodiments.
[0128] An embodiment of the present application also provides an electronic device, comprising the chip as described in the above embodiment.
[0129] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.
[0130] In addition, although each operation is described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or to be performed in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the application. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.
[0131] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.
[0132] Multiple embodiments of the present application are described in detail above, but the present application is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications to the embodiments based on the concept of the present application, and these variations and modifications should all fall within the scope of protection required by the present application.
Claims
1. A method for eliminating burrs generated by asynchronous reset, characterized in that: Applied to an asynchronous FIFO circuit, the method comprises: Based on the reset glitch of the asynchronous FIFO reset signal, the glitch duration that needs to be shielded determines the cycle selection signal; Based on the cycle selection signal, the asynchronous FIFO reset signal is delayed through the register to obtain a delayed FIFO reset signal corresponding to the current cycle selection signal; The first multiplexer selects and outputs the delay FIFO reset signal based on the mask selection signal to obtain a first output signal and a second output signal; Determining a transient signal of the asynchronous FIFO based on the first output signal and a generation mechanism of the asynchronous FIFO output signal; Based on the mask selection signal, determining a method of performing a first AND logic operation on the second output signal and / or the asynchronous FIFO reset signal to obtain a first AND logic output signal; The second multiplexer selects and outputs the first AND logic output signal based on the shielding selection signal to obtain a shielding signal; A second AND logic operation is performed on the shielding signal and the transient signal to obtain a glitch-free output signal of the asynchronous FIFO.
2. The method according to claim 1, characterized in that Based on the cycle selection signal, delay processing is performed on the asynchronous FIFO reset signal through a register, including: Determining the number of required registers based on the cycle selection signal, wherein the number of registers is the same as the value of the cycle selection signal; The asynchronous FIFO reset signal is delayed by determining the number of registers.
3. The method according to claim 2, characterized in that The first multiplexer selects and outputs the delay FIFO reset signal based on the shielding selection signal to obtain a first output signal and a second output signal, including: When the reset glitch of the asynchronous FIFO reset signal is a rising edge reset glitch, determining that the shielding selection signal is a first shielding selection signal; Selecting and outputting the delay FIFO reset signal based on the first shielding selection signal to obtain a third output signal and a fourth output signal, wherein the third output signal is one of the first output signals, and the fourth output signal is one of the second output signals; When the reset glitch of the asynchronous FIFO reset signal is a falling edge reset glitch, determining that the shielding selection signal is a second shielding selection signal; The delay FIFO reset signal is selectively output based on the second mask selection signal to obtain a fifth output signal and a sixth output signal, wherein the fifth output signal is one of the first output signals, and the sixth output signal is one of the second output signals.
4. The method according to claim 3, characterized in that: Based on the mask selection signal, determining a manner of performing a first AND logic operation on the second output signal and / or the asynchronous FIFO reset signal to obtain a first AND logic output signal comprises: Based on the first shielding selection signal, a first operation is performed, the first operation comprising: Performing an AND logic operation on the fourth output signal and the asynchronous FIFO reset signal to obtain a first position shielding signal; Based on the second shielding selection signal, a second operation is performed, the second operation comprising: Determine that the asynchronous FIFO reset signal is a second position masking signal; When the shielding selection signal is a third shielding selection signal, performing a third operation, wherein the third shielding selection signal includes the first shielding selection signal and the second shielding selection signal; The third operation includes performing an AND logic operation on the first position mask signal and the asynchronous FIFO reset signal to obtain a third position mask signal.
5. The method according to claim 4, characterized in that The second multiplexer selects and outputs the first AND logic output signal based on the shielding selection signal to obtain a shielding signal, including: The second multiplexer determines the first position shielding signal as the shielding signal based on the first shielding selection signal; The second multiplexer determines the second position shielding signal as the shielding signal based on the second shielding selection signal; The second multiplexer determines the third position masking signal as the masking signal based on the third masking selection signal.
6. The method according to claim 1, characterized in that Determining a transient signal of the asynchronous FIFO based on the first output signal and a generation mechanism of the asynchronous FIFO output signal includes: Determine a transient signal of the asynchronous FIFO based on the first output signal and a comparison result of the asynchronous FIFO read pointer and the asynchronous FIFO write pointer; The read pointer and the write pointer are pointers that have crossed the read and write clock domains.
7. The method according to claim 1, characterized in that The method further comprises: Before issuing the asynchronous FIFO reset signal, the cycle selection signal and a manner of performing a first AND logic operation on the second output signal and / or the asynchronous FIFO reset signal are configured.
8. A FIFO circuit, characterized in that: include: A register, used for receiving an asynchronous FIFO reset signal and a clock signal, and outputting a delayed FIFO reset signal after delay processing respectively; a first multiplexer connected to each of the registers, respectively, for receiving a cycle selection signal, a mask selection signal, and an asynchronous FIFO reset signal or a delayed FIFO reset signal after delay processing, and outputting a first output signal and a second output signal; A first AND logic operation component, connected to the first multiplexer, configured to receive the second output signal and an asynchronous FIFO reset signal, and output a first AND logic output signal; an asynchronous FIFO connected to the first multiplexer, configured to receive the first output signal and output a transient signal; a second multiplexer connected to the first AND logic operation component, configured to receive the first AND logic output signal and a shielding selection signal, and output a shielding signal; The second AND logic gate is connected to the asynchronous FIFO and the second multiplexer respectively, and performs an AND logic operation on the transient signal and the shielding signal to obtain a glitch-free output signal of the asynchronous FIFO.
9. A chip, characterized in that: The method according to any one of claims 1 to 7 is used to eliminate the reset glitch of the asynchronous reset signal.
10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.