Error detection and compensation for multiplexed transmitters

Abstract

The invention relates to various aspects of error detection and compensation for multiplexed transmitters. For example, a system may include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure a duty cycle error of a clock associated with a transmitter to generate an error detector output based on a clock pattern for an output generated by the transmitter in response to the defined bit pattern. The duty cycle correction circuit is configured to adjust a clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure a quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system may include a quadrature error correction circuit configured to adjust a phase shift between the in-phase clock and the quadrature clock based on a quadrature error.

Description

[0001] Divisional Application Information

[0002] This invention patent application is a divisional application of an invention patent application with an application date of September 19, 2019, application number 201980063691.0, and invention name “Error detection and compensation for multiplexed transmitters”. Technical Field

[0003] The present invention relates generally to electronic circuits and, more particularly, to transmitter circuits. Background Art

[0004] As the demand for higher data rates increases, the operating speed of transmitters continues to increase. In an example, a multiplexer can be used in a transmitter manufactured via a complementary metal oxide semiconductor (CMOS) process. However, conventional high-speed full-rate multiplexers consume power and cause many implementation challenges in high-frequency clock distribution circuits. In addition, conventional half-rate multiplexing architectures are sensitive to clock duty cycle errors. In addition, quarter-rate multiplexers are sensitive to both duty cycle errors and orthogonal errors about the clock. Therefore, conventional multiplexers and / or conventional transmitters that employ multiplexers can be improved. Summary of the invention

[0005] In an example embodiment, a system for reducing errors associated with a multiplexed transmitter includes an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure a duty cycle error of a clock associated with the transmitter to generate an error detector output based on a clock pattern for an output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output.

[0006] In another example embodiment, a system for reducing errors associated with a multiplexed transmitter includes an error detector circuit and a quadrature error correction circuit. The error detector circuit is configured to measure a quadrature error between an in-phase clock and a quadrature clock associated with the transmitter to generate an error detector output based on a clock pattern for an output generated by the transmitter in response to a defined bit pattern. The quadrature error correction circuit is configured to adjust a phase shift between the in-phase clock and the quadrature clock based on the quadrature error.

[0007] In yet another example embodiment, a method includes providing a first defined bit pattern to a transmitter. The method also includes determining first error data associated with a duty cycle distortion of an in-phase clock provided to the transmitter. Additionally, the method includes adjusting the in-phase clock of the transmitter based on the first error data. The method also includes adjusting the quadrature clock of the transmitter based on second error data associated with a duty cycle distortion of the quadrature clock, the second error data being determined in response to a second defined bit pattern provided to the transmitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Example non-limiting embodiments of systems according to various aspects described herein are shown.

[0009] Figure 2 An example non-limiting embodiment of a multiplexing core according to various aspects described herein is shown.

[0010] Figure 3 Example non-limiting embodiments of error detection circuits in accordance with various aspects described herein are shown.

[0011] Figure 4 Example non-limiting embodiments of quadrature error correction circuits in accordance with various aspects described herein are shown.

[0012] Figure 5 Example non-limiting embodiments of duty cycle correction circuits in accordance with various aspects described herein are shown.

[0013] Figure 6 Example non-limiting embodiments of digital logic circuits according to various aspects described herein are shown.

[0014] Figure 7 Another example non-limiting embodiment of a timing diagram in accordance with various aspects described herein is shown.

[0015] Figure 8 A flow chart illustrating an example non-limiting embodiment of a method for error detection and compensation for a multiplexed transmitter is shown.

[0016] Fig. 9A -B shows a flow chart of another example non-limiting embodiment of a method for error detection and compensation for a multiplex transmitter. DETAILED DESCRIPTION

[0017] The disclosure herein is described with reference to the accompanying drawings, wherein throughout the entire text, the same reference numerals are used to refer to the same elements. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of the present invention. However, it is apparent that the different disclosed aspects can be practiced without these specific details. In other examples, well-known structures and devices are shown in block diagram form to facilitate description of the present invention.

[0018] The emergence of high-speed mobile connections, cloud computing, storage applications, etc. has significantly increased the demand for higher data transmission speeds in operator networks and data centers. In order to provide higher data transfer speeds, optical transceivers can adopt PAM-4 and / or forward error correction (FEC) schemes to achieve data rates exceeding 100Gbps on, for example, single-λ communication optical fibers. Alternatively, coherent transceivers can adopt dual polarization and / or higher-order modulation schemes to support data rates of, for example, more than 400Gbps / λ. In both cases, a high-speed transmitter using a multiplexer can be used. A multiplexer is an electronic device that selects a signal from a set of signals (e.g., a set of signals received as input) and outputs the selected signal. In a high-speed multiplexed transmitter, a multiplexer can be used to sequentially select between lower speed input signals to produce a combined output at a higher speed. To achieve this, high-speed clock creation and distribution are required. However, high speed clock generation and / or high speed clock distribution is often difficult to implement with conventional transceivers and / or conventional multiplexers due to increasing errors (eg, increased duty cycle errors and / or increased quadrature errors) as operating speeds increase.

[0019] To address these and / or other problems, one or more embodiments described herein provide error detection and / or error compensation for a multiplexed transmitter, which provides multiple benefits relative to conventional techniques and / or conventional transmitters. For example, a complementary metal oxide semiconductor (CMOS) multiplexed transmitter circuit implementation may be provided, which may increase operating speed and / or reduce errors. On the one hand, a CMOS quarter rate multiplexed transmitter for a high-speed serial link may be provided. In an embodiment, by adopting one or more embodiments described herein, detection and compensation of duty cycle errors and / or quadrature errors may be provided. For example, a duty cycle detector circuit may be employed at the output of a transmitter. During a calibration mode, a defined bit pattern may be applied to the input of a transmitter input by controlling switching logic, and the duty cycle detector output may be fed back to a set of error correction circuits (e.g., a set of duty cycle correction circuits and / or a set of quadrature error correction circuits). For example, errors may be measured at the transmitter output to compensate for any errors in the data path as well as the clock path. In addition, the same detector may be used to correct quadrature errors and duty cycle errors. In some embodiments, a duty cycle correction may be performed on an in-phase clock for a transmitter during a first calibration mode, a duty cycle correction may be performed on a quadrature clock for a transmitter during a second calibration mode, and / or a quadrature error correction may be performed between the in-phase clock and the quadrature clock during a third calibration mode. Thus, the performance of a multiplexed transmitter can be improved. Additionally, errors associated with the multiplexed transmitter can be reduced. For example, a duty cycle error and / or a quadrature error associated with the multiplexed transmitter can be reduced. Furthermore, an increased operating speed of the multiplexed transmitter can be achieved while also reducing errors.

[0020] Now turn to Figure 1, a block diagram of an example, non-limiting embodiment of a system 100 according to various aspects described herein is shown. System 100 may be a transmitter system, such as a multiplexed transmitter system. In an embodiment, system 100 may be a multiplexed transmitter system with quadrature error detection and / or duty cycle detection. System 100 includes a transmitter 102. Transmitter 102 may include a multiplexer core 104 and an output buffer stage 106. Transmitter 102 may receive a set of data signals D0-D3. For example, transmitter 102 may receive data signal DO, data signal D1, data signal D2, and data signal D3. The set of data signals D0-D3 may be, for example, a set of data streams having a defined number of bits. In an embodiment, the set of data signals D0-D3 may be a set of pseudo-random binary sequence data streams. For example, the set of data signals D0-D3 may be a unit data stream of a specific data rate (e.g., 14 GHz for a 56 Gbps transmitter, etc.). However, it should be understood that the set of data signals D0-D3 may be formatted into different types of data streams. The serializer 108 may convert the DIN signal (e.g., Figure 1 DIN) is converted into a set of data signals D0-D3. The DIN signal can be, for example, a low-speed parallel data stream. In one embodiment, the DIN signal can include 64 bits. As such, in a non-limiting example, the serializer 108 can be a 64:4 serializer. However, it should be understood that in some embodiments, the DIN signal can include another number of bits. In addition, it should be understood that in some embodiments, the serializer 108 can be a different type of serializer. In one embodiment, the serializer 108 can sample the DIN signal at a specific sampling rate to generate a set of data signals D0-D3. In an embodiment, the set of data signals D0-D3 provided by the serializer 108 can be a defined bit pattern. For example, the set of data signals D0-D3 provided by the serializer 108 can be a four-bit defined bit pattern such as "1100", "0110", "1010", "1001", "0011", etc. In some embodiments, the value of the set of data signals D0-D3 can depend on the type of calibration mode implemented by the transmitter 102.

[0021] The multiplexer core 104 of the transmitter 102 may convert the set of data signals D0-D3 into a first output data stream DOUTP (eg, Figure 1 DOUTP shown in FIG. 1 ) and a second output data stream DOUTM (eg, Figure 11 . In one aspect, the first output data stream DOUTP may be inverted relative to the second output data stream DOUTM. In another aspect, the first output data stream DOUTP and the second output data stream DOUTM may be differential outputs of the multiplexer core 104. The multiplexer core 104 may be, for example, a complementary metal oxide semiconductor (CMOS) multiplexer. For example, the multiplexer core 104 may be a CMOS quarter rate multiplexer. In a non-limiting example, the multiplexer core 104 may correspond to a 4:1 multiplexer. The output buffer stage 106 of the transmitter 102 may process the first output data stream DOUTP and the second output data stream DOUTM for transmission. For example, the output buffer stage 106 may drive the first output data stream DOUTP and the second output data stream DOUTM. The output buffer stage 106 may be, for example, a differential circuit having a differential input and a differential output. In one aspect, the output buffer stage 106 can increase the power of the first output data stream DOUTP and the second output data stream DOUTM without changing the value of the first output data stream DOUTP and the second output data stream DOUTM. In one example, the first output data stream DOUTP can be a first data stream of 10Gb / s, and the second output data stream DOUTM can be a second data stream of 10Gb / s. Moreover, the first output data stream DOUTP and the second output data stream DOUTM can be different data signals. However, it should be understood that the first output data stream DOUTP and / or the second output data stream DOUTM can be different types of data signals.

[0022] The system 100 also includes an error detector circuit 110 and a digital logic circuit 112. The error detector circuit 110 can monitor the differential output of the transmitter 102. In an embodiment, the error detector circuit 110 can measure a duty cycle error of a clock associated with the transmitter 102 to generate an error detector output (e.g., Figure 1). For example, the error detector circuit may measure a duty cycle error of an in-phase clock (e.g., I_CLK) associated with the transmitter 102 to generate an error detector output based on an in-phase clock pattern of a first output data stream DOUTP and / or a second output data stream DOUTM generated by the transmitter 102 in response to a defined bit pattern associated with the set of data signals D0-D3. Additionally or alternatively, the error detector circuit may measure a duty cycle error of a quadrature clock (e.g., Q_CLK) associated with the transmitter 102 to generate an error detector output based on a quadrature clock pattern of a first output data stream DOUTP and / or a second output data stream DOUTM generated by the transmitter 102 in response to a defined bit pattern associated with the set of data signals D0-D3. In this manner, the error detector circuit 110 may determine an error associated with the first output data stream DOUTP and / or the second output data stream DOUTM.

[0023] In an embodiment, the error detector circuit 110 may be a duty cycle detection circuit that determines a duty cycle error associated with the first output data stream DOUTP and / or the second output data stream DOUTM. In one aspect, the error detector circuit 110 may receive the first output data stream DOUTP and the second output data stream DOUTM. In addition, the error detector circuit 110 may measure the duty cycle error of the first output data stream DOUTP and / or the second output data stream DOUTM. In an embodiment, the error detector circuit 110 may use a comparator to measure the duty cycle error associated with the first output data stream DOUTP and / or the second output data stream DOUTM. For example, the error detector circuit 110 may compare the first output data stream DOUTP and the second output data stream DOUTM. On the other hand, the error detector circuit 110 may generate an error detector output. The error detector output may include the result of the error associated with the first output data stream DOUTP and / or the second output data stream DOUTM. For example, the error detector output may indicate the type of error associated with the first output data stream DOUTP and / or the second output data stream DOUTM. Additionally or alternatively, the error detector circuit 110 may be a quadrature error detection circuit that determines a quadrature error associated with the first output data stream DOUTP and / or the second output data stream DOUTM. For example, the error detector circuit 110 may measure a quadrature error between an in-phase clock and a quadrature clock associated with the first output data stream DOUTP and / or the second output data stream DOUTM in response to a defined bit pattern associated with a set of data signals D0-D3.

[0024] In another aspect, error detector circuit 110 may generate an N-bit pattern (eg, Figure 1). The N-bit pattern may be a collection of bits used to perform quadrature error correction and / or duty cycle correction associated with transmitter 102. For example, quadrature error correction circuit 114, quadrature error correction circuit 115, duty cycle correction circuit 116, and / or duty cycle correction circuit 117 may receive the N-bit pattern. Quadrature error correction circuit 114 may correct for quadrature error correction and / or duty cycle correction associated with in-phase clock I_CLK (e.g., Figure 1 I_CLK shown) and / or a quadrature clock Q_CLK (e.g., Figure 1 The quadrature error correction circuit 115 can also correct the quadrature error associated with the in-phase clock I_CLK and / or the quadrature clock Q_CLK. The duty cycle correction circuit 116 can correct the duty cycle distortion associated with the in-phase clock I_CLK and / or the quadrature clock Q_CLK. Similarly, the duty cycle correction circuit 117 can correct the duty cycle distortion associated with the in-phase clock I_CLK and / or the quadrature clock Q_CLK.

[0025] In an embodiment, the duty cycle correction circuit 116 and / or the duty cycle correction circuit 117 may adjust the in-phase clock I_CLK and / or the quadrature clock Q_CLK associated with the transmitter 102 based on the error detector output and / or the N-bit pattern. For example, the duty cycle correction circuit 116 and / or the duty cycle correction circuit 117 may adjust the in-phase clock I_CLK and / or the quadrature clock Q_CLK associated with the transmitter 102 based on the duty cycle error amount indicated by the error detector output and / or the N-bit pattern. Additionally or alternatively, the quadrature error correction circuit 114 and / or the quadrature error correction circuit 115 may adjust the phase shift between the in-phase clock I_CLK and the quadrature clock Q_CLK based on the error detector output and / or the N-bit pattern. For example, quadrature error correction circuit 114 and / or quadrature error correction circuit 115 may adjust the phase shift between in-phase clock I_CLK and quadrature clock Q_CLK based on the amount of quadrature error indicated by the error detector output and / or the N-bit pattern. As such, based on the N-bit pattern, one or more clocks (e.g., Figure 1). In an embodiment, quadrature error correction circuit 114 may be an in-phase clock quadrature error correction circuit, quadrature error correction circuit 115 may be a quadrature clock quadrature error correction circuit, duty cycle correction circuit 116 may be an in-phase clock duty cycle correction circuit, and duty cycle correction circuit 117 may be a quadrature clock duty cycle correction circuit. In certain embodiments, one or more clocks may be digitally delayed via a clock buffer 118 associated with duty cycle correction circuit 116 and / or a clock buffer 119 associated with duty cycle correction circuit 117 to manage the rise time and / or fall time of one or more clocks provided to multiplexer core 104 of transmitter 102. In an embodiment, one or more clocks may include a set of quarter rate clock signals. For example, one or more clocks may include a first quarter rate clock signal (e.g., CK4_0), a second quarter rate clock signal (e.g., CK4_90), a third quarter rate clock signal (e.g., CK4_180), and a fourth quarter rate clock signal (e.g., CK4_270). In some embodiments, the one or more clocks may control one or more transmission gates of the multiplexer core 104 .

[0026] In some embodiments, a calibration mode may be performed in which different defined bit patterns are provided to the transmitter 102 via the set of data signals D0-D3 to determine an error associated with the transmitter 102. For example, the error detector circuit 110 may measure a duty cycle error of a clock associated with the transmitter 102 to generate a second error detector output based on a second clock pattern of a second output generated by the transmitter 102 in response to an inverted version of the defined bit pattern associated with the set of data signals D0-D3. Additionally, the error detector circuit 110 may determine an average of the first error detector output and the second error detector output. Furthermore, the error detector circuit 110 may adjust a clock associated with the transmitter 102 (e.g., the in-phase clock I_CLK and / or the quadrature clock Q_CLK) based on the average of the first error detector output and the second error detector output.

[0027] In certain embodiments, aspects of the error detector circuit 110 and / or digital logic circuit 112 may constitute one or more machine-executable components embodied in one or more machines, for example, embodied in one or more computer-readable media (or media) associated with one or more machines. When executed by one or more machines (e.g., one or more computers, one or more computing devices, one or more virtual machines, etc.), one or more such components may cause the one or more machines to perform the described operations. For example, the error detector circuit 110 and / or digital logic circuit 112 may include a memory for storing computer-executable components and instructions and / or may communicate with a memory for storing computer-executable components and instructions. In addition, the error detector circuit 110 and / or digital logic circuit 112 may include a processor and / or may communicate with a processor to facilitate the system's operation of instructions (e.g., computer-executable components and instructions).

[0028] See now Figure 2 , a block diagram of an example non-limiting embodiment of a system 200 according to various aspects described herein is shown. System 200 includes a multiplexer core 104. Multiplexer core 104 may include a multiplexer 202. Multiplexer 202 may receive a set of data signals D0-D3. In addition, multiplexer 202 may receive one or more clocks. For example, the set of data signals D0-D3 may include data signal DO, data signal D1, data signal D2, and data signal D3. The set of data signals D0-D3 may be, for example, a set of data streams with a defined number of bits. In one example, the set of data signals D0-D3 may be a set of pseudo-random binary sequence data streams. For example, the set of data signals D0-D3 may be a unit data stream of a specific data rate (e.g., 14 GHz for a 56 Gbps transmitter, etc.). Multiplexer 202 may multiplex the set of data signals D0-D3 into a first output data stream DOUTP. And, the multiplexer 202 may multiplex the set of data signals D0-D3 into the second output data stream DOUTM. In an embodiment, the set of data signals D0-D3 may be a defined bit pattern. For example, the set of data signals D0-D3 may be a four-bit defined bit pattern, such as "1100", "0110", "1010", "1001", "0011", etc. In an embodiment, the value of the set of data signals D0-D3 may depend on the type of calibration mode performed by the transmitter 102.

[0029] See now Figure 3, a block diagram of an example non-limiting embodiment of a system 300 according to various aspects described herein is shown. System 300 includes error detector circuit 110. Error detector circuit 110 may include resistor 302, capacitor 304, resistor 306, capacitor 308, comparator 310 and / or digital accumulator 312. Resistor 302 and capacitor 304 may correspond to a first RC filter. In addition, resistor 306 and capacitor 308 may correspond to a second RC filter. In one aspect, a first output data stream DOUTP may be provided to resistor 302. In addition, resistor 302 may be electrically coupled to capacitor 304 and comparator 310. A second output data stream DOUTM may be provided to resistor 306. In addition, resistor 306 may be electrically coupled to capacitor 308 and comparator 310. Capacitor 304 may also be electrically coupled to capacitor 308 and electrical ground. Comparator 310 can compare a first output data stream DOUTP (e.g., a first output data stream DOUTP processed by a first RC filter associated with resistor 302 and capacitor 304) with a second output data stream DOUTM (e.g., a second output data stream DOUTM processed by a second RC filter associated with resistor 306 and capacitor 308). In one aspect, the first RC filter associated with resistor 302 and capacitor 304 can generate an average value of the first output data stream DOUTP. Additionally, the second RC filter associated with resistor 306 and capacitor 308 can generate an average value of the second output data stream DOUTP. Thus, in certain embodiments, comparator 310 can compare the average value of the first output data stream DOUTP with the average value of the second output data stream DOUTM. Based on the comparison of the first output data stream DOUTP with the second output data stream DOUTM, comparator 310 can generate a comparator output (e.g., Figure 3). For example, the comparator output may include data indicating a comparison of the first output data stream DOUTP with the second output data stream DOUTM. In an example, the comparator 310 may determine whether the differential average between the average of the first output data stream DOUTP and the average of the second output data stream DOUTM is positive or negative. The comparator output may be provided to a digital accumulator 312. The digital accumulator 312 may convert the comparator output to an error detector output. In an embodiment, the error detector output may be an N-bit pattern. For example, the digital accumulator 312 may accumulate the comparator output to obtain an N-bit pattern associated with the error detector output. The N-bit pattern associated with the error detector output may be, for example, an N-bit word. In an embodiment, the digital accumulator 312 may employ a linear search to convert the comparator output to an error detector output (e.g., an N-bit pattern associated with the error detector output). In another embodiment, the digital accumulator 312 may be implemented as a continuous approximation register that employs a binary search to convert the comparator output to an error detector output (e.g., an N-bit pattern associated with the error detector output).

[0030] See now Figure 4 , a block diagram of an example non-limiting embodiment of a system 400 according to various aspects described herein is shown. System 400 includes a quadrature error correction circuit 402. Quadrature error correction circuit 402 may correspond to quadrature error correction circuit 114 and / or quadrature error correction circuit 115. Quadrature error correction circuit 402 may include phase interpolator 404 and phase interpolator 406. Phase interpolator 404 may be an I clock phase interpolator. Phase interpolator 404 may receive an in-phase clock I_CLK and a quadrature clock Q_CLK. In addition, phase interpolator 404 may receive a defined code (e.g., Figure 4 The defined code shown in ). The defined code may be a defined N-bit value. Based on the in-phase clock I_CLK, the quadrature clock Q_CLK and the defined code, the phase interpolator 404 may generate a modified I_CLK (eg, Figure 4 ). The modified I_CLK may be a modified version of the in-phase clock I_CLK. For example, the phase and / or delay of the in-phase clock I_CLK may be modified by the phase interpolator 404 to generate the modified I_CLK. The phase interpolator 406 may be a Q-clock phase interpolator. The phase interpolator 406 may receive the in-phase clock I_CLK and the quadrature clock Q_CLK. In addition, the phase interpolator 406 may receive the N-bit pattern. Based on the in-phase clock I_CLK, the quadrature clock Q_CLK, and the N-bit pattern, the phase interpolator 406 may generate a modified Q_CLK (e.g., Figure 4). The modified I_CLK may be a modified version of the quadrature clock Q_CLK. For example, the phase and / or delay of the quadrature clock Q_CLK may be modified by the phase interpolator 406 to generate the modified Q_CLK. In certain embodiments, the modified I_CLK and / or the modified Q_CLK may be provided to a duty cycle correction circuit (e.g., the duty cycle correction circuit 116 or the duty cycle correction circuit 117). Additionally or alternatively, the modified I_CLK and / or the modified Q_CLK may be provided to the transmitter 102 (e.g., provided to the multiplexer core 104 of the transmitter 102). For example, the modified I_CLK and / or the modified Q_CLK may be included in one or more clocks provided to the transmitter 102 (e.g., provided to the multiplexer core 104 of the transmitter 102).

[0031] See now Figure 5 , a block diagram of an exemplary, non-limiting embodiment of a system 500 according to various aspects described herein is shown. System 500 includes a duty cycle correction circuit 502. In an embodiment, duty cycle correction circuit 502 may correspond to duty cycle correction circuit 116. In another embodiment, duty cycle correction circuit 502 may correspond to duty cycle correction circuit 117. Duty cycle correction circuit 502 may include a current mode logic (CML) buffer 504 and a digital-to-analog converter (DAC) 505. In an embodiment where duty cycle correction circuit 502 corresponds to duty cycle correction circuit 116, CML buffer 504 may receive a modified I_CLK. Alternatively, in an embodiment where duty cycle correction circuit 502 corresponds to duty cycle correction circuit 117, CML buffer 504 may receive a modified Q_CLK. In some embodiments, the modified I_CLK and / or the modified Q_CLK may be processed by the CML buffer 504 to manage the rise time and / or fall time of the modified I_CLK and / or the modified Q_CLK. The DAC 505 may receive the N-bit pattern. The DAC 505 may convert the N-bit pattern from a digital signal to an analog signal. The duty cycle correction circuit 502 may also include an inverter 506 and an inverter 508. In an embodiment where the duty cycle correction circuit 502 corresponds to the duty cycle correction circuit 116, the inverter 506 may employ resistive feedback via the resistor 510 to convert the modified I_CLK (e.g., a current mode logic input clock) into a first CMOS clock CKOUTP (e.g., a current mode logic input clock) for the transmitter 102. Figure 5 In addition, inverter 508 can employ resistive feedback via resistor 512 to convert the modified I_CLK (eg, current mode logic input clock) into a second CMOS clock CKOUTM (eg, Figure 5CKOUTM shown in ). In an alternative embodiment where the duty cycle correction circuit 502 corresponds to the duty cycle correction circuit 117, the inverter 506 can employ resistive feedback via resistor 510 to convert the modified Q_CLK (e.g., the current mode logic input clock) into a first CMOS clock CKOUTP for the transmitter 102. In addition, the inverter 508 can employ resistive feedback via resistor 512 to convert the modified Q_CLK (e.g., the current mode logic input clock) into a second CMOS clock CKOUTM for the transmitter 102. The first CMOS clock CKOUTP and the second CMOS clock CKOUTM can be included in one or more clocks provided to the multiplexer core 104, for example. In some embodiments, the duty cycle correction circuit 502 can also include a capacitor 514 and / or a capacitor 516. The capacitor 514 can be electrically coupled to the CML buffer 504. In addition, the capacitor 514 can be electrically coupled to the inverter 506, the resistor 510, and the resistor 518. The resistor 518 can also be electrically coupled to the DAC 505. Capacitor 516 may be electrically coupled to CML buffer 504. Furthermore, capacitor 516 may be electrically coupled to inverter 508, resistor 512, and resistor 520. Resistor 520 may also be electrically coupled to DAC 505.

[0032] In an embodiment, the duty cycle of the first CMOS clock CKOUTP and / or the second CMOS clock CKOUTM may depend on the value of the N-bit pattern. In one aspect, the N-bit pattern may be a threshold voltage of the duty cycle correction circuit 502. For example, the duty cycle correction circuit 502 may be a CML-CMOS converter, and the N-bit pattern may be a threshold voltage of the CML-CMOS converter. In this way, by digitally adjusting the value of the N-bit pattern, the duty cycle of the first CMOS clock CKOUTP and / or the second CMOS clock CKOUTM may be adjusted. In some embodiments, the duty cycle correction circuit 502 may also include an inverter 522 and / or an inverter 524. The inverter 522 may be configured to perform logical inversion with respect to a data signal (e.g., an inverted version of a modified I_CLK or an inverted version of a modified Q_CLK) received from the inverter 506. For example, the inverter 522 may be configured as a non-logic gate that inverts an inverted version of a modified I_CLK or an inverted version of a modified Q_CLK to provide a first CMOS clock CKOUTP. In addition, the inverter 524 can be configured to perform logic inversion on the data signal (e.g., the inverted version of the modified Q_CLK or the inverted version of the modified Q_CLK) received from the inverter 508. For example, the inverter 524 can be configured as a NOT logic gate that inverts the inverted version of the modified Q_CLK or the inverted version of the modified Q_CLK to provide the second CMOS clock CKOUTM.

[0033] See now Figure 6 , a block diagram of an example non-limiting embodiment of a system 600 according to various aspects described herein is shown. System 600 includes digital logic circuit 112. Digital logic circuit 112 may include switch 602, switch 604, switch 606, and switch 608. Digital logic circuit 112 may receive an error detector output generated by error detector circuit 110. For example, digital logic circuit 112 may receive an N-bit pattern associated with the error detector output generated by error detector circuit 110. Based on the error detector output, digital logic circuit 112 may generate an N-bit pattern provided to quadrature error correction circuit 114, quadrature error correction circuit 115, duty cycle correction circuit 116, and / or duty cycle correction circuit 117. For example, based on the error detector output, digital logic circuit 112 may configure switch 602, switch 604, switch 606, and switch 608 to generate an N-bit pattern provided to quadrature error correction circuit 114, quadrature error correction circuit 115, duty cycle correction circuit 116, and / or duty cycle correction circuit 117. In one aspect, digital logic circuit 112 may open or close switch 602, open or close switch 604, open or close switch 606, and open or close switch 608 based on the error detector output. In another aspect, digital logic circuit 112 may be a demultiplexer that connects an input associated with the error detector output to one of the outputs associated with the N-bit pattern based on an operating mode of quadrature error correction circuit 114, quadrature error correction circuit 115, duty cycle correction circuit 116, and / or duty cycle correction circuit 117. For example, during a first operating mode (e.g., mode=00), an output 610 of the digital logic circuit 112 associated with the error detector output (e.g., an N-bit pattern provided by the error detector output) may be provided to the duty cycle correction circuit 116, during a second operating mode (e.g., mode=01), an output 612 of the digital logic circuit 112 associated with the error detector output (e.g., the N-bit pattern provided by the error detector output) may be provided to the duty cycle correction circuit 117, during a third operating mode (e.g., mode=10), an output 614 of the digital logic circuit 112 associated with the error detector output (e.g., the N-bit pattern provided by the error detector output) may be provided to the orthogonal error correction circuit 114, and during a fourth operating mode (e.g., mode=11), an output 616 of the digital logic circuit 112 associated with the error detector output (e.g., the N-bit pattern provided by the error detector output) may be provided to the orthogonal error correction circuit 115.

[0034] See now Figure 7, illustrates an example non-limiting embodiment of a timing diagram 700 according to various aspects described herein. The timing diagram 700 includes timing data 702 for a clock signal CK4_90. The clock signal CK4_90 may be, for example, a clock signal included in one or more clock signals provided to the multiplexer core 104 of the transmitter 102. The timing diagram 700 also includes timing data 704 for a clock signal CK4_0. The clock signal CK4_0 may be, for example, another clock signal included in one or more clock signals provided to the multiplexer core 104 of the transmitter 102. The timing diagram 700 also includes timing data 706 for an output data stream DOUT. The output data stream DOUT associated with the timing data 706 may be, for example, an output data stream generated by the multiplexer core 104 of the transmitter 102. For example, the output data stream DOUT associated with the timing data 706 may correspond to the output data stream DOUTP and / or the output data stream DOUTM. In an example, the timing data 706 may be represented by a bit pattern of "1010". The timing diagram 700 also includes timing data 708 for the output data stream DOUT. The output data stream DOUT associated with the timing data 708 may be, for example, an output data stream generated by the multiplexer core 104 of the transmitter 102. For example, the output data stream DOUT associated with the timing data 708 may correspond to the output data stream DOUTP and / or the output data stream DOUTM. In an example, the timing data 708 may be represented by a bit pattern of "1100". The timing diagram 700 also includes timing data 710 for the output data stream DOUT. The output data stream DOUT associated with the timing data 710 may be, for example, an output data stream generated by the multiplexer core 104 of the transmitter 102. For example, the output data stream DOUT associated with the timing data 710 may correspond to the output data stream DOUTP and / or the output data stream DOUTM. In an example, the timing data 710 may be represented by a bit pattern of "0110".

[0035] In certain embodiments, aspects of the systems, devices, or processes explained in the present disclosure (e.g., aspects of system 100, system 200, system 300, system 400, system 500, and / or system 600) may constitute one or more machine-executable components embodied in one or more machines, for example, embodied in one or more computer-readable media (or media) associated with one or more machines. When executed by one or more machines (e.g., one or more computers, one or more computing devices, one or more virtual machines, etc.), one or more such components may cause one or more machines to perform the described operations. For example, a system (e.g., system 100, system 200, system 300, system 400, system 500, and / or system 600) may include a memory for storing computer-executable components and instructions. In addition, a system (e.g., system 100, system 200, system 300, system 400, system 500, and / or system 600) may include a processor to facilitate the system's operation of instructions (e.g., computer-executable components and instructions).

[0036] Given the example system above, see Figure 8 Flowchart and Fig. 9A and Fig. 9B Methods that may be implemented according to the described subject matter may be better understood. Although the methods are shown and described as a series of blocks for purposes of simplicity of explanation, it should be understood and appreciated that the claimed subject matter is not limited by the order of the blocks, as some blocks may occur in a different order than that depicted and described herein and / or concurrently with other blocks. Furthermore, not all of the blocks shown are required to implement the methods described below.

[0037] Reference Figure 8 , a flow chart of an exemplary non-limiting embodiment of a method 800 for error detection and compensation for a multiplexed transmitter is shown. The method 800 may begin at block 802, where a first defined bit pattern is provided to a transmitter (e.g., by a serializer 108). For example, the first defined bit pattern may be a "1100" bit pattern. In an embodiment, the first defined bit pattern may be provided to the transmitter during a calibration mode of the transmitter. The transmitter may include, for example, a multiplexer core that receives the first defined bit pattern. In some embodiments, the transmitter may receive the first defined bit pattern via a set of data signals.

[0038] At block 804, first error data associated with a duty cycle distortion of a co-phase clock provided to a transmitter is determined (e.g., by error detector circuit 110 and / or digital logic circuit 112). For example, an output co-phase clock pattern generated by the transmitter in response to a first defined bit pattern may be analyzed to determine the duty cycle distortion of the co-phase clock. In an embodiment, the first error data may include a measure of the duty cycle distortion associated with the output co-phase clock pattern generated by the transmitter. Additionally or alternatively, the first error data may include an N-bit pattern that may be used as feedback to adjust the co-phase clock duty cycle to compensate for the duty cycle distortion.

[0039] At block 806, the in-phase clock for the transmitter is adjusted based on the first error data (e.g., by duty cycle correction circuit 116 and / or duty cycle correction circuit 117). For example, a threshold voltage of a CML-CMOS converter may be adjusted based on the first error data to adjust the duty cycle of the in-phase clock provided to the transmitter.

[0040] At block 808, a second defined bit pattern is provided to the transmitter (e.g., by the serializer 108). For example, the second defined bit pattern may be a "0110" bit pattern. In an embodiment, the second defined bit pattern may be provided to the transmitter during a calibration mode of the transmitter. In some embodiments, the transmitter may receive the second defined bit pattern via a set of data signals.

[0041] At block 810, second error data associated with duty cycle distortion of a quadrature clock provided to a transmitter is determined (e.g., by error detector circuit 110 and / or digital logic circuit 112). For example, an output quadrature clock pattern generated by the transmitter in response to a second defined bit pattern may be analyzed to determine the duty cycle distortion of the quadrature clock. In an embodiment, the second error data may include a measure of the duty cycle distortion associated with the output quadrature clock pattern generated by the transmitter. Additionally or alternatively, the second error data may include an N-bit pattern that may be used as feedback to adjust the quadrature clock duty cycle to compensate for the duty cycle distortion.

[0042] At 812, a quadrature clock for the transmitter is adjusted based on the second error data (e.g., by duty cycle correction circuit 116 and / or duty cycle correction circuit 117). For example, a threshold voltage of a CML-CMOS converter may be adjusted based on the second error data to adjust the duty cycle of the quadrature clock provided to the transmitter.

[0043] At 814, a third defined bit pattern is provided to the transmitter (e.g., by the serializer 108). For example, the third defined bit pattern may be a "1010" bit pattern. In an embodiment, the third defined bit pattern may be provided to the transmitter during a calibration mode of the transmitter. In some embodiments, the transmitter may receive the third defined bit pattern via a set of data signals.

[0044] At 816, third error data associated with a quadrature error between the in-phase clock and the quadrature clock is determined (e.g., by the error detector circuit 110 and / or the digital logic circuit 112). For example, an output in-phase clock pattern generated by the transmitter in response to the third defined bit pattern may be compared to an output quadrature clock pattern generated by the transmitter in response to the third defined bit pattern to determine the quadrature error. In an embodiment, the third error data may include a measurement of a quadrature error associated with the in-phase clock pattern and the quadrature clock pattern. Additionally or alternatively, the third error data may include an N-bit pattern that may be used as feedback to a phase interpolator to compensate for the quadrature error.

[0045] At 818, a phase shift between the in-phase clock and the quadrature clock is adjusted based on the third error data (e.g., by quadrature error correction circuit 114 and / or quadrature error correction circuit 115). For example, a Q clock phase interpolator value of a phase interpolator may be adjusted based on the third error data to compensate for the quadrature error.

[0046] Reference Fig. 9A , a flow chart of an exemplary, non-limiting embodiment of a method 900 for error detection and compensation for a multiplexed transmitter is shown. The method 900 may begin at block 902, where a first defined bit pattern is provided to a transmitter (e.g., by a serializer 108). For example, the first defined bit pattern may be a "1100" bit pattern. In an embodiment, the first defined bit pattern may be provided to the transmitter during a calibration mode of the transmitter. The transmitter may include, for example, a multiplexer core that receives the first defined bit pattern. In some embodiments, the transmitter may receive the first defined bit pattern via a set of data signals.

[0047] At block 904, first error data associated with duty cycle distortion of a co-phase clock provided to the transmitter is determined (e.g., by the error detector circuit 110 and / or the digital logic circuit 112). For example, an output co-phase clock pattern generated by the transmitter in response to a first defined bit pattern may be analyzed to determine the duty cycle distortion of the co-phase clock. In an embodiment, the first error data may include a measure of the duty cycle distortion associated with the output co-phase clock pattern generated by the transmitter. Additionally or alternatively, the first error data may include an N-bit pattern that may be used as feedback to adjust the co-phase clock duty cycle to compensate for the duty cycle distortion.

[0048] At block 906, an inverted version of the first defined bit pattern is provided to the transmitter (e.g., by the serializer 108). For example, the inverted version of the first defined bit pattern may be a "0011" bit pattern. In an embodiment, the inverted version of the first defined bit pattern may be provided to the transmitter during a calibration mode of the transmitter. In some embodiments, the transmitter may receive the inverted version of the first defined bit pattern via a set of data signals.

[0049] At block 908, second error data associated with a duty cycle distortion of a co-phase clock provided to the transmitter is determined (e.g., by the error detector circuit 110 and / or the digital logic circuit 112). For example, an output co-phase clock pattern generated by the transmitter in response to an inverted version of the first defined bit pattern may be analyzed to determine the duty cycle distortion of the co-phase clock. In an embodiment, the first error data may include a measurement of the duty cycle distortion associated with the inverted version of the output co-phase clock pattern generated by the transmitter. Additionally or alternatively, the first error data may include an N-bit pattern that may be used as feedback to adjust the co-phase clock duty cycle to compensate for the duty cycle distortion.

[0050] At 910 , third error data associated with an average of the first error data and the second error data is determined (eg, by the error detector circuit 110 and / or the digital logic circuit 112 ).

[0051] At 912, a duty cycle of the in-phase clock for the transmitter is adjusted based on the third error data (e.g., by duty cycle correction circuit 116 and / or duty cycle correction circuit 117). For example, a threshold voltage of a CML-CMOS converter may be adjusted based on the third error data to adjust the duty cycle of the in-phase clock provided to the transmitter.

[0052] At 914, a second defined bit pattern is provided to the transmitter (e.g., by the serializer 108). For example, the second defined bit pattern may be a "0110" bit pattern. In an embodiment, the second defined bit pattern may be provided to the transmitter during a calibration mode of the transmitter. In some embodiments, the transmitter may receive the second defined bit pattern via a set of data signals.

[0053] At 916, fourth error data associated with duty cycle distortion of a quadrature clock provided to the transmitter is determined (e.g., by error detector circuit 110 and / or digital logic circuit 112). For example, an output quadrature clock pattern generated by the transmitter in response to the second defined bit pattern may be analyzed to determine the duty cycle distortion of the quadrature clock. In an embodiment, the fourth error data may include a measurement of the duty cycle distortion associated with the output quadrature clock pattern generated by the transmitter. Additionally or alternatively, the fourth error data may include an N-bit pattern that may be used as feedback to adjust the quadrature clock duty cycle to compensate for the duty cycle distortion.

[0054] At 918, an inverted version of the second defined bit pattern is provided to the transmitter (e.g., by the serializer 108). For example, the inverted version of the second defined bit pattern may be a "1001" bit pattern. In an embodiment, the inverted version of the second defined bit pattern may be provided to the transmitter during a calibration mode of the transmitter. In some embodiments, the transmitter may receive the inverted version of the second defined bit pattern via a set of data signals.

[0055] See now Fig. 9B , further illustrating a flow chart of an example, non-limiting embodiment of method 900. Method 900 may continue at block 920, where fifth error data associated with duty cycle distortion of a quadrature clock provided to the transmitter is determined (e.g., by error detector circuit 110 and / or digital logic circuit 112). For example, an output quadrature clock pattern generated by the transmitter in response to an inverted version of the second defined bit pattern may be analyzed to determine the duty cycle distortion of the quadrature clock. In an embodiment, the fifth error data may include a measurement of the duty cycle distortion associated with the output quadrature clock pattern generated by the transmitter. Additionally or alternatively, the fifth error data may include an N-bit pattern, which may be used as feedback to adjust the quadrature clock duty cycle to compensate for the duty cycle distortion.

[0056] At 922 , sixth error data associated with an average of the fourth error data and the fifth error data is determined (eg, by the error detector circuit 110 and / or the digital logic circuit 112 ).

[0057] At 924, the duty cycle of the quadrature clock for the transmitter is adjusted based on the sixth error data (e.g., by duty cycle correction circuit 116 and / or duty cycle correction circuit 117). For example, a threshold voltage of a CML-CMOS converter may be adjusted based on the sixth error data to adjust the duty cycle of the quadrature clock provided to the transmitter.

[0058] At 926, a third defined bit pattern is provided to the transmitter (e.g., by the serializer 108). For example, the third defined bit pattern may be a "1010" bit pattern. In an embodiment, the third defined bit pattern may be provided to the transmitter during a calibration mode of the transmitter. In some embodiments, the transmitter may receive the third defined bit pattern via a set of data signals.

[0059] At 928, seventh error data associated with a quadrature error between the in-phase clock and the quadrature clock is determined (e.g., by the error detector circuit 110 and / or the digital logic circuit 112). For example, an output in-phase clock pattern generated by the transmitter in response to the third defined bit pattern may be compared with an output quadrature clock pattern generated by the transmitter in response to the third defined bit pattern to determine the quadrature error. In an embodiment, the seventh error data may include a measure of the quadrature error associated with the in-phase clock pattern and the quadrature clock pattern. Additionally or alternatively, the seventh error data may include an N-bit pattern that may be used as feedback to a phase interpolator to compensate for the quadrature error.

[0060] At 930, an inverted version of the third defined bit pattern is provided to the transmitter (e.g., via the serializer 108). For example, the inverted version of the third defined bit pattern may be a "0101" bit pattern. In an embodiment, the inverted version of the third defined bit pattern may be provided to the transmitter during a calibration mode of the transmitter. In some embodiments, the transmitter may receive the inverted version of the third defined bit pattern via a set of data signals.

[0061] At 932, eighth error data associated with a quadrature error between the in-phase clock and the quadrature clock is determined (e.g., by the error detector circuit 110 and / or the digital logic circuit 112). For example, an output in-phase clock pattern generated by the transmitter in response to an inverted version of the third defined bit pattern may be compared to an output quadrature clock pattern generated by the transmitter in response to an inverted version of the third defined bit pattern to determine the quadrature error. In an embodiment, the eighth error data may include a measurement of the quadrature error associated with the in-phase clock pattern and the quadrature clock pattern. Additionally or alternatively, the eighth error data may include an N-bit pattern that may be used as feedback to a phase interpolator to compensate for the quadrature error.

[0062] At 934 , ninth error data associated with an average of the seventh error data and the eighth error data is determined (eg, by the error detector circuit 110 and / or the digital logic circuit 112 ).

[0063] At 936, the phase shift between the in-phase clock and the quadrature clock is adjusted based on the ninth error data (e.g., by quadrature error correction circuit 114 and / or quadrature error correction circuit 115). For example, a Q clock phase interpolator value of a phase interpolator may be adjusted based on the ninth error data to compensate for the quadrature error.

[0064] Although not required, some aspects of the disclosed subject matter may be implemented in part via an operating system for use by developers of devices or services for an object, and / or included in application software that operates in conjunction with components of the disclosed subject matter. Software may be described in the general context of computer-executable instructions (such as program modules or components) executed by one or more computers (such as a projection display device, viewing device, or other device). Those skilled in the art will appreciate that the disclosed subject matter may be practiced with other computer system configurations and protocols.

[0065] References throughout this specification to "one embodiment," "an embodiment," "an example," "the disclosed aspect," or "an aspect" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment or aspect is included in at least one embodiment or aspect of the present disclosure. Thus, the appearances of the phrases "in one embodiment," "in one aspect," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in the various disclosed embodiments.

[0066] As utilized herein, the terms "component," "system," "engine," "architecture," and the like are intended to refer to a computer or electronic related entity, either hardware, a combination of hardware and software, software (e.g., in execution), or firmware. For example, a component may be one or more transistors, memory cells, an arrangement of transistors or memory cells, a gate array, a programmable gate array, an application specific integrated circuit, a controller, a processor, a process running on a processor, an object accessing or interfacing with a semiconductor memory, an executable, a program or application, a computer, and the like, or a suitable combination thereof. A component may include erasable programming (e.g., processing instructions stored at least in part in an erasable memory) or hard programming (e.g., processing instructions burned into a non-erasable memory at the time of manufacture).

[0067] As an illustration, the processes executed from the memory and the processor can be components. As another example, the architecture may include the arrangement of electronic hardware (e.g., parallel or serial transistors), processing instructions and processors, which implement the processing instructions in a manner suitable for the arrangement of the electronic hardware. In addition, the architecture may include a single component (e.g., a transistor, a gate array, ...) or an arrangement of components (e.g., a series or parallel arrangement of transistors, a gate array connected to a program circuit, a power line, an electrical ground, an input signal line, and an output signal line, etc.). The system may include one or more components and one or more architectures. An example system may include a switch block architecture, which includes crossed input / output lines and transmission gate transistors and power supplies, signal generators, communication buses, controllers, I / O interfaces, address registers, etc. It should be understood that some overlaps in the intended definitions, and the architecture or system may be an independent component, or a component of another architecture, system, etc.

[0068] In addition to the foregoing, the disclosed subject matter can be implemented as a method, device or product that uses typical manufacturing, programming or engineering techniques to produce hardware, firmware, software or any suitable combination thereof to control electronic devices to implement the disclosed subject matter. The terms "device" and "product" used herein are intended to cover electronic devices, semiconductor devices, computers, or computer programs that can be accessed from any computer-readable device, carrier or medium. Computer-readable media may include hardware media or software media. In addition, the medium may include non-transient media or transmission media. In one example, non-transient media may include computer-readable hardware media. Specific examples of computer-readable hardware media may include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, tapes ...), optical disks (e.g., compact disks (CDs), digital versatile disks (DVDs) ...), smart cards and flash memory devices (e.g., cards, sticks, key drives ...). Computer-readable transmission media may include carrier waves, etc. Of course, those skilled in the art will recognize that many modifications may be made to the configuration without departing from the scope or spirit of the disclosed subject matter.

[0069] The foregoing includes examples of the present invention. Of course, for the purpose of describing the subject innovation, it is not possible to describe every conceivable combination of parts or methods, but those of ordinary skill in the art will recognize that many further combinations and arrangements of the subject innovation are possible. Therefore, the disclosed subject matter is intended to cover all such changes, modifications and variations that fall within the spirit and scope of the present disclosure. In addition, to the extent that the terms "comprises," "including," "having," or "having" and variations thereof are used in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term "comprises," as "comprises" is interpreted when used as a transitional word in the claims.

[0070] In addition, the word "exemplary" is used herein to mean used as an example, instance or illustration. Any aspect or design described herein as "exemplary" is not necessarily interpreted as being preferred or advantageous over other aspects or designs. On the contrary, the use of the word exemplary is intended to present concepts in a specific way. As used in this application, the term "or" is intended to represent an inclusive "or", rather than an exclusive "or". That is, unless otherwise specified or clearly seen from the context, "X adopts A or B" is intended to mean any natural inclusive arrangement. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing cases. In addition, the articles "one / a (a)" and "an (an)" as used in this application and the appended claims should generally be interpreted as meaning "one or more / one or more", unless otherwise specified or clearly seen from the context that it is for a singular form.

[0071] In addition, some portions of the detailed description have been presented in terms of algorithms or process operations on data bits within an electronic memory. These process descriptions or representations are the mechanisms employed by those skilled in the art to effectively convey the substance of their work to other equivalently skilled persons. Here, a process is generally conceived to be a self-consistent sequence of actions leading to a desired result. These actions are those requiring physical manipulations of physical quantities. Typically, although not necessarily, these quantities take the form of electrical and / or magnetic signals capable of being stored, transferred, combined, compared, and / or otherwise manipulated.

[0072] It has proven convenient, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless expressly stated otherwise or apparent from the foregoing discussion, it should be understood that throughout the disclosed subject matter, discussions utilizing terms such as process, compute, calculate, determine, or display refer to the actions and processes of processing systems, and / or similar consumer or industrial electronic devices or machines, that manipulate or transform data represented as physical (electrical and / or electronic) quantities within registers or memories of electronic devices, other data similarly represented as physical quantities within machine and / or computer system memories or registers or other such information storage devices, transmission and / or display devices.

[0073] With respect to the various functions performed by the above-described components, architectures, circuits, processes, etc., the terms used to describe such components (including references to "means") are intended to correspond, unless otherwise indicated, to any component (e.g., a functional equivalent) that performs the specified function of the described component, even if not structurally equivalent to the disclosed structure, which performs the functions of the exemplary aspects of these embodiments presented herein. In addition, while a particular feature may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more other features of other embodiments, as may be desired and advantageous for any given or particular application. It will also be recognized that the embodiments include systems having computer-executable instructions for performing the actions and / or events of the various processes, as well as computer-readable media.

Claims

1. A system for reducing errors associated with a multiplex transmitter, comprising: an error detector circuit configured to measure a duty cycle error of a clock associated with a transmitter to generate an error detector output based on a clock pattern of an output generated by the transmitter in response to a defined bit pattern; as well as A duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output.

2. The system according to claim 1, wherein: The error detector circuit is configured to measure the duty cycle error of an in-phase clock associated with the transmitter to generate the error detector output based on an in-phase clock pattern of the output generated by the transmitter in response to the defined bit pattern.

3. The system according to claim 1, wherein: The error detector circuit is configured to measure the duty cycle error of a quadrature clock associated with the transmitter to generate the error detector output based on a quadrature clock pattern of the output generated by the transmitter in response to the defined bit pattern.

4. The system according to claim 1, wherein: The error detector circuit is configured to measure a quadrature error between the in-phase clock and the quadrature clock in response to the defined bit pattern, and Also included is a quadrature error correction circuit configured to adjust a phase shift between the in-phase clock and the quadrature clock based on the quadrature error.

5. The system according to claim 1, wherein: The error detector output is a first error detector output, the clock pattern is a first clock pattern, and the output is a first output, and wherein the error detector circuit is configured to measure a duty cycle error of the clock associated with the transmitter to generate a second error detector output based on a second clock pattern of a second output generated by the transmitter in response to an inverted version of the defined bit pattern.

6. The system according to claim 5, wherein: The error detector circuit is configured to determine an average of the first error detector output and the second error detector output, and the duty cycle correction circuit is configured to adjust the clock based on the average of the first error detector output and the second error detector output.

7. A system for reducing errors associated with a multiplex transmitter, comprising: an error detector circuit configured to measure a quadrature error between an in-phase clock and a quadrature clock associated with a transmitter to generate an error detector output based on a clock pattern of an output generated by the transmitter in response to a defined bit pattern; as well as A quadrature error correction circuit is configured to adjust a phase shift between the in-phase clock and the quadrature clock based on the quadrature error.

8. The system according to claim 7, wherein: The error detector circuit is configured to measure a duty cycle error of the in-phase clock associated with the transmitter to generate the error detector output, and Also included is a duty cycle correction circuit configured to adjust the in-phase clock associated with the transmitter based on the duty cycle error.

9. The system according to claim 7, wherein: The error detector circuit is configured to measure a duty cycle error of the quadrature clock associated with the transmitter to generate the error detector output, and Also included is a duty cycle correction circuit configured to adjust the quadrature clock associated with the transmitter based on the duty cycle error.

10. The system according to claim 7, wherein: The error detector output is a first error detector output, the clock mode is a first clock mode, and the output is a first output, and wherein the error detector circuit is configured to measure a quadrature error between the in-phase clock and the quadrature clock to generate a second error detector output based on a second clock mode of a second output generated by the transmitter in response to an inverted version of the defined bit pattern.

Images