Data processing method and electronic device

Abstract

The present disclosure provides a data processing method and an electronic device. The method is applied to a first device, the first device comprising a first memory and a first cache, the first memory being configured to store a first routing table. The method comprises: receiving a first routing table entry from a second device through a first channel; the first channel being a channel based on a high-speed interconnection protocol between the first device and the second device; updating the first routing table according to the first routing table entry; and sending a to-be-forwarded packet by using the updated first routing table.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and particularly relates to a data processing method and an electronic device. BACKGROUND

[0002] With the vigorous development of the computing field, data processing units (DPU) are emerging as a key element to redefine the future of data centers and computing architectures. Field-programmable gate arrays (FPGA) are one of the core technologies to implement DPU, which has the ability to reconfigure at the hardware level, making it suitable for a variety of computing tasks. DPU can take advantage of the flexibility of FPGA to achieve efficient data processing by reconfiguring hardware.

[0003] In the related art, when the routing table is updated due to changes in the networking topology, the FPGA in the DPU generally adopts an I2C (Inter-Integrated Circuit) bus synchronization method or a routing table synchronization method based on special messages. The routing table item data transfer delay is high, and the routing table cannot change as soon as possible, which can easily lead to problems such as packet loss and incorrect routing of messages. SUMMARY

[0004] According to a first aspect of the present disclosure, a data processing method is provided, the method is applied to a first device, the first device includes: a first memory and a first cache, the first memory is used to store a first routing table; the method includes:

[0005] receiving a first routing table item from a second device through a first channel; the first channel is a channel based on a high-speed interconnection protocol between the first device and the second device;

[0006] updating the first routing table according to the first routing table item, and sending a to-be-forwarded message by using the updated first routing table.

[0007] According to a second aspect of the present disclosure, a data processing apparatus is provided, the apparatus is applied to a first device, the first device includes: a first memory and a first cache, the first memory is used to store a first routing table; the apparatus includes:

[0008] a first transmission module, configured to receive a first routing table item from a second device through a first channel; the first channel is a channel based on a high-speed interconnection protocol between the first device and the second device;

[0009] a first processing module, configured to update the first routing table according to the first routing table item;

[0010] The first transmission module is further configured to send the to-be-forwarded packet by using the updated first routing table.

[0011] According to a third aspect of the present disclosure, a data processing method is provided, the method is applied to a second device, and the method comprises:

[0012] determining a first routing table entry;

[0013] sending the first routing table entry to a first device through a first channel; the first channel is a high-speed interconnection protocol-based channel between the first device and the second device.

[0014] According to a fourth aspect of the present disclosure, a data processing apparatus is provided, the apparatus is applied to a second device, and the apparatus comprises:

[0015] a determining module configured to determine a first routing table entry;

[0016] a second transmission module configured to send the first routing table entry to a first device through a first channel; the first channel is a high-speed interconnection protocol-based channel between the first device and the second device.

[0017] According to a fifth aspect of the present disclosure, an electronic device is provided, comprising:

[0018] at least one processor; and

[0019] a memory connected to the at least one processor in communication; wherein,

[0020] the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of the present disclosure.

[0021] According to a sixth aspect of the present disclosure, a non-transitory computer readable storage medium storing computer instructions is provided, the computer instructions are used to enable the computer to perform the method of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0022] The above and other objects, features and advantages of the present disclosure exemplary embodiments will be readily understood through reading the detailed description below, with reference to the accompanying drawings. In the drawings, several embodiments of the present disclosure are shown in an exemplary, but not limiting, manner, wherein:

[0023] In the drawings, the same or corresponding reference numbers indicate the same or corresponding parts.

[0024] Figure 1 a schematic diagram of a DPU based on FPGA;

[0025] Figure 2 A flowchart of a data processing method provided by an embodiment of the present disclosure is shown in FIG. 1.

[0026] Figure 3 A flowchart of another data processing method provided by an embodiment of the present disclosure is shown in FIG. 2.

[0027] Figure 4 A schematic diagram of data transmission based on a CXL shared cache mode provided by an embodiment of the present disclosure is shown in FIG. 3.

[0028] Figure 5 A schematic diagram of route table updating based on a CXL shared cache mode provided by an embodiment of the present disclosure is shown in FIG. 4.

[0029] Figure 6 A schematic diagram of route table updating based on a CXL shared memory mode provided by an embodiment of the present disclosure is shown in FIG. 5.

[0030] Figure 7 A schematic diagram of packet forwarding based on a CXL shared cache mode provided by an embodiment of the present disclosure is shown in FIG. 6.

[0031] Figure 8 A schematic diagram of a Virtio module queue provided by an embodiment of the present disclosure is shown in FIG. 7.

[0032] Figure 9 A structural schematic diagram of a data processing apparatus provided by an embodiment of the present disclosure is shown in FIG. 8.

[0033] Figure 10 A structural schematic diagram of another data processing apparatus provided by an embodiment of the present disclosure is shown in FIG. 9.

[0034] Figure 11 A structural schematic diagram of an electronic device provided by an embodiment of the present disclosure is shown in FIG. 10. DETAILED DESCRIPTION

[0035] In order to make the objectives, features and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0036] Before the embodiments of the present disclosure are further described in detail, the related technologies involved in the embodiments of the present disclosure are described.

[0037] Figure 1 A schematic diagram of a DPU based on FPGA is shown in FIG. 11. Figure 1As shown, the FPGA-based DPU can be divided into two channels, uplink and downlink. The uplink message passes through the Ethernet (ETH) network interface, and after being unpacked by the Receive Multiplexer (RMUX) port selection Parser (PA), the message information is processed by the Packet Processing Engine (PPE) for table lookup, and the message is stored through the Data Path. For the downlink message sent by the host, the operation is reversed. In addition, Figure 1 TXQ in the figure can represent Transmit Queue, Adp can represent Adapter, MUX can represent Multiplexer, DMUX can represent Down multiplexer, QM can represent Queue Management, and MODIFY can represent message modification module. The Host is connected to a double data rate synchronous dynamic random access memory (DDR) for storing data.

[0038] FPGA requires various lookup tables to implement network message routing, editing and processing, so the FPGA board card needs a large amount of fast storage to save various table data. With the continuous increase of network bandwidth and network topology, the storage routing table items are getting larger, and the storage resources (such as BRAM) of the FPGA cannot meet the storage requirements of various table items. Therefore, a DDX memory is externally connected to the FPGA to store the routing table, for example Figure 1 As shown in the FPGA, there is a DDR storing a routing table.

[0039] When the network changes, such as network topology changes, new hosts are added to the existing network or existing hosts are withdrawn, causing the network to change, the routing table items need to be relearned and synchronized. The general processing is to send the first packet of the new host message to the coprocessor for processing, where the coprocessor can be an Extend Central Processing Unit (ECPU). Then the routing table items are flushed to the DDX memory through the FPGA.

[0040] The learning and synchronization of the above routing table entries can adopt an I2C bus synchronization manner. Specifically, the FPGA and various processors (including ECPU and Host) communicate with each other through an I2C bus. The FPGA sends a first packet of a new host message to the ECPU, the ECPU learns the changed routing table entries and then sends them to the FPGA, and the FPGA writes the changed routing table entries into the DDR memory. Since the I2C bus is a low-speed bus (usually KB speed), and the I2C bus is connected to multiple configuration modules inside the FPGA, the I2C bus is very slow in updating the routing table entries, which causes a large number of network packet losses during the updating of the routing table entries, and seriously affects the performance of the application.

[0041] The learning and synchronization of the routing table entries can also adopt a special message-based routing table synchronization manner. The changed routing table entries are packaged into special messages, the messages are parsed by a message parsing module of the FPGA, the payload (updated routing table entries) is stripped, and the updated routing table entries are written into the DDRx memory via the FPGA. Compared with the I2C bus synchronization routing table manner, the special message manner can quickly synchronize the messages to the routing table in the DDRx memory through a high-speed message processing channel (which can reach GB speed). However, the packaging and parsing of the routing messages increase the delay of the routing synchronization, and especially for delay-sensitive fields (such as real-time surgery, financial quantification, real-time high-definition video, etc.), the current application requirements cannot be met.

[0042] In summary, the I2C bus synchronization manner or the special message-based routing table synchronization manner has a high delay in the transmission of routing table entry data, and the routing table cannot be changed quickly, which easily causes problems such as packet loss and incorrect routing of messages.

[0043] Figure 2 A flowchart of a data processing method provided by an embodiment of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the method is applied to a first device, which includes a first memory and a first cache. The first memory is used to store a first routing table. The method includes the following steps. Figure 2

[0044] Step 201: receiving first routing table entries from a second device through a first channel. The first channel is a high-speed interconnection protocol-based channel between the first device and the second device.

[0045] Step 202: updating the first routing table according to the first routing table entries, and sending a to-be-forwarded message by using the updated first routing table.

[0046] In some embodiments, the first channel is a first-type first channel or a second-type first channel.

[0047] ​The first type of first channel is a high-speed interconnection protocol-based channel between the first cache and the cache of the second device.

[0048] The second type of first channel is a high-speed interconnection protocol-based channel between the first memory and the second device.

[0049] Here, the first device can be an FPGA of a DPU, and the second device can be a coprocessor such as an ECPU of the DPU. The first cache can be a cache, and the first memory can be a DDR.

[0050] Using the first channel (the first type of first channel or the second type of first channel) based on the high-speed interconnection protocol to transmit the routing table item from the ECPU to the FPGA can reduce the data transmission delay and improve the data transmission rate, so that the FPGA can receive the routing table item in real time, and problems such as packet loss and incorrect routing of messages can be reduced.

[0051] In some embodiments, the method further includes:

[0052] determining device information of the first device and / or a size of the first memory; the device information is used to indicate a version of a high-speed interconnection protocol supported by the first device;

[0053] generating a channel establishment request according to the device information and / or the size of the first memory; the channel establishment request is used to request to establish the first type of first channel or the second type of first channel;

[0054] sending the channel establishment request to the second device.

[0055] Here, the version of the high-speed interconnection protocol (CXL, Compute Express Link) includes: CXL type1 (first type of CXL), CXL type2 (second type of CXL), and CXL type3 (second type of CXL).

[0056] If the device information indicates that the first device supports CXL type1 based on device support, the first type of first channel can be selected to be established;

[0057] If the device information indicates that the first device supports CXL type3 based on device support, the second type of first channel can be selected to be established;

[0058] If the device information indicates that the first device supports CXL type2 based device, the first memory size can be further determined, and it is determined whether the first memory size exceeds a preset memory threshold. If the memory threshold is exceeded, a second type of first channel is selected to be established, and if the memory threshold is not exceeded, a first type of first channel is selected to be established. The memory threshold can be set based on actual needs, such as 8G, 16G, etc.

[0059] Here, according to the device information and / or the first memory size, it is determined which type of first channel is selected, and a corresponding channel establishment request is generated and sent to the second device to establish a corresponding first channel.

[0060] In this way, the appropriate channel type is selected according to the device information and the memory size, the delay in the data transmission process is reduced, and the speed and efficiency of data exchange are improved.

[0061] In some embodiments, the generation of the channel establishment request comprises one of the following:

[0062] The starting address, total length and access granularity of the first routing table in the first memory are determined, and the channel establishment request is generated according to the starting address, total length and access granularity;

[0063] The address information of the first cache is determined, and the channel establishment request is generated according to the address information.

[0064] Here, if the first type of first channel needs to be generated, the address information of the first cache is determined, and the channel establishment request is generated according to the address information. So that the second device establishes a high-speed interconnection protocol based channel between the first cache and the cache of the second device according to the channel establishment request.

[0065] Here, if the second type of first channel needs to be generated, the starting address, total length and access granularity of the first routing table in the first memory are determined, and the channel establishment request is generated according to the starting address, total length and access granularity. So that the second device establishes a high-speed interconnection protocol based channel between the first memory and the second device. The starting address can be the starting address of the first routing table in the first memory, which is used to indicate the reference point of accessing the first routing table of the first memory. The access granularity is used to indicate the minimum unit of memory access, which can determine the memory size involved in each routing table entry update or access. The total length is used to indicate the total length of the first routing table, which is usually in bytes.

[0066] Of course, according to the application scenario and demand, the information of the generated channel establishment request can also include other contents, which are not limited here.

[0067] In some embodiments, if the first channel is a first type of first channel, updating the first routing table according to the first routing table entry includes:

[0068] obtaining a first routing table entry from the first cache;

[0069] writing the first routing table entry into the first routing table of the first memory.

[0070] Here, the first routing table is used to store paths pointing to specific network addresses, and can also record the routing metric values of the paths, and contains the topology information of the network periphery, and is mainly used to implement routing protocols and static routing selection.

[0071] The routing table entry in the first routing table is a single entry, which can describe the forwarding information required for a specific network target (such as an IP address or a subnet).

[0072] The first routing table entry refers to a newly learned or obtained routing table entry, which is written into the first routing table so that it can be queried and used for subsequent packet forwarding.

[0073] Here, considering that the first routing table is saved into the first memory, and the first routing table entry is received by the first cache, after the first cache receives the first routing table entry, the first routing table entry needs to be written into the first routing table of the first memory, so that the complete routing table entry can be obtained immediately when the first routing table is subsequently queried.

[0074] Specifically, after obtaining the first routing table entry from the first cache, the first routing table entry can be first issued to a buffer (such as a memory resource block (BRAM) composed of a static random-access memory (SRAM)) inside the first device. Here, the purpose of the device buffer is to serve as an intermediate buffer when the operation timing of the first cache and the first memory does not match, to quickly obtain data from the first cache, and to avoid data in the first cache being replaced into the memory of the host connected to the first device. The updated routing table entry in the buffer is synchronously written into the first routing table of the first memory, and the routing table entry that has been updated in the buffer is synchronously removed. If the first device receives a packet at this time, it does not hit any routing table entry in the first routing table, at this time, the routing table entry in the small buffer can also be preferentially searched, if it is hit, the packet is processed according to the hit routing table entry, reducing a large number of packet drops due to the update of the routing table entry not being timely. Through the above-mentioned manner, the loss of packets, especially important packet data, can be reduced.

[0075] In some embodiments, the method further includes one of:

[0076] receive the to-be-forwarded packet from other devices.

[0077] receive the to-be-forwarded packet from other devices.

[0078] Specifically, the first device can be a FPGA, which is used as an accelerator in a DPU for packet forwarding; and the second device can be an ECPU of the DPU, which can be used for route learning and / or obtaining new routing table entries.

[0079] The first device and the second device belong to the same electronic device, which can further include a host, which can be a processor, and the first device is connected to the processor.

[0080] In an example, if the electronic device needs to send a packet, the processor sends the to-be-forwarded packet to the first device for forwarding based on the first routing table. Here, a second channel is provided, specifically a channel based on a high-speed interconnection protocol between the first cache of the first device and the last level cache of the processor, through which the to-be-forwarded packet is sent, so that the first device can quickly and instantly obtain the to-be-forwarded packet.

[0081] In another example, the first device can also receive the to-be-forwarded packet sent by other devices as a receiving end or a transfer party, and send the to-be-forwarded packet.

[0082] Correspondingly, the method can further include:

[0083] The first device determines address information of the first cache, and generates a channel establishment request according to the address information.

[0084] The first device sends the channel establishment request to the processor, and the channel establishment request is used to request the processor to establish the second channel.

[0085] In this way, after the processor receives the channel establishment request, the second channel can be established based on the channel establishment request. Thus, the first device and the processor can realize fast packet transmission through the second channel.

[0086] In some embodiments, sending the to-be-forwarded packet by using the updated first routing table includes:

[0087] If it is determined according to the first routing table that the destination address of the to-be-forwarded packet is the device to which the first device belongs, the to-be-forwarded packet is sent to a processor of the device through a second channel; the second channel is a channel based on a high-speed interconnection protocol between the first cache of the first device and a last-level cache of the processor.

[0088] Here, if the first device can receive a to-be-forwarded packet sent by another device and the destination address of the to-be-forwarded packet is the device to which the first device belongs, the first device can send the to-be-forwarded packet to a processor of the device through a second channel, so that the processor can quickly and immediately obtain the to-be-forwarded packet.

[0089] In some embodiments, the method further includes one of the following:

[0090] The first cache is polled to determine whether the first routing table entry is received by the first cache;

[0091] The flag bit state of the first memory is periodically detected, and it is determined according to the flag bit state whether the first routing table entry is received by the first memory.

[0092] Here, a query mechanism is provided, so that the first device can quickly discover that a new routing table entry, i.e., the first routing table entry, is obtained in the first cache or the first memory of the first device.

[0093] If the first type of first channel is used, the first device can poll the first cache to determine whether the first routing table entry is received by the first cache, so that it is immediately discovered whether there is a change in the first cache.

[0094] If the first type of second channel is used, the first device can periodically detect the flag bit state of the first memory, and determine according to the flag bit state whether the first routing table entry is received by the first memory, so that it is immediately discovered whether there is a change in the first memory. The flag bit state can be identified in any form to distinguish whether there is a change or not, which is not limited here.

[0095] Of course, in addition to the above-mentioned manners, other manners can also be used, such as an interrupt manner, i.e., a kind of interrupt is set, if the first memory receives the first routing table entry, an interrupt signal is generated to the processing unit of the first device, so as to inform the first device that the new first routing table entry has been obtained.

[0096] Figure 3 A flowchart of a data processing method provided by an embodiment of the present disclosure is shown in FIG. Figure 3 As shown in FIG.

[0097] Step 301, determining a first routing table entry;

[0098] Step 302: Send the first routing table entry to the first device through the first channel; the first channel is a channel between the first device and the second device based on a high-speed interconnection protocol.

[0099] In some embodiments, determining the first routing table entry includes at least one of the following:

[0100] Receive a new message from the first device; perform route learning based on the new message to obtain a first routing table entry;

[0101] Receive at least one first routing table entry from another second device.

[0102] In one example, when network topology changes, a new host joins the existing network, or an existing host leaves, causing network changes, the overall network structure changes, requiring relearning and synchronizing routing table entries. If the first device receives a packet from a newly joined host and fails to query the first routing table, it can send the new packet to the second device, which will then perform route learning to obtain the first routing table entry. The route learning can employ any route learning rule or mechanism; the method used by the second device to determine the first routing table entry is not limited here.

[0103] In another example, suppose the second device belongs to a cluster, and other devices in the cluster have determined a new routing entry that can be forwarded to each other. For example, the cluster includes servers A, B, C, and D. If server A determines a new routing entry, and the second devices of each server can communicate synchronously, it can send the entry to the second devices of other servers, who in turn forward it to the first device. Here, the new routing entry is the first routing entry, and there can be one or more first routing entries.

[0104] Thus, by using a first channel (first type first channel or second type first channel) based on a high-speed interconnection protocol, latency is reduced, data transmission reliability is enhanced, and data transmission rate is increased, thereby enabling the first device to receive the first routing table entry in real time.

[0105] In some embodiments, the first channel is a first type of first channel or a second type of first channel;

[0106] The first channel of the first type is a channel based on a high-speed interconnect protocol between the first cache and the cache of the second device;

[0107] The second type of first channel is a channel between the first memory and the second device based on a high-speed interconnect protocol.

[0108] Here, the first channel (the first type of first channel or the second type of first channel) based on the high-speed interconnection protocol is adopted to reduce the delay, enhance the reliability of data transmission, and improve the data transmission rate, so that the first device can receive the first routing table item in time.

[0109] In some embodiments, the method further comprises:

[0110] receiving a channel establishment request; the channel establishment request is used to request to establish the first type of first channel or the second type of first channel;

[0111] establishing the corresponding first type of first channel or the second type of first channel according to the channel establishment request.

[0112] Here, the second device can complete the establishment of the corresponding first channel based on the channel establishment request and the information carried thereby.

[0113] For example, the information can include the start address, the total length, and the access granularity of the first routing table in the first memory; or the information can include the address information of the first cache.

[0114] The first type of first channel and the second type of first channel have been described in the Figure 2 The method is not described here.

[0115] Figure 4 A schematic diagram of a CXL-based shared cache mode for data transmission provided by an embodiment of the present disclosure; Figure 4 In the figure, CORE represents each processor core, a multi-core processor can have multiple processor cores, L1 and L2 represent the first level cache and the second level cache respectively, LLC represents the last level cache, and DDR represents the memory. In the FPGA, cache represents the first cache of the FPGA, and AFU represents the accelerator functional unit (Accelerator Functional Unit).

[0116] For the storage hierarchy, the closer the storage (such as registers and caches at different levels) to the processor, the lower the data delay, for example, the last level cache (LLC) data processing delay is lower than the memory data processing delay. Therefore, based on the discovery that the shared cache (especially LLC) has relatively lower data processing delay, higher performance, and lower power consumption than the shared memory, a CXL-based shared cache mode is proposed.

[0117] Figure 5 A schematic diagram of routing table updating in a CXL-based shared cache mode provided by an embodiment of the present disclosure; as Figure 5As shown, a shared cache mechanism between FPGA and ECPU is provided to replace the original I2C shared memory mechanism to realize low-delay routing table synchronization. Physical data update is actually transmitted to the Cache of FPGA through the Cache channel based on CXL protocol (equivalent to the first type of first channel).

[0118] Specifically, after the ECPU learns the routing table, the FPGA quickly acquires the routing table from the ECPU based on CXL Cache; then, the routing table is issued to the buffer in the FPGA; and the updated routing table in the buffer is written into the routing table in the DDR (Table0, Table1…TableN represent the routing table) and the buffer is synchronized to remove the updated table. Figure 5 If the FPGA hardware receives a packet at this time, it does not hit the hardware routing table, at this time, the buffer can be searched preferentially, if it hits, the packet is processed according to the routing table, and a large number of packet loss caused by the delay of updating the routing table is reduced. In this way, the loss of packets can be reduced.

[0119] The following provides a routing table updating method based on CXL shared cache mode, comprising:

[0120] 1. After the FPGA receives a new host packet, the FPGA hardware analyzes the packet and obtains packet information;

[0121] 2. The FPGA queries the routing table to determine that there is no matching routing table item, i.e., the FPGA fails to search the table, and the packet is sent to the ECPU for processing;

[0122] Here, the packet can also be sent to the ECPU based on CXL Cache.

[0123] 3. The ECPU analyzes the packet and learns the routing to obtain a new routing table item;

[0124] 4. The ECPU writes the new routing table item into the local soft routing table (TableX) and forwards the packet to the FPGA;

[0125] Here, the packet can also be sent to the FPGA based on CXL Cache.

[0126] 5. The FPGA reads the new routing table item from the local CXL Cache based on the CXL shared cache mode, writes it into the Buffer, synchronizes the data of the routing table item in the Buffer to the DDR, and deletes the synchronized routing table item in the Buffer.

[0127] Figure 6A schematic diagram of a CXL shared memory based routing table update provided by an embodiment of the present disclosure is shown in FIG. 1. As shown in FIG. 1, a CXL type 3 protocol is used inside the FPGA to map the FPGA's DDR to the ECPU, and the ECPU can directly access the FPGA's DDR through CXL. Specifically, the routing table in the FPGA's DDR is mapped to the address space of the ECPU, and the ECPU can update the FPGA-side routing table entries as if it were updating local memory. When the ECPU learns new routing table entries through routing learning, it updates the local routing table entries, synchronously issues the routing table entries to the FPGA's memory, and implements the update of the routing table. The physical data update is actually performed through the first channel (equivalent to the second type first channel) based on the CXL protocol, and the updated routing table entries are directly written into the routing table of the FPGA memory. Figure 6

[0128] A CXL shared memory based routing table update method is provided below, which includes the following steps:

[0129] 1. After receiving a new host message, the FPGA hardware parses the message and obtains the message information.

[0130] 2. The FPGA queries the routing table to determine whether there is a matching routing table entry, i.e., the FPGA fails to find the table, and the message is sent to the ECPU for processing.

[0131] 3. The ECPU parses the message and learns the routing to obtain new routing table entries.

[0132] 4. The ECPU writes the new routing table entries into the local soft routing table (Table X) and forwards the message to the FPGA.

[0133] 5. The ECPU issues the new routing table entries to the FPGA. Here, since the routing table in the FPGA's DDR has been mapped to the ECPU, the ECPU can directly update the routing table entries; equivalently, the ECPU automatically synchronizes the new routing table entries to the routing table on the FPGA side through the CXL protocol.

[0134] Figure 7 A schematic diagram of a CXL cache sharing based message forwarding provided by an embodiment of the present disclosure is shown in FIG. 2. As shown in FIG. 2, message sending is divided into uplink and downlink directions. Figure 7

[0135] ​​Upstream: FPGA receives the packet through MAC (media access control layer), and the packet is forwarded through OVS (open virtual switch) hardware lookup. For the packet with the target address of the local machine, the processed packet is written into the Virtio module queue, supporting the RSS (load balancing hash) mode of the packet to write multiple queues for concurrent processing. The current Virtio module queue number is generally an integer multiple of the processor core. The processed packet is written into the CXL Cache of FPGA, and is automatically synchronized to the LLC of the processor based on the Cache consistency protocol. The corresponding bound processor core reads the packet data from the shared LLC quickly.

[0136] In this way, the packet is obtained based on the CXL shared cache, the data delay is low, and the efficiency is high. If the cache of the processor is full or replaced, the shared memory mode can be used subsequently.

[0137] Downstream: The processed packet of the processor is preferentially buffered in the LLC, and the FPGA obtains the packet sent by the processor based on the CXL shared cache. In this way, the FPGA can quickly obtain the packet.

[0138] Here, the packet obtained by the FPGA from the CXL Cache can be written into the Virtio module queue, and the OVS reads the packet in the queue for forwarding processing.

[0139] It should be noted that the above Figures 5-7 CXL EP Gen5x16 represents an example of an interconnection technology, wherein CXL represents a protocol adopted, EP refers to an end port (End Port) for connecting the FPGA, Gen5 refers to the fifth generation of CXL standard, and x16 represents that the connection can have 16 channels. CXL cache represents a shared cache based on CXL.

[0140] ECPU in the DPDK (Data Plane Development Kit) represents an accelerated packet processing unit, and OVS (Open vSwitch) represents a multi-layer virtual switch.

[0141] Regarding the Virtio module queue, an example is provided, as shown in Figure 8 To adapt to the replacement of data to DDR due to the reduction of cache data reorganization, a queue form suitable for Q0, Q1…QN is designed. The bit width of each entry is a complete cache line (Cache line) size, and the data bit width is matched with the cache, so that the data reorganization and splitting in the CXL Cache are avoided, and the data processing delay is reduced.

[0142] The device mapping method provided by the embodiments of the present disclosure includes: downloading an engineering containing a CXL protocol to an FPGA board card and powering on; after the FPGA is powered on, the FPGA can negotiate the capability and protocol type of the CXL with a processor supporting the CXL through a CXL.IO protocol. The FPGA can also allocate the start address, granularity and length of a routing table in a memory. After the processor negotiates with the FPGA, the processor can discover and enumerate the FPGA and can also obtain the address space of the FPGA. The routing table in the FPGA memory can also be mapped to an ECPU, and the ECPU can update the routing table entries in the FPGA memory as if it directly manipulates the local memory.

[0143] Figure 9 A structural schematic diagram of a data processing apparatus provided by the embodiments of the present disclosure is shown in FIG. 1. As shown in FIG. 1, the apparatus is applied to a first device, and the first device includes a first memory and a first cache, and the first memory is used to store a first routing table. The apparatus includes: Figure 9

[0144] a first transmission module, configured to receive a first routing table entry from a second device through a first channel; the first channel is a channel based on a high-speed interconnection protocol between the first device and the second device;

[0145] a first processing module, configured to update the first routing table according to the first routing table entry;

[0146] The first transmission module is further configured to send a to-be-forwarded packet by using the updated first routing table.

[0147] In some embodiments, the first channel is a first channel of a first type or a first channel of a second type.

[0148] The first channel of the first type is a channel based on the high-speed interconnection protocol between the first cache and a cache of the second device.

[0149] The first channel of the second type is a channel based on the high-speed interconnection protocol between the first memory and the second device.

[0150] In some embodiments, the first processing module is further configured to determine device information of the first device and / or a first memory size; the device information is used to indicate a high-speed interconnection protocol version supported by the first device.

[0151] According to the device information and / or the first memory size, a channel establishment request is generated; the channel establishment request is used to request to establish the first channel of the first type or the first channel of the second type.

[0152] The first transmission module is further configured to send the channel establishment request to the second device.

[0153] ​In some embodiments, the first processing module is configured to perform one of the following:

[0154] determining a start address, a total length and an access granularity of the first routing table in the first memory, and generating a channel establishment request according to the start address, the total length and the access granularity;

[0155] determining address information of the first cache, and generating a channel establishment request according to the address information.

[0156] In some embodiments, if the first channel is a first-type first channel, the first processing module is configured to acquire a first routing table item from the first cache;

[0157] write the first routing table item into the first routing table in the first memory.

[0158] In some embodiments, the first transmission module is further configured to perform one of the following:

[0159] receive the to-be-forwarded packet through a second channel; the second channel is a channel based on a high-speed interconnection protocol between a first cache of the first device and a last-level cache of a processor, and the first device and the processor belong to the same device;

[0160] receive the to-be-forwarded packet from other devices.

[0161] In some embodiments, the first transmission module is configured to, if it is determined according to the first routing table that a destination address of the to-be-forwarded packet is the device to which the first device belongs, send the to-be-forwarded packet to the processor of the device through a second channel; the second channel is a channel based on a high-speed interconnection protocol between a first cache of the first device and a last-level cache of the processor.

[0162] In some embodiments, the first processing module is further configured to perform one of the following:

[0163] poll the first cache to determine whether the first routing table item is received by the first cache;

[0164] periodically detect a flag bit state of the first memory to determine whether the first routing table item is received by the first memory according to the flag bit state.

[0165] It can be understood that the data processing apparatus provided by the above embodiments can be completed by different program modules according to needs when implementing the corresponding data processing method, so as to complete all or part of the above processing. In addition, the apparatus provided by the above embodiments and the corresponding method embodiments belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0166] Figure 10 Another structural schematic diagram of a data processing apparatus provided by an embodiment of the present disclosure is provided. As shown in the figure, the apparatus is applied to a second device, and the apparatus comprises: Figure 10 A determining module configured to determine a first routing entry.

[0167] A second transmitting module configured to transmit the first routing entry to a first device through a first channel. The first channel is a channel based on a high-speed interconnection protocol between the first device and the second device.

[0168] It can be understood that the data processing apparatus provided by the above embodiments can be completed by different program modules according to the needs when implementing the corresponding data processing method, so as to complete all or part of the above processing. In addition, the apparatus provided by the above embodiments and the embodiments of the corresponding method belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0169] An embodiment of the present disclosure provides a computer-readable storage medium storing executable instructions, wherein the executable instructions, when executed by a processor, will trigger the processor to execute the data processing method provided by an embodiment of the present disclosure.

[0170] In some embodiments, the computer-readable storage medium can be a Ferroelectric RAM (FRAM), a Read-Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable ROM (EPROM), an Electrically Erasable Programmable ROM (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a CD-ROM memory, etc. It can also be various devices including one or any combination of the above memories.

[0171] In some embodiments, the executable instructions can be in the form of a program, software, software module, script or code, written in any form of programming language (including a compiled or interpreted language, or a declarative or procedural language), and can be deployed in any form, including being deployed as an independent program or as a module, model, subroutine or other unit suitable for use in a computing environment.

[0172]

[0173] ​As an example, the executable instructions can be deployed to execute on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected via a communication network.

[0174] The embodiment of the disclosure provides a computer program product, the computer program product comprises computer programs / instructions, and the computer programs / instructions are executed by a processor to implement the data processing method provided by the embodiment of the disclosure.

[0175] Figure 11 A structural schematic diagram of an electronic device is provided in the embodiment of the disclosure. As shown in the figure, the electronic device 110 comprises a processor 1101 and a memory 1102 for storing computer programs capable of running on the processor; the processor 1101 is used to run the computer programs to execute any one of the data processing methods provided by the embodiment of the disclosure. Figure 11

[0176] In actual application, the electronic device 110 can further comprise at least one network interface 1103. Various components in the electronic device 110 are coupled together through a bus system 1104. It can be understood that the bus system 1104 is used to realize the connection and communication between the components. The bus system 1104 comprises not only a data bus, but also a power supply bus, a control bus and a status signal bus. However, in order to clearly illustrate, all kinds of buses are marked as the bus system 1104 in the figure. The number of the processor 1101 can be at least one. The network interface 1103 is used for wired or wireless communication between the electronic device 110 and other devices. Figure 11

[0177] The memory 1102 in the embodiment of the disclosure is used to store various types of data to support the operation of the electronic device 110.

[0178] ​​The method disclosed by the embodiments of the present disclosure can be applied to the processor 1101 or implemented by the processor 1101. The processor 1101 can be an integrated circuit chip having a signal processing capability. In the implementation process, each step of the above method can be completed by the integrated logic circuit or the instruction in the form of software in the processor 1101. The processor 1101 described above can be a general processor, a digital signal processor (DSP), or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. The processor 1101 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present disclosure. The general processor can be a microprocessor or any conventional processor, etc. In combination with the steps of the method disclosed in the embodiments of the present disclosure, the hardware decoding processor can be directly embodied to complete the execution, or the hardware and software modules in the decoding processor can be combined to complete the execution. The software module can be located in the storage medium, and the storage medium is located in the memory 1102. The processor 1101 reads the information in the memory 1102 and combines the hardware to complete the steps of the above method.

[0179] In some embodiments, the electronic device 110 can be implemented by one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors (Microprocessors), or other electronic elements, for executing the above-described methods.

[0180] It should be understood that the steps can be reordered, added, or deleted using the various forms of flow shown above. For example, the steps described in the present disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved, and the present disclosure does not limit herein.

[0181] In addition, the terms "first", "second", etc. are used only for the purpose of description, and should not be understood as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0182] The above description is merely a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A data processing method, the method being applied to a first device, the first device comprising: A first memory and a first cache, wherein the first memory is used to store a first routing table; The method includes: The first routing table entry is received from the second device through the first channel; the first channel is a channel between the first device and the second device based on a high-speed interconnect protocol. The first routing table is updated according to the first routing table entry, and the packet to be forwarded is sent using the updated first routing table.

2. The method according to claim 1, wherein the first channel is a first type of first channel or a second type of first channel; The first channel of the first type is a channel based on a high-speed interconnect protocol between the first cache and the cache of the second device; The second type of first channel is a channel between the first memory and the second device based on a high-speed interconnect protocol.

3. The method according to claim 1 or 2, further comprising: Determine the device information and / or the first memory size of the first device; The device information is used to indicate the high-speed interconnect protocol version supported by the first device; Generate a channel establishment request based on the device information and / or the first memory size; The channel establishment request is used to request the establishment of a first type of first channel or a second type of first channel; Send the channel establishment request to the second device.

4. The method according to claim 3, wherein the generation of the channel establishment request includes one of the following: Determine the starting address, total length, and access granularity of the first routing table in the first memory, and generate a channel establishment request based on the starting address, total length, and access granularity; Determine the address information of the first cache, and generate a channel establishment request based on the address information.

5. The method according to claim 1, wherein if the first channel is a first type of first channel, updating the first routing table according to the first routing table entry includes: Retrieve the first routing table entry from the first cache; Write the first routing table entry into the first routing table in the first memory.

6. The method according to claim 1, further comprising one of the following: The message to be forwarded is received through a second channel; the second channel is a high-speed interconnect protocol-based channel between the first cache of the first device and the last level cache of the processor, and the first device and the processor belong to the same device; Receive the message to be forwarded from other devices.

7. The method according to claim 1, wherein the packet to be forwarded is sent using the updated first routing table, comprising: If the destination address of the packet to be forwarded is determined to be the device to which the first device belongs based on the first routing table, the packet to be forwarded is sent to the processor of the device through the second channel. The second channel is a high-speed interconnect protocol-based channel between the first cache of the first device and the last level cache of the processor.

8. The method according to claim 1, further comprising one of the following: Poll the first cache to determine whether the first cache has received the first routing table entry; The flag status of the first memory is periodically checked, and the first routing table entry is determined based on the flag status.

9. A data processing method, the method being applied to a second device, the method comprising: Determine the first routing table entry; The first routing table entry is sent to the first device via the first channel; The first channel is a channel between the first device and the second device based on a high-speed interconnect protocol.

10. A first device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform: The first routing table entry is received from the second device through the first channel; the first channel is a channel between the first device and the second device based on a high-speed interconnect protocol. The first routing table is updated according to the first routing table entry, and the packet to be forwarded is sent using the updated first routing table.

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