Priority queue scheduling method and device

Abstract

The invention discloses a priority queue scheduling method and device, the method can be applied to network intermediate equipment, an output port of the network intermediate equipment is provided with a virtual input port cache, and the method comprises the following steps: determining N logic queues included in the virtual input port cache; and for a first logic queue in the N logic queues, scheduling each network packet according to the network packet descriptor of each network packet in the first logic queue. Each logical queue is used for caching data packets from the same input port, each logical queue is composed of M sub-logical queues, and one sub-logical queue is used for storing a network packet of one priority and a corresponding network packet descriptor. According to the method, on the basis of a traditional VIQ structure, each logic queue is further divided into a plurality of virtual priority queues. And the plurality of virtual priority queues in each logic queue are independently scheduled, so that the problem of queue head blockage when the network packet is queued and cached during forwarding based on the priority can be avoided.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a priority queue scheduling method and device. Background Art

[0002] Different services require different Quality of Service (QoS). In order to meet the QoS requirements of various services, the processing and forwarding rules of business data are usually controlled.

[0003] In order to provide better services, a priority-based virtual input queue (VIQ) technology is proposed. However, when there are multiple virtual queues with the same priority level network packets that need to be queued and cached at the same time, the head-of-line blocking (HoL) problem will occur. Summary of the invention

[0004] The present application provides a priority queue scheduling method and device, which can improve the efficiency of queue scheduling and reduce the forwarding delay of network packets.

[0005] In a first aspect, a priority queue scheduling method is provided, wherein the execution subject of the method is an electronic device with computing capability, and the electronic device may be a computer or a personal computer or a processor, such as a field programmable gate array (FPGA).

[0006] The priority queue scheduling method can be applied to a network intermediate device, the output port of which is provided with a virtual input port cache, and the method comprises: the network intermediate device determines N logical queues included in the virtual input port cache; for the first logical queue among the N logical queues, the network intermediate device schedules each network packet according to the network packet descriptor of each network packet in the first logical queue, so as to store each network packet in sequence in the priority cache queue. Wherein, each logical queue is used to cache data packets from the same input port, and each logical queue is composed of M sub-logical queues, and one sub-logical queue is used to store at least one network packet of the same priority and the network packet descriptor of at least one network packet. Network packets of different priorities in the first logical queue are independently stored in the priority cache queue. The network packet descriptor includes the forwarding priority, packet length and packet entry time of the network packet, N is the number of input ports, and M is the number of priority levels.

[0007] In this solution, based on the traditional VIQ structure, the logical queue corresponding to each input port is further divided into several virtual priority queues. Multiple virtual priority queues in each logical queue are scheduled independently, thus avoiding the head-of-line blocking problem when network packets are queued and cached when forwarding based on priority.

[0008] In a possible implementation, the network intermediate device schedules each network packet according to the network packet descriptor of each network packet in the first logical queue, including: Obtain the network packet descriptor of each network packet in the first logical queue, and determine the timing value corresponding to each network packet according to the packet entry time in the obtained network packet descriptor t i ;in, t i satisfy: t i = t d – t s , t d is the maximum queue delay, t s The current reference time value t r and network packet arrival time t m The time interval between t r Greater than or equal to t d ; According to the timing value corresponding to each network packet t i Determining a network packet with the shortest absolute deadline in the first logical queue; Cache the network packets with the shortest absolute deadline into the priority cache queue.

[0009] In this solution, each logical queue can be set with a corresponding queue scheduling module. Since each sub-logical queue is independent, each logical queue is also independent. Therefore, N logical queues can be queued and scheduled in parallel, thereby improving the efficiency of queue caching. In addition, network packets with short absolute deadlines can be queued and cached first, thereby increasing the time margin for network packet output and reducing the forwarding delay of network packets.

[0010] In a possible implementation, t r Generated by a maintained cyclic accumulation timer, and t s satisfy: .

[0011] In this scheme, considering that the network packets in each sub-logical queue in each logical queue are scheduled independently, the actual packet arrival time cannot keep increasing. Therefore, a cyclic accumulation timer is maintained to generate a reference time. t r If overflow occurs, the bit is set to 0 to start a new cycle, so that network packets of different priorities can be queued and cached at the same time.

[0012] In a possible implementation, the method further includes: If the processing time of the first network packet in the first logical queue is greater than or equal to the guaranteed network packet delay of the first network packet, the descriptor of the first network packet is stored in the delay guarantee queue; wherein the network packets in the delay guarantee queue are scheduled first; If the delay guarantee queue is not empty, the network packet corresponding to the network packet descriptor in the delay guarantee queue is output.

[0013] In this solution, a delay guarantee queue can be maintained for outbound scheduling. The delay guarantee queue can store network packets whose processing time is close to the processing delay requirement. When there is a network packet in the delay guarantee queue, it is immediately scheduled for output to ensure the maximum forwarding delay requirement of the network packet in each queue.

[0014] In a possible implementation, the network packet guaranteed delay of the first network packet is the guaranteed delay of the queue where the first network packet is located, wherein the guaranteed delay of the queue is (pre-)set, and the guaranteed delays of queues with different priorities are different.

[0015] By flexibly setting the guaranteed delay of the queue, the guaranteed delays of queues with different priorities can be different, thereby balancing the priority and forwarding delay requirements of data packets.

[0016] In a possible implementation, storing the first network packet in a delay guarantee queue includes: Obtaining the network packet descriptor of each network packet in the first logical queue in order from high to low priority; Determine a timing value according to a packet entry time in a network packet descriptor of each network packet and a current reference time; If the timing value is greater than the corresponding network packet guaranteed delay, the network packet descriptor is read and the obtained network packet descriptor is stored in the delay guarantee queue.

[0017] In this scheme, the writing mechanism of the latency guarantee queue is similar to the aforementioned queue scheduling process, which can ensure the efficiency of the queue cache as much as possible.

[0018] In a possible implementation, the method further includes: If the delay guarantee queue is empty, poll the network packets of each priority in the first logical queue; For the first-priority network packet, whether to send the first-priority network packet is determined based on the packet length of the first-priority network packet and the weight of the exportable data length; wherein, if the packet length of the first-priority network packet is less than or equal to the weight of the exportable data length, the first-priority network packet is sent.

[0019] In this scheme, when the latency guarantee queue is empty, for network packets of each priority level, dequeue scheduling can be performed according to the packet length of the network packet and the weight of the output data length, which can ensure the fairness of bandwidth allocation for different network packets.

[0020] In a possible implementation, the method further includes: After polling the first logical queue, the initial value of the output data length weight corresponding to each priority queue in the first logical queue is updated, wherein the updated initial value of the output data length weight is the remaining output data length of each priority queue at the end of the previous round of scheduling.

[0021] After the last round of scheduling is completed, the scheme updates the initial value of the corresponding output data length weight, and can flexibly allocate the service time and bandwidth obtained by each priority queue.

[0022] In a second aspect, an electronic device is provided, the electronic device comprising: The output port is provided with a virtual input port buffer; The processing module is used to: determine the N logical queues included in the virtual input port cache, and for the first logical queue among the N logical queues, schedule each network packet according to the network packet descriptor of each network packet in the first logical queue, so as to store each network packet in sequence in the priority cache queue; wherein each logical queue is used to cache data packets from the same input port, and each logical queue is composed of M sub-logical queues, and one sub-logical queue is used to store at least one network packet of the same priority and the network packet descriptor of at least one network packet. Network packets of different priorities in the first logical queue are independently stored in the priority cache queue. The packet descriptor includes the forwarding priority, packet length and packet entry time of the network packet, N is the number of input ports, and M is the number of priority levels.

[0023] In a possible implementation, the processing module is used to schedule each network packet according to the network packet descriptor of each network packet in the first logical queue, including: Obtain the network packet descriptor of each network packet in the first logical queue, and determine the timing value corresponding to each network packet according to the packet entry time in the obtained network packet descriptor t i ;in, t isatisfy: t i = t d – t s , t d is the maximum queue delay, t s The current reference time value t r and network packet arrival time t m The time interval between t r Greater than or equal to t d ; According to the timing value corresponding to each network packet t i Determining a network packet with the shortest absolute deadline in the first logical queue; Cache the network packets with the shortest absolute deadline into the priority cache queue.

[0024] In a possible implementation, t r Generated by a maintained cyclic accumulation timer, and t s satisfy: .

[0025] In a possible implementation, the processing module is further used for: If the processing time of the first network packet in the first logical queue is greater than or equal to the guaranteed network packet delay of the first network packet, the descriptor of the first network packet is stored in the delay guarantee queue; wherein the network packet corresponding to the network packet descriptor in the delay guarantee queue is scheduled first; If the delay guarantee queue is not empty, the network packets in the delay guarantee queue are output.

[0026] In a possible implementation, the network packet guaranteed delay of the first network packet is the guaranteed delay of the queue where the first network packet is located, wherein the guaranteed delay of the queue is (pre-)set, and the guaranteed delays of queues with different priorities are different.

[0027] In a possible implementation, the processing module is used to store the first network packet in the delay guarantee queue, including: Obtaining the network packet descriptor of each network packet in the first logical queue in order from high to low priority; Determine a timing value according to a packet entry time in a network packet descriptor of each network packet and a current reference time; If the timing value is greater than the corresponding network packet guaranteed delay, the network packet descriptor is read and the obtained network packet descriptor is stored in the delay guarantee queue.

[0028] In a possible implementation, the processing module is further used for: If the delay guarantee queue is empty, poll the network packets of each priority in the first logical queue; For the first-priority network packet, whether to send the first-priority network packet is determined based on the packet length of the first-priority network packet and the weight of the exportable data length; wherein, if the packet length of the first-priority network packet is less than or equal to the weight of the exportable data length, the first-priority network packet is sent.

[0029] In a possible implementation, the processing module is further used for: After polling the first logical queue, the initial value of the output data length weight corresponding to each priority queue in the first logical queue is updated, wherein the updated initial value of the output data length weight is the remaining output data length of each priority queue at the end of the previous round of scheduling.

[0030] In a third aspect, an electronic device is provided, which has the function of implementing the behavior in the method embodiment of the first aspect above. The function can be implemented by hardware, or it can be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. The electronic device includes a communication interface and a processor, and optionally, also includes a memory. The memory is used to store computer programs or instructions, and the processor is coupled to the memory and the communication interface. When the processor executes the computer program or instruction, the electronic device executes the method executed by the above method embodiment.

[0031] In a fourth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed, the method performed in the first aspect is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A forwarding model for a network intermediate device provided in an embodiment of the present application; Figure 2 A forwarding model based on priority scheduling for a network intermediate device provided in an embodiment of the present application; Figure 3 A schematic diagram of priority-based scheduling of a network intermediate device provided in an embodiment of the present application; Figure 4 for Figure 3 A schematic diagram showing the existence of head blocking in the priority queue scheduling in the VIQ structure shown; Figure 5 A schematic diagram of the data plane architecture of the SDN device provided in the embodiment of the present application; Figure 6 A functional diagram of a service port provided in an embodiment of the present application; Figure 7 A schematic diagram of the architecture of a scheduling output unit provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of the queue scheduling module provided in the embodiment of the present application; Fig. 9 A virtual priority cache structure based on VIQ provided in an embodiment of the present application; Fig.10 A multi-priority parallel enqueue scheduling process based on EDF provided in an embodiment of the present application; Fig.11 Schematic diagram of the EDF scheduling process provided in the embodiment of the present application; Fig.12 A schematic diagram of the dequeue scheduling process of the delay guarantee queue provided in the embodiment of the present application; Fig.13 A schematic diagram of the structure of the dequeue scheduling module provided in an embodiment of the present application; Fig.14 A state transition diagram for dequeue scheduling provided in an embodiment of the present application; Fig.15 A schematic diagram of state transitions during the dequeue scheduling process provided in an embodiment of the present application; Fig.16 A flowchart of a priority queue scheduling method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0034] Different services require different Quality of Service (QoS). By using the programmable interface to develop the control of the device, the processing and forwarding rules of the network packets can be determined according to the different QoS requirements of the network packets to meet the QoS requirements of different services as much as possible.

[0035] Typically, packets entering a device are forwarded through an intermediate network device, such as a switch or router. For example, see Figure 1 , shows a network intermediate device forwarding model. Figure 1As shown, the input device receives the network packet through the input interface, searches the forwarding table (i.e., forwarding rules) according to the destination address of the network packet, determines the output port of the network packet, transmits it to the network intermediate device through the output port, and finally transmits it to the corresponding port by the network intermediate device. Figure 1 For example, the number of input ports and output ports is N, where N is a positive integer.

[0036] Traditional network middleware forwards received network packets in the order in which they are received. Different network packets may have different lengths, importance or transmission delays. Forwarding network packets according to traditional network middleware may lead to unreasonable allocation of network resources and low utilization. And with the diversification of business types, the requirements for QoS are more stringent, such as stricter transmission delay requirements. For this reason, a priority queue scheduling mechanism is proposed, that is, scheduling each network packet according to its priority to meet the QoS requirements of each network packet.

[0037] For example, see Figure 2 , shows a forwarding model based on priority scheduling of a network intermediate device. Figure 2 and Figure 1 The difference is that the network intermediate device determines the forwarding priority of the network packet based on the characteristic information of the network packet, and stores the data packet in the queue cache according to the forwarding priority. The data packets in the queue cache are output in sequence based on a certain scheduling algorithm.

[0038] like Figure 3 , showing a schematic diagram of priority-based scheduling of network intermediate devices. Figure 3 Take M priorities as an example. Priority queue scheduling includes two parts: queue scheduling and dequeue scheduling. In order to avoid multiple input ports transmitting network packets to the same output port at the same time, which may cause blocking and packet loss, the network packets transmitted from each input port are first stored in the priority queue cache based on the queue scheduling algorithm to ensure that only one network packet with the same priority from different input ports is queued at the same time. Based on the dequeue scheduling algorithm, the network packets in the priority queue cache are sorted and scheduled to ensure that only one network packet is output through the actual link port at the same time.

[0039] In order to provide more optimized cache services and achieve more flexible and efficient queue management, the virtual queue (VQ) technology is proposed. VQ technology divides virtual logical queues according to the different characteristics of network packets. According to the location of the virtual queue, VQ can be divided into virtual input queue (VIQ) and virtual output queue (VOQ). VIQ sets a virtual logical queue for each input port at the output port to cache the network packets transmitted from each input port to avoid congestion of network packets when passing through network intermediate devices and improve the forwarding efficiency of network intermediate devices. However, the VQ model in the network intermediate device does not take into account the priority of the network packet and cannot meet the actual forwarding requirements of the business well.

[0040] To this end, a priority-based virtual output queue scheduling strategy is proposed. This scheduling strategy refers to setting multiple priority virtual sub-queues in each virtual output queue, using a scheduling algorithm to fairly schedule the output of network packets with the same priority in each virtual output queue, or scheduling the output of network packets with different priorities in the virtual output queue in order from high to low priority. With the VIQ cache technology, there are situations where network packets with the same priority in multiple virtual queues need to be queued and cached at the same time, so there will be a head-of-line blocking (HoL) problem during queue scheduling.

[0041] For example, see Figure 4 , which is a schematic diagram of the head blocking in the priority enqueue scheduling in the transmission VIQ structure. Figure 4 Take 8 priorities (0-7) as an example. When a network packet with a priority of 7 is enqueued and cached, the head network packet with a priority of 7 in virtual queue A needs to wait and cannot be read out immediately, thus blocking the subsequent reading of network packets with priorities of 5 and 4, that is, priority 5 and priority 4 are blocked. HoL blocking will reduce the efficiency of enqueuing scheduling of the priority queue cache and increase the forwarding delay of the blocked network packets. The current priority-based virtual output queue scheduling strategy has the problem of enqueuing blocking and cannot simultaneously guarantee the fairness of bandwidth allocation and maximum forwarding delay requirements of the priority queue output.

[0042] In view of this, an embodiment of the present application proposes a new priority queue scheduling method, which can reduce queue entry blocking while ensuring the fairness of bandwidth allocation and maximum forwarding delay requirements of the priority queue output.

[0043] To facilitate understanding of the technical solutions provided by the embodiments of the present application, some concepts related to the embodiments of the present application are first introduced.

[0044] 1) Earliest Deadline First (EDF) algorithm: Scheduling is based on the absolute deadline of network packets, that is, giving priority to network packets with short absolute deadlines. It is widely used in scheduling control of real-time tasks. The EDF algorithm specifies a maximum network packet delay for each queue and maintains a timing value for each network packet. t i , t i The size of satisfies formula (1), where i Represents the network packet number in the queue, t m Represents the time when the network packet arrives. t d Represents the maximum queue delay. When multiple network packets need service at the same time, select t i Minimum (i.e. min t i ) corresponding to the network packet, that is, the network packet with the shortest absolute deadline is scheduled.

[0045] t i = t m + t d (1)

[0046] 2) Deficit Round Robin (DRR) algorithm: It is also a polling scheduling algorithm based on weights. The weight of the Weighted Round Robin (WRR) algorithm is the number of network packets, while the weight of the DRR algorithm is the byte length of the network packet. The DRR algorithm maintains a counter with an initial value of the weight for each priority queue. When polling to send a network packet, the length of the first packet in the queue is first compared with the weight. If it is less than or equal to the counter value, the packet is sent, and the counter value is divided by the packet length. If it is greater than the counter value, the network packet is not sent. When all counter values ​​are zero or the length of all first packets in the queue is greater than the corresponding counter value, the next polling cycle begins. At the beginning of the next polling cycle, the initial weight of each queue needs to be added with the counter residual value of the corresponding queue in the previous polling cycle.

[0047] The technical solution provided by the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0048] The present application embodiment is applicable to SDN, such as Figure 5 , which is a schematic diagram of the data plane architecture of the SDN device provided in an embodiment of the present application.

[0049] The data plane architecture of SDN equipment includes service ports and control ports. Among them, the service port mainly completes the error control, editing processing, classification forwarding and QoS guarantee functions of the network packet. The service port may include a receiving unit, a processing switching unit and a scheduling output unit. The control port is mainly used for control message parsing, flow table update and network packet encapsulation upload functions. The control port may include a control message receiving unit, a control message processing unit and a scheduling encapsulation output unit. The processing switching unit of each port is linked to other ports and the control port except this port. There are three ways to process the input network packet: upload to the controller, forward by other ports and discard.

[0050] like Figure 6 As shown, a functional schematic diagram of a service port is shown. Figure 6 , briefly introduces the structure and function of each functional unit of the business port.

[0051] (1) Receiving unit: mainly used to complete the reception and verification of network packets. The receiving unit may include an input module and a packet verification module. The input module can be used to convert physical signals into a data stream that can be processed by the user. The packet verification module is used to perform data verification, discard network packets with verification errors, and pass correct network packets to the next stage.

[0052] (2) Processing and switching unit: mainly used to complete the editing and processing of network packets and classified forwarding according to the packet feature fields. The processing and switching unit may include a network packet parser, a layer 2 forwarding flow table matching module, a high-level flow table matching module, a network packet cache module, an action execution module, a network packet reverse parser and a network packet selector. Among them, the network packet parser is used to extract the packet feature information of the network packet for subsequent flow table matching. The layer 2 forwarding flow table matching module transmits the layer 2 switching network packet to the network packet selector, and passes the network packet that needs high-level table lookup processing to the post-processing. The high-level flow table matching module completes the feature field matching of the network layer and the transport layer, and writes the matching results into the action set. The action execution module is used to execute the packet editing action in the action set to realize the editing and processing of the network packet. The network packet cache module is used to store the original packet header and payload information of the network packet. The network packet reverse parser is used to complete the splicing of the new packet header and payload fields, and then output it to the network packet selector. The network packet selector is used to cache the input layer 2 forwarding network packet and the high-level processing network packet respectively, and then pass them to the corresponding output port according to their output port information.

[0053] (3) Scheduling output unit: It is mainly used to cache network packets from different input ports, manage queues and sort outputs according to the priority of network packets, and realize QoS guarantee function based on priority queue scheduling. The scheduling output unit includes a queue scheduling module and an output module. The queue scheduling module is used to complete the cache management and scheduling of priority queues and provide network packet forwarding delay guarantee function. The output module is used to convert data streams into physical signal outputs.

[0054] The scheduling output unit includes the queue scheduling module and the queue scheduling module. For example, see Figure 7 , shows the architecture of the scheduling output unit. The enqueue scheduling module is used to cache network packets from different input ports, and perform enqueue scheduling on the network packets, and store the network packets cached in the buffer area of ​​each input port into the priority queue buffer area. The dequeue scheduling module is mainly used to perform dequeue scheduling on the network packets in the priority queue buffer, and read out the network packets in the priority queue buffer area in sequence and output them to the Ethernet interface controller. The scheduling output unit can be implemented by FPGA. Figure 7 The network packet descriptor in includes key information of the network packet, such as forwarding priority, packet length, and packet entry time.

[0055] In the embodiment of the present application, the queue scheduling module adopts the virtual priority cache structure of VIQ, that is, on the basis of the traditional VIQ cache queue, several virtual priority sub-queues are further divided. The queue scheduling module provided by the embodiment of the present application can improve the queue cache efficiency and reduce the forwarding delay of network packets.

[0056] For example, see Figure 8 , is a schematic diagram of the structure of the queue scheduling module provided in the embodiment of the present application. For an SDN data plane with N input ports and supporting M-level priority queues, the input port buffer area of ​​the queue scheduling module can establish N logical queues, and each VIQ logical queue is composed of M sub-logical queues. Figure 8 Take the queue scheduling module including three input port buffers as an example. Figure 8 As shown, these three input port buffers are input port buffer VIQ logical queue A-input port buffer VIQ logical queue C as an example. Each input port buffer VIQ logical queue includes multiple network packet buffer VIO queues (i.e., sub-logical queues). Each network packet buffer VIO queue is used to store a network packet of a priority and the key information of the network packet. The key information of the network packet can be represented by a network packet descriptor. The network packet descriptor includes information such as forwarding priority, packet length, and packet entry time. The network packet buffer VIO queue can be implemented by FIFO, and each VIQ queue in the input port buffer area independently completes the writing of each FIFO according to the forwarding priority in the input network packet descriptor.

[0057] Figure 8 The structure shown can independently cache the network packets to be scheduled for output according to the priority of each network packet, avoiding the HoL problem of priority enqueue scheduling when the traditional VIQ cache queue adopts a single FIFO cache structure, and can improve the enqueue cache efficiency of the network packet and reduce the forwarding delay of the network packet.

[0058] For easier understanding, see Fig. 9 , shows a VIQ-based virtual priority cache structure. Fig. 9 Take N=4, M=8 as an example. That is, the input port buffer area includes input port buffer VIQ logical queue A-input port buffer VIQ logical queue D (that is, virtual priority queue A-virtual priority queue D), and each input port buffer VIQ logical queue includes 8 network packet buffer VIO queues 0-7.

[0059] Although conflicts still exist when network packets with the same forwarding priority in different VIQ logical queues are queued at the same time, network packets with different forwarding priorities in the same VIQ logical queue can be queued independently, thus reducing congestion. Fig. 9 As shown, when M=8, when the queue scheduling module controls the network packets with a priority of 7 in the VIQ logical queue D to be queued and cached, the network packets with a priority of 7 in the logical queue A need to wait, but the network packets with a priority of 5 can be queued and cached. It can be seen that the virtual priority cache structure of VIQ provided by the embodiment of the present application can avoid the head-of-line blocking problem when the network packets are queued and cached when forwarding based on priority, compared with the traditional VIQ cache queue.

[0060] In the embodiment of the present application, different EDF scheduling units are used to perform parallel enqueue scheduling for network packets of the same priority in each VIQ virtual cache queue. This can greatly improve the enqueue cache efficiency of network packets. In addition, network packets with short absolute deadlines can be prioritized for enqueue caching, increasing the time margin for network packet scheduling output and reducing the forwarding delay of network packets.

[0061] For a network packet that supports N input ports and M levels of priority, M EDF scheduling modules can be used to schedule and write M-level priority queues. Each EDF scheduling module reads the min value in each VIQ virtual priority queue in the N input port buffer. t i The corresponding network packet is written into the corresponding priority queue in the priority cache queue of the output port. t m It is impossible to keep increasing, therefore, in the embodiment of the present application, each EDF scheduling module maintains a cyclic accumulation timer in real time to generate a reference timet r The timing range of this timer is 0~max t r (max t r ≥ t d ), used to generate reference time t r The timing value maintained by the EDF scheduling module t i Satisfies formula (2): t i = t d – t s (2)

[0062] in, t s Represents the time the network packet has been processed, that is, the current reference time value t r and network packet arrival time t m The time interval between t r Is a loop-accumulated value. When calculating t i Time, reference time t r It may have overflowed. In this case, set it to 0 to start a new cycle. t r < t m Therefore, the calculation t s When t r < t m ,illustrate t r is the reference time for a new cycle. In this case, the cycle time needs to be added for calculation. t s Satisfies formula (3): .

[0063] For easier understanding, see Fig.10 , shows the multi-priority parallel enqueue scheduling process based on EDF. Fig.10 With input port N=3 (such as Fig.10For example, VIQ logical queue A-VIQ logical queue C), that is, the number of priority queues is 8 (priority 0 cache FIFO-priority 7 cache FIFO). Each virtual priority queue includes 8 VIO queues. Fig.10 As shown, each VIO queue can be scheduled independently based on Fig.10 It can realize the simultaneous entry and caching of 8 network packets of different priorities, thus improving the efficiency of the entry and caching. It can also give priority to the entry and caching of network packets with short absolute deadlines, thus increasing the time margin for the scheduling and output of network packets and reducing the forwarding delay of network packets.

[0064] Each VIQ queue in the input port buffer area independently completes the writing of each VIQ queue according to the network packet descriptor. For example, see Fig.11 , is a schematic diagram of the EDF scheduling process provided in an embodiment of the present application. Fig.11 Taking each VIQ logical queue including 8 FIFOs as an example, accordingly, the embodiment of the present application adopts 8 EDF scheduling modules to respectively complete the queue entry control of 8 queues with different priorities. Fig.11 The implementation mechanism of the EDF scheduling module is introduced by taking the network packet enqueue scheduling process of the priority 0 queue as an example.

[0065] First, the EDF scheduling module can obtain the network descriptor in the non-empty priority 0 cache FIFO in the VIQ queue of each input port, so as to calculate the timing value according to the packet entry time in the network packet descriptor, and make a decision on whether to schedule the corresponding network packet according to the timing value. The decision result is the registered input port buffer area number and the network packet descriptor. The EDF scheduling module can output the obtained decision result. In other words, the scheduling process of the EDF scheduling module includes a decision state and an output state.

[0066] The calculation method of the timing value refers to the aforementioned formula (4), wherein 1500us and 2000us in formula (4) may also be other possible values. In a possible implementation, the network packet with a larger timing value needs to store the network packet descriptor each time a decision is made, waiting for the next decision. In another possible implementation, a "fast out" FIFO can be used to cache the network packet descriptor. The FIFO in the "fast out" mode can obtain the head of queue cache information in the FIFO from the output port register without a read operation. In this case, it is only necessary to calculate according to the packet entry time, reference time and maximum forwarding delay of the network packet in the non-empty priority 0 cache FIFO output port register, determine the network packet descriptor in the priority 0 cache FIFO corresponding to the minimum timing value and store it. Afterwards, the stored input port buffer area number can be jumped to the output state.

[0067]

[0068] The EDF scheduling module reads data of corresponding length from the priority 0 cache FIFO in the VIQ queue in the corresponding input port buffer according to the registered input port buffer number and network packet descriptor, writes it into the priority 0 cache queue in the priority queue buffer, and outputs a new network packet descriptor. The new network packet descriptor includes the packet length and packet arrival time of the read network packet.

[0069] Usually, the dequeue scheduling module adopts the SP (Strict Priority) algorithm, WRR (Weighted Round Robin) algorithm, DRR algorithm and URR (Urgency-based Round Robin) algorithm, but none of them can guarantee the delay requirements of network packets. In addition, the SP algorithm, WRR algorithm and URR algorithm also have unfairness in the allocation of network packet bandwidth. To this end, the embodiment of the present application provides a new DRR algorithm that can give priority to outputting delay-limited adjacent networks, thereby ensuring the fairness of network packet bandwidth allocation and forwarding delay requirements.

[0070] First, the DRR algorithm provided by the embodiment of the present application is introduced. The DRR algorithm provided by the embodiment of the present application sets up a delay guarantee queue for storing network packets whose internal processing time is close to the processing delay time requirement. When there is a network packet in the delay guarantee queue, the scheduling output is immediately performed. When the delay guarantee queue is empty, the scheduling output uses the traditional DRR algorithm to schedule each priority queue. Among them, the writing mechanism of the delay guarantee queue is similar to the aforementioned queue scheduling process. The writing of the delay guarantee queue also requires a cyclically accumulated reference time. t r It is also necessary to maintain a timing value for each network packet, which is the time when the network packet enters the processor. t m .

[0071] Combine the following Fig.12 , describes the queue scheduling of the delay guarantee queue. Fig.12 , which is a flow chart of implementing dequeue scheduling based on the DRR algorithm provided in an embodiment of the present application. Fig.12 Take the priority level M as an example. Fig.12 middle, P ( P ∈[0,M-1]) is the priority level, P The larger the value, the higher the priority; W P Priority P The weight of the queue, indicating the priority queue in each round of scheduling PThe length of data that can be output. WD P Priority P The initial weight of a queue is a preset value assigned according to the importance of each priority queue; WA P The priority at the end of the previous round of scheduling P The weight margin of the queue's output data length; L P Priority P The length of the first network packet in the queue.

[0072] When dispatching out of the team, a certain time period is used t c Timing value of network packets in each queue t m With reference time t r The time interval between is calculated, that is, the time consumed by the network packet processing is obtained t s .like t s Greater than or equal to the guaranteed delay of network packets t g , the network packet is written into the delay guarantee queue for priority scheduling. t g = 1250us, t s Formula (3) is satisfied. The embodiment of the present application guarantees the delay of network packets. t g The specific value of is not limited. Moreover, in the embodiment of the present application, the network packet guarantee delays corresponding to queues of different priorities may be different. For example, the network packet guarantee delay corresponding to a queue with a high priority may be smaller than the network packet guarantee delay corresponding to a queue with a low priority. The network packet guarantee delay corresponding to each priority queue may be pre-set or flexibly set later according to actual needs.

[0073] For details about this application, please see Fig.13 , is a structural diagram of the dequeue scheduling module provided in an embodiment of the present application. Take the existence of 8 priorities as an example. The dequeue scheduling module may include 8 priority queue cache FIFOs and 8 network packet descriptor FIFOs. The 8 priority queue cache FIFOs are used to store network packet data of different priorities, and the 8 network packet descriptor FIFOs are used to cache the network packet descriptors of the corresponding priority queues. The writing of each priority queue cache FIFO and the network packet descriptor FIFO is carried out independently and in parallel. The dequeue scheduling module also includes a delay guarantee queue FIFO, which is used to cache network packet descriptors whose internal processing time is close to the maximum forwarding delay time requirement.

[0074] The writing process of the latency guarantee queue is similar to the decision-making process of the queue scheduling module. For example, the network packet descriptor FIFO is also designed using the "fast out" FIFO. The queue scheduling module maintains a 0~100us cyclic accumulation timer to generate the reference time. t r . Taking the order from priority 7 to priority 0 as an example, every time the timer value accumulates to 100, a timing value is calculated based on the packet entry time in the corresponding network packet descriptor FIFO output port register and the current reference time. If the timing value is greater than or equal to the network packet guaranteed delay, the network packet descriptor in the FIFO is obtained and written into the delay guarantee queue FIFO together with the priority information corresponding to the FIFO; if the timing value is less than the network packet guaranteed delay, the next priority is polled. The timing value satisfies formula (5).

[0075] .

[0076] See also Fig.14 , is a state transition diagram of the dequeue scheduling provided in the embodiment of the present application. The dequeue scheduling process includes ten states: polling cycle reset state, delay guarantee queue polling state, priority 7 queue polling state ~ priority 0 queue polling state. 8 initial weight registers can be set WD 0~7 [15:0], 8 weight registers W 0~7 [15:0], 8 weight margin registers WA 0~7 [15:0] and 8 packet length registers L 0~7 [15:0]. WD 0~7 [15:0] is used to record the preset value of each priority queue weight. W 0~7 [15:0] is used to record the data length that can be output by each priority queue in each round of scheduling. WA 0~7 [15:0] is used for the remaining output data length of each priority queue at the end of the previous round of scheduling. L 0~7 [15:0] is used to record the length of the first network packet in each priority queue. The value of each packet length register is equal to the packet length in the FIFO output port register of the corresponding non-empty network packet descriptor of the corresponding priority. When the FIFO is empty, the value of the packet length register is 0. The initial values ​​of the 8 weight registers can be preset values ​​[1700, 3400, 5100, 6800, 8500, 10200, 11900, 13600]. The initial values ​​of the 8 weight margin registers can be 0.

[0077] Polling cycle reset state: If formula (6) is satisfied, that is, the values ​​of the 8 weight registers are 0 or less than the corresponding packet length register value, then a polling cycle ends. The weight register value is reset as shown in formula (7), the weight margin register value is updated to the reset weight register value, and the next polling cycle is entered, and then jumps to the delay guarantee queue polling state.

[0078] .

[0079] Delay guarantee queue polling status: Determine whether the delay guarantee queue FIFO is empty; if the delay guarantee queue FIFO is not empty, read the network packet descriptor in the FIFO, jump to the corresponding priority queue polling state according to the forwarding priority value in the network packet descriptor, and read the network packet of the corresponding length in the priority cache FIFO according to the packet length value in the network packet descriptor; if the delay guarantee queue FIFO is empty, Fig.15 The state jump diagram shown in the dequeue scheduling process jumps to maintain the polling order of each priority queue and maintain the service fairness of each priority queue.

[0080] Priority 7 queue polling status: If the network packet descriptor FIFO corresponding to the priority 7 queue is not empty and the weight is W 7[15:0]≥Packet length register L 7[15:0], then read the FIFO; then read the network packet of corresponding length from the priority 7 queue cache FIFO according to the packet length, and output it, and update the weight register according to formula (8) W 7[15:0], at this time, the weight margin register value WA 7[15:0] is equal to the updated W 7[15:0]; Determine whether the delay guarantee queue FIFO is empty. If the delay guarantee queue FIFO is not empty, jump to the delay guarantee queue output state; if the delay guarantee queue FIFO is empty, jump to the priority 6 queue polling state. If the network packet descriptor FIFO corresponding to the priority 7 queue is empty or W 7[15:0] < L 7[15:0], jump to the priority 6 queue polling state.

[0081] The above only takes the polling state of the priority 7 queue as an example. The polling states of other priority queues are similar to the polling state of the priority 7 queue, which will not be repeated here.

[0082] The dequeue scheduling method provided in the embodiment of the present application maintains a counter with an initial value of the weight for each queue. During each poll, the queue with a counter value other than 0 can be served, and the counter is reduced by 1. If the queue that is served is not empty, data is sent once. When all counters are 0, the counters are reset to the initial value of the weight, thus ensuring that each queue can be served, avoiding the "starvation" of low-priority queues, and being able to flexibly allocate the service time and bandwidth obtained by each priority queue by changing the initial value of the weight.

[0083] Combine the following Fig.16 The architecture shown introduces the priority queue scheduling method provided by the embodiment of the present application. Fig.16 , is a flow chart of a priority queue scheduling method provided in an embodiment of the present application, which can be executed by a network intermediate device, such as a switch or a router. The network intermediate device is provided with an input port buffer, and the input port buffer includes N logical queues. The method may include the following steps: S1601. Determine N logical queues included in the virtual input port cache, wherein each logical queue is used to cache data packets from the same input port, and each logical queue is composed of M sub-logical queues, and one sub-logical queue is used to store at least one network packet of a priority and a network packet descriptor of at least one network packet. N is the number of input ports, and M is the number of priority levels. The network packet descriptor includes the forwarding priority, packet length, and packet entry time of the network packet.

[0084] S1602 . For a first logical queue among the N logical queues, schedule each network packet according to the network packet descriptor of each network packet in the first logical queue, so as to store each network packet in sequence into a priority cache queue.

[0085] The network packets with different priorities in the first logical queue are scheduled independently. Taking the scheduling of the network packets in the first logical queue as an example, each network packet can be scheduled according to the network packet descriptor of each network packet in the first logical queue. For example, the network packet descriptor of each network packet in the first logical queue can be obtained, and the timing value corresponding to each network packet can be determined according to the packet entry time in the obtained network packet descriptor. t i ;in, t i satisfy: t i = t d – t s , t d is the maximum queue delay, t s The current reference time valuet r and network packet arrival time t m The time interval between t r Greater than or equal to t d ; According to the timing value corresponding to each network packet t i Determine the network packet with the shortest absolute deadline in the first logical queue, and then cache the network packet with the shortest absolute deadline in the priority cache queue. t r Generated by a maintained cyclic accumulation timer, and t s satisfy: .

[0086] If the processing time of the first network packet in the first logical queue is equal to the network packet guaranteed delay of the first network packet, the first network packet is stored in the delay guarantee queue; if the delay guarantee queue is not empty, the network packets in the delay guarantee queue are output; wherein, the network packets in the delay guarantee queue are scheduled first.

[0087] The first network packet may be stored in the delay guarantee queue according to the queue scheduling process. For example, the network packet descriptors of each network packet in the first logical queue may be obtained in order from high to low priority; the timing value may be determined according to the packet entry time in the network packet descriptor of each network packet and the current reference time; if the timing value is greater than the corresponding network packet guarantee delay, the network packet descriptor is read, and the obtained network packet descriptor and the corresponding network packet are stored in the delay guarantee queue.

[0088] If the delay guarantee queue is empty, then poll the network packets of each priority in the first logical queue; for the network packets of the first priority, determine whether to send the network packets of the first priority according to the packet length of the network packets of the first priority and the weight of the output data length; wherein, if the packet length of the network packets of the first priority is less than or equal to the weight of the output data length, then send the network packets of the first priority. After polling the first logical queue, update the weight of the output data length corresponding to each priority queue in the first logical queue, wherein the updated weight of the output data length is the remaining output data length of each priority queue at the end of the previous round of scheduling.

[0089] Fig.16 The method shown can be specifically referred to the aforementioned related content, and the repeated content will not be repeated here.

[0090] The following describes the device used to implement the above method in the embodiment of the present application in conjunction with the accompanying drawings. Therefore, the above content can be used in subsequent embodiments, and the repeated content will not be repeated.

[0091] The embodiment of the present application also provides an electronic device that implements the functions of the above-mentioned various method embodiments. The electronic device includes at least a processing module and a memory, etc. Among them, the memory is provided with an input port cache for storing received network packets. The processing module can be used to: determine the N logical queues included in the input port cache, and for the first logical queue among the N logical queues, schedule the respective network packets according to the network packet descriptors of the respective network packets in the first logical queue, so as to store the respective network packets in the priority cache queue in sequence; Among them, each logical queue is used to cache data packets from the same input port, and each logical queue is composed of M sub-logical queues, one of the sub-logical queues is used to store at least one network packet of a priority and the network packet descriptor of the at least one network packet, the network packet descriptor includes the forwarding priority, packet length and packet entry time of the network packet, N is the number of input ports, and M is the level of priority.

[0092] In a possible implementation, network packets of different priorities in the first logical queue are independently stored in the priority cache queue.

[0093] In a possible implementation, the processing module is used to schedule each network packet according to the network packet descriptor of each network packet in the first logical queue, including: Obtain the network packet descriptor of each network packet in the first logical queue, and determine the timing value corresponding to each network packet according to the packet entry time in the obtained network packet descriptor t i ;in, t i satisfy: t i = t d – t s , t d is the maximum queue delay, t s The current reference time value t r and network packet arrival time t m The time interval between t r Greater than or equal to t d ; According to the timing value corresponding to each network packett i Determining a network packet with the shortest absolute deadline in the first logical queue; Cache the network packets with the shortest absolute deadline into the priority cache queue.

[0094] In a possible implementation, t r Generated by a maintained cyclic accumulation timer, and t s satisfy: .

[0095] In a possible implementation, the processing module is further used for: If the processing time of the first network packet in the first logical queue is greater than or equal to the guaranteed network packet delay of the first network packet, the descriptor of the first network packet is stored in the delay guarantee queue; wherein the network packets in the delay guarantee queue are scheduled first; If the delay guarantee queue is not empty, the network packet corresponding to the network packet descriptor in the delay guarantee queue is output.

[0096] In a possible implementation, the processing module is used to store the first network packet in the delay guarantee queue, including: Obtaining the network packet descriptor of each network packet in the first logical queue in order from high to low priority; Determine a timing value according to a packet entry time in a network packet descriptor of each network packet and a current reference time; If the timing value is greater than the corresponding network packet guaranteed delay, the network packet descriptor is read and the obtained network packet descriptor is stored in the delay guarantee queue.

[0097] In a possible implementation, the processing module is further used for: If the delay guarantee queue is empty, poll the network packets of each priority in the first logical queue; For the first-priority network packet, whether to send the first-priority network packet is determined based on the packet length of the first-priority network packet and the weight of the exportable data length; wherein, if the packet length of the first-priority network packet is less than or equal to the weight of the exportable data length, the first-priority network packet is sent.

[0098] In a possible implementation, the processing module is further used for: After polling the first logical queue, the initial value of the output data length weight corresponding to each priority queue in the first logical queue is updated, wherein the updated initial value of the output data length weight is the remaining output data length of each priority queue at the end of the previous round of scheduling.

[0099] A computer-readable storage medium is also provided in an embodiment of the present application, including instructions, which, when executed on a computer, enable the computer to execute the method in the above method example. Please refer to the detailed description in the method example for details, which will not be repeated here.

[0100] The term "plurality" in the embodiments of the present application refers to two or more. The term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0101] "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0102] Furthermore, unless otherwise specified, ordinal numbers such as "first" and "second" mentioned in the embodiments of the present application are used to distinguish multiple objects and are not used to limit the size, content, order, timing, priority or importance of multiple objects.

[0103] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)), etc.

[0104] The various illustrative logic units and circuits described in the embodiments of the present application can be implemented or operated by a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, or any combination of the above. The general-purpose processor can be a microprocessor, and optionally, the general-purpose processor can also be any conventional processor, controller, microcontroller or state machine. The processor can also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0105] The steps of the method or algorithm described in the embodiments of the present application can be directly embedded in the software unit executed by the hardware, the processor, or a combination of the two. The software unit can be stored in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM or other storage media of any form in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from the storage medium and can write information to the storage medium. Alternatively, the storage medium can also be integrated into the processor. The processor and the storage medium can be arranged in an ASIC.

[0106] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0107] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0108] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0109] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0110] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0111] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A priority queue scheduling method, characterized in that: Applied to a network intermediate device, the output port of the network intermediate device is provided with a virtual input port cache, the method comprising: Determine N logical queues included in the virtual input port cache, wherein each logical queue is used to cache data packets from the same input port, and each logical queue is composed of M sub-logical queues, one of the sub-logical queues is used to store at least one network packet of the same priority and a network packet descriptor of each of the at least one network packet, network packets of different priorities in the first logical queue are independently stored in the priority cache queue, the network packet descriptor includes the forwarding priority, packet length and packet entry time of the network packet, N is the number of input ports, and M is the number of priority levels; For the first logical queue among the N logical queues, the network intermediate device schedules each network packet according to the network packet descriptor of each network packet in the first logical queue, so as to store each network packet in the priority cache queue in sequence.

2. The method according to claim 1, characterized in that The network intermediate device schedules each network packet according to the network packet descriptor of each network packet in the first logical queue, including: Obtaining a network packet descriptor for each network packet in the first logical queue, and determining a timing value corresponding to each network packet according to the packet entry time in the obtained network packet descriptor t i ; wherein said t i satisfy: t i = t d – t s , t d is the maximum queue delay, t s The current reference time value t r and network packet arrival time t m The time interval between t r Greater than or equal to t d ; According to the timing value corresponding to each network packet t i Determining a network packet with the shortest absolute deadline in the first logical queue; The network packet with the shortest absolute deadline is cached in the priority cache queue.

3. The method according to claim 2, characterized in that Said t r Generated by the maintained cycle accumulation timer, and the t s satisfy: 。 4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: If the processing time of the first network packet in the first logical queue is greater than or equal to the guaranteed network packet delay of the first network packet, the descriptor of the first network packet is stored in the delay guarantee queue; wherein the network packets in the delay guarantee queue are scheduled first; If the delay guarantee queue is not empty, the network packet corresponding to the network packet descriptor in the delay guarantee queue is output.

5. The method according to claim 4, characterized in that The guaranteed delay of the first network packet is the guaranteed delay of the queue where the first network packet is located, wherein the guaranteed delay of the queue is (pre-)set, and the guaranteed delays of queues with different priorities are different.

6. The method according to claim 4, characterized in that Storing the first network packet in a delay guarantee queue includes: Obtaining the network packet descriptor of each network packet in the first logical queue in order from high to low priority; Determine a timing value according to a packet entry time in a network packet descriptor of each network packet and a current reference time; If the timing value is greater than the corresponding guaranteed delay of the network packet, the network packet descriptor is read, and the obtained network packet descriptor is stored in the delay guarantee queue.

7. The method according to claim 4, characterized in that The method further comprises: If the delay guarantee queue is empty, polling the network packets of each priority in the first logical queue; For a network packet of the first priority, whether to send the network packet of the first priority is determined based on the packet length of the network packet of the first priority and the weight of the exportable data length; wherein, if the packet length of the network packet of the first priority is less than or equal to the weight of the exportable data length, the network packet of the first priority is sent.

8. The method according to claim 7, characterized in that The method further comprises: After polling the first logical queue, the initial value of the output data length weight corresponding to each priority queue in the first logical queue is updated, wherein the initial value of the updated output data length weight is the remaining output data length of each priority queue at the end of the previous round of scheduling.

9. An electronic device, characterized in that: include: A memory, provided with an input port buffer, for storing received network packets; The processing module is used to: determine N logical queues included in the input port cache, and for a first logical queue among the N logical queues, schedule each network packet according to a network packet descriptor of each network packet in the first logical queue, so as to store each network packet in the priority cache queue in sequence; Among them, each logical queue is used to cache data packets from the same input port, and each logical queue is composed of M sub-logical queues, one of the sub-logical queues is used to store at least one network packet of the same priority and the network packet descriptor of each of the at least one network packet, and the network packets of different priorities in the first logical queue are independently stored in the priority cache queue, and the network packet descriptor includes the forwarding priority, packet length and packet entry time of the network packet, N is the number of input ports, and M is the number of priority levels.

10. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory is used to store computer programs or instructions. When the processor executes the computer program or instructions, the electronic device executes the method as described in any one of claims 1 to 8.

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