FPGA-based data plane state programmable system and switch

Abstract

The application provides a data plane state programmable system and a switch based on FPGA, which comprises a matching action table pipeline with multiple levels; the pipeline comprises multiple ordered matching action table modules, which are used to realize different data plane processing and forwarding algorithms according to read configuration instructions in combination with flow state matching tables and conditional branch matching tables; the matching action table module comprises: a key value extraction module used to form a key value to be matched; a flow state query module used to match the key value to be matched to obtain flow address information and read corresponding flow state information; a packet header vector emission queue used to take the flow state address in the flow state information as an identifier and dynamically schedule the packet header vector to emit in disorder according to the flow state address and a dependency relationship; an action module used to determine the data plane processing and forwarding algorithm according to the configuration instruction to process, update the flow state information and table state information; and a packet header vector reordering cache module used to store the executed packet header vector and submit the packet header vector in disorder in order.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of FPGA and network packet processing, and particularly relates to a data plane state programmable system and switch based on FPGA. BACKGROUND

[0002] With the rapid development of the Internet, the traffic size in the network is growing exponentially, which poses great challenges to the performance of switching devices. Current switching device architectures mainly fall into three categories: architectures based on special network card chips, architectures based on general-purpose processors, and architectures based on FPGAs. In recent years, as the network size continues to expand, general-purpose processors are difficult to support the data packet line-speed forwarding requirement in high-speed networks. FPGA, as a compromise between general-purpose processors and special-purpose chips, is widely used in high-speed networks due to its programmability and high performance.

[0003] In traditional network devices, network devices such as routers and switches use data plane and control plane algorithms to process data packets. Users can configure control plane functions and protocols, but the underlying algorithms can only be changed by operators. In software-defined networks (SDN), users can deploy their custom algorithms in network devices. Forwarding devices with programmable data planes provide an implementation of user programmable functions. They use the "match-action" paradigm, and users can define protocol field processing methods and forwarding behaviors through programmable data planes.

[0004] The data plane in traditional SDN is a stateless data plane, and its network state information is completely managed by the controller. The data plane is only responsible for forwarding functions.

[0005] The related patent application "Packet programmable state set (publication number: CN111771358A)" proposes a network device containing a state set memory, which retains flow state information of data packets passing through the network device. The network device interacts with the state set to control the processing performed on the flow of the above data packets. The patent method implements packet processing and state set management functions based on the general-purpose processor of a computer, and the packet processing delay is large. The related published paper "Open Packet Processor" proposes a hardware-implementable extended state machine model to deploy a state data plane on hardware. The problem with the above method is that it does not consider the consistency of flow state information. SUMMARY

[0006] The present application aims to overcome the defects of the prior art and proposes a data plane state programmable system and switch based on FPGA.

[0007] An FPGA-based data plane state programmable system, the system comprising a matching action table pipeline with multiple stages;

[0008] The matching action table pipeline with multiple stages comprises a plurality of ordered matching action table modules, each matching action table module being configured to implement different data plane processing forwarding algorithms in combination with a flow state matching table and a conditional branch matching table according to read configuration instructions; wherein the matching action table module comprises:

[0009] A key value extraction module configured to extract fields from a packet header vector, global state and / or table state information according to the issued instructions to form a matching key value;

[0010] A flow state query module configured to match the packet flow address information from the flow state matching table according to the matching key value, and read the corresponding flow state information according to the address;

[0011] A packet header vector transmission queue configured to dynamically schedule the packet header vector according to the flow state address and the dependency relationship to perform out-of-order transmission with the flow state address in the flow state information as an identifier;

[0012] An action module configured to determine a custom data plane processing forwarding algorithm through the conditional branch matching table according to the read configuration instructions, process the flow state information corresponding to the out-of-order transmitted packet header vector, and update the flow state information and the table state information; and

[0013] A packet header vector reordering cache module configured to store the executed packet header vector and submit the out-of-order packet header vector in order.

[0014] Preferably, the output of each matching action table module can serve as the input of the subsequent matching action table module.

[0015] Preferably, the flow state matching table is a ternary content addressable memory matching table, a hash matching table or a longest prefix matching table.

[0016] Preferably, the packet header vector transmission queue comprises:

[0017] A score board configured to record the read and write back operations of the flow state, and determine whether the flow state of the packet header vector entering the packet header vector transmission queue depends on the write back results of other to-be-executed packet header vectors;

[0018] The packet header vector transmission queue is configured to cache the input packet header vector into an idle table item;

[0019] A selection logic configured to select a longest time packet header vector with ready flow state information from the packet header vector transmission queue into the action module at each clock cycle, while the packet header vector with unready flow state information continues to wait.

[0020] Preferably, the configuration instruction adopts a very long instruction word structure, and encapsulates multiple data-independent instructions into one very long instruction word.

[0021] Preferably, the action module comprises a conditional branch judgment sub-module, a state updating sub-module and a packet header vector action sub-module, wherein,

[0022] The conditional branch judgment sub-module is configured to select fields from the packet header vector and the state information according to the configuration instruction, input the fields into a plurality of parallel arithmetic logic units supporting very long instruction words for computing comparison results, and determine corresponding specific data plane processing forwarding algorithms in a conditional branch matching table according to the comparison results.

[0023] The state updating sub-module is configured to update the state information according to the configuration instruction.

[0024] The packet header vector action sub-module is configured to modify the packet header vector.

[0025] In another aspect, the application provides a switch comprising the FPGA-based data plane state programmable system.

[0026] Compared with the prior art, the application has the following advantages:

[0027] 1. The state data plane in the application allows network applications to store part of network state information in the data plane, adopts a "match-state-action" paradigm, and highlights programmability in the overall design of the module, so that user-defined algorithms can be realized by issuing configuration instructions, and dynamic network applications can be deployed, and appropriate data packet forwarding strategies can be selected in real time according to the state information in the data plane.

[0028] 2. Compared with the stateless data plane of the traditional SDN, the state data plane allows network applications to store part of network state information in the data plane, reduces the interaction between the data plane and the control plane, and can realize more dynamic network functions.

[0029] 3. Flexibility: the data plane function can be quickly changed, and new protocols can be quickly deployed.

[0030] 4. High performance: the packet header vector can be processed in parallel at the flow level, and line-speed processing and flow state consistency can be guaranteed.

[0031] 5. The packet header vector is dynamically scheduled according to the flow state address and the dependency relationship, which significantly improves the data packet processing speed while guaranteeing the state consistency.

[0032] 6. Based on FPGA deployment, it has the advantages of low delay and low power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a general framework diagram of the FPGA-based data plane state programmable system of the present application;

[0034] Figure 2 is a matching action module architecture diagram in Figure 1

[0035] Figure 3 is a packet header vector emission queue architecture diagram in Figure 2

[0036] Figure 4 is a conditional branch judgment submodule architecture diagram;

[0037] Figure 5 is a state programmable data plane flowchart;

[0038] Figure 6 is an arithmetic logic unit architecture diagram. DETAILED DESCRIPTION

[0039] The present application aims at the needs of supporting packet processing based on state information and the needs of programmable flexibility in FPGA programmable switching chips, and proposes a FPGA-based data plane state programmable system. As shown in Figure 1 The system includes a multi-stage matching action table pipeline; the multi-stage matching action table pipeline includes a plurality of ordered matching action table modules, each matching action table module being configured to implement different data plane processing forwarding algorithms in combination with a flow state matching table and a conditional branch matching table according to a read configuration instruction. As shown in Figure 2 The system includes a multi-stage matching action table pipeline; the multi-stage matching action table pipeline includes a plurality of ordered matching action table modules, each matching action table module being configured to implement different data plane processing forwarding algorithms in combination with a flow state matching table and a conditional branch matching table according to a read configuration instruction. As shown in

[0040] A key value extraction module is configured to extract fields from a packet header vector, global state and / or table state information according to an issued instruction to form a matching key value;

[0041] A flow state query module is configured to match a flow address information of a packet from a flow state matching table according to the matching key value, and read corresponding flow state information according to the address;

[0042] A packet header vector emission queue is configured to dynamically schedule packet header vectors according to flow state addresses and dependency relationships to emit the packet header vectors in a disordered manner with the flow state addresses as identifiers;

[0043] An action module is configured to determine a custom data plane processing forwarding algorithm through a conditional branch matching table according to a read configuration instruction, process flow state information corresponding to the disordered emitted packet header vectors, and update the flow state information and table state information; and

[0044] ​​The packet header vector reordering buffer module is configured to store the executed packet header vector and submit the out-of-order packet header vector in order.

[0045] The programmable key value extraction module is configured to extract the fields from the packet header vector, the global state and the table state according to the issued instruction to form the key value to be matched.

[0046] The matching table is configured to be a ternary content address memory (TCAM) matching table, a hash matching table or a longest prefix matching table, and is configured to match the address information of the flow to which the packet belongs according to the input key value, and read the corresponding flow state information according to the address.

[0047] The flow state storage module is configured to read the flow state information in the storage module according to the input address information.

[0048] The packet header vector launch queue is configured to schedule the adjacent packet header vectors belonging to the same flow ID in the launch queue according to the dependence relationship of the flow state of the packet header vector, and block the packet header vectors with flow state dependence relationship. Figure 3

[0049] The action module is composed of a conditional branch judgment submodule, a state update submodule and a packet header vector action submodule.

[0050] The conditional branch judgment submodule is configured to select the fields from the packet header vector and the state information according to the issued instruction, and input the fields into a plurality of parallel execution arithmetic logic units supporting very long instruction word (VLIW) to calculate and compare the results. Figure 4 is a structural framework diagram of the conditional branch judgment submodule.

[0051] ​The implementation steps of the state update submodule and the header vector action submodule are as follows: according to the read-out very long instruction word from the instruction storage module, the current header vector and the modification update instruction of the state information are determined. The arithmetic logic unit modifies the header vector and updates the state value according to the instruction.

[0052] The above-mentioned very long instruction word is a kind of instruction highly parallel computer instruction set architecture. A plurality of unrelated instructions are packaged to form a very long instruction word. The processor supporting the very long instruction word is composed of a plurality of independent functional components. The structure simplifies the hardware design and has strong data processing capacity.

[0053] The implementation steps of the reordering buffer are as follows: the reordering buffer stores the completed header vector of the pipeline execution, writes to the corresponding address of the queue according to the ROB ID, and submits the out-of-order header vector in order.

[0054] Figure 5 It is a state programmable data plane flow chart.

[0055] The technical solutions of the present application will be described in detail below in combination with the drawings and embodiments.

[0056] Embodiment 1

[0057] Embodiment 1 of the present application proposes a FPGA-based data plane state programmable system to realize the statistical TCP retransmission data packet quantity and the weighted round robin scheduling (Weighted Round Robin) algorithm, for example, and specific instructions are given. If other custom algorithms are to be realized, they can be designed according to this principle.

[0058] The number of TCP retransmission data packets is calculated, and the implementation principle of the algorithm is as follows: for a plurality of sequentially arrived data packets belonging to the same flow, whether the data packet is a retransmission data packet is determined by the seq sequence number in the TCP data packet and the latest valid seq sequence number of the flow. If the current received data packet seq sequence number is the same as or smaller than the latest data packet seq number recorded by the module, the received data packet is determined to be a retransmission data packet. The flow state variable Num is used to record the number of retransmission data packets of a flow.

[0059] The implementation method of the algorithm in the application is to configure the corresponding instructions and table entries of the data plane state programmable module components in turn: programmable key value extraction module, matching table, state storage module, programmable condition judgment module, and state update module. First, the programmable key value extraction module will issue instructions to extract the five-tuple (source IP address, destination IP address, source port number, destination port number, protocol number) from the packet header vector to form the Key to be matched. The flow matching table and the flow state storage module together constitute the flow state matching table as shown below. The flow matching table matches the key value to obtain the flow state address, which is used to read the flow state information (R0, R1) from the storage module, which are respectively: the retransmission packet cumulative number of the flow to which the packet belongs flow i .Num; sequence number flow i .Seq, as shown in Table 1 below.

[0060] Table 1 Calculation of TCP retransmission packet number-flow state matching table

[0061]

[0062] In the condition judgment module, the state information and the comparison judgment result are input as matching fields. In this application, according to the module issued instructions, the size relationship between the seq sequence number of the current TCP packet and the maximum seq sequence number of the flow is judged, and the judgment result C i (indicating the size relationship between the packet seq number and the flow seq number) is output. Enter the ternary content addressable memory (TCAM) matching table as shown in Table 2 below, match the corresponding condition branch, get the instruction block address corresponding to the condition branch, and read the very long instruction word from the instruction storage module according to the address. In Table 2, Key corresponds to the condition branch to be matched, and Value corresponds to the instruction block obtained by matching.

[0063] Table 2 Calculation of TCP retransmission packet number-condition branch matching table

[0064]

[0065] The state update and action arithmetic logic unit executes the corresponding instructions for updating the state information and modifying the packet header vector according to the very long instruction word read from the instruction storage module. In the current application of calculating the TCP retransmission data packet number, the seq sequence number of the flow (flow i .Seq) or the retransmission packet number (flow i .Num) is updated according to the condition branch judgment result.

[0066] Embodiment 2

[0067] Embodiment 2 of the application proposes a data plane state programmable system based on FPGA to implement the weighted round-robin scheduling algorithm.

[0068] Weighted round robin scheduling belongs to load balancing algorithm, the implementation principle of which is: polling on the current node's selectable path weight set. The arriving data packet will select the path corresponding to the current weight, and after selecting the path, the current weight will be reduced by 1. Until the current weight value is reduced to 0, the initial weight value is restored, and then jump to the next selectable path. The above process is executed again until the current selected path weight value is reduced to 0 and the initial weight value is restored, and then jump to the next selectable path.

[0069] The application of 8 selectable path weights will be taken as an example below to illustrate the corresponding instruction configuration and matching action table entry issuing of the data plane state programmable module. The table state storage module of the data plane issues information that the current node's selectable path set is {path[0], path[1], …, path[7]}, the initial weight value of each path of the current node is {init[0], init[1], …, init[7]}, and each packet header vector entering the matching action table can obtain the above table state information.

[0070] The programmable key value extraction module extracts the selectable path set of the table state information and the corresponding fields of the packet header vector according to the issued instruction to generate the data packet's selectable path subset mask of the current node as the input query key value of the flow state matching table.

[0071] In the flow state matching table shown in Table 3 below, the variables {w0, w1, …, w7} represent the current weight values of the 8 selectable paths of the flow, the variables {nxt_w0, nxt_w1, …, nxt_w7} represent the next-hop selectable path sequence numbers of the current path, the index value domain is 0 to 7, and represents the current selectable path sequence number of the flow. The matching table can indicate the path sequence number and the path weight value of the current flow and other flow state information.

[0072] Table 3 Weighted round robin scheduling-flow state matching table

[0073]

[0074]

[0075] In the conditional branch judgment module, the state can be used as a matching domain or as an input of an arithmetic logic unit. The module judges whether the current weight value has enough remaining according to the issued instruction. If the current weight value is greater than 1, the current path is selected, otherwise, the next selectable path is jumped to: (the corresponding state update operation index = nxt_w index). The key value generated by the module enters a ternary content addressable memory (TCAM) conditional branch matching table shown in Table 4 below, matches the corresponding conditional branch, obtains the instruction block address of the corresponding conditional branch, and reads the very long instruction word from the instruction storage module according to the address.

[0076] Table 4 Weighted Round Robin Scheduling-Conditional Branch Matching Table

[0077]

[0078]

[0079] The state update and action module performs corresponding operations of updating state information and modifying the packet header vector according to the very long instruction word read out by the instruction storage module. In the current weighted round robin scheduling application, the module updates the weight value (W i ) of the flow to which the data packet belongs and the index, and modifies the corresponding indication path field in the packet header vector.

[0080] The conditional branch judgment module and the state update and action module are composed of a plurality of parallel basic arithmetic logic units, and the overall architecture of the arithmetic logic unit is shown in Figure 6 , the input is: 2-way 32-bit wide operands op rand0, op rand1, and 32-bit wide instructions, and the output is 32-bit result calculation result. The arithmetic logic unit supports 32-bit, 16-bit, and 8-bit wide operations and comparison operations. Figure 6 The variable suffixes B3, B2, B1, B0, H1, H0, and W in the above table respectively represent 8-bit, 16-bit, and 32-bit inputs, and the relative positions in the 32-bit input width. The arithmetic logic unit supports selecting the relative addresses of input and output data (such as result.B3 = op rand0.B0 + op rand1.B2, the input data address and the specified output data address can be selected by instructions), and has good programmability and flexibility.

[0081] It should be noted that the above two embodiments are only for illustrating how the system is implemented in combination with specific data forwarding algorithms, and are not limited to the above algorithms.

[0082] Embodiment 3

[0083] The embodiment of the application proposes a switch having the system of the embodiment 1 or the embodiment 2.

[0084] The above detailed description of the specific embodiments of the present application has been given to understand the objectives, technical solutions, and advantages of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A data plane state programmable system based on FPGA, characterized in that, The system includes a multi-level matching action table pipeline; The multi-level matching action table pipeline includes multiple ordered matching action table modules. Each matching action table module is used to implement different data plane processing and forwarding algorithms based on the read configuration instructions, combined with the flow state matching table and the conditional branch matching table. The matching action table module includes: The key-value extraction module is used to extract fields from the packet header vector, global status and / or table status information according to the issued instructions, and to form the key-value pair to be matched. The flow status query module is used to match the flow status matching table to obtain the flow address information to which the packet belongs based on the key value to be matched, and to read the corresponding flow status information using this address; The packet header vector emission queue is used to dynamically schedule packet header vectors for out-of-order emission based on the flow state address in the flow state information and the dependency relationship. The action module, based on the read configuration instructions, determines a custom data plane processing and forwarding algorithm through a conditional branch matching table, processes the flow state information corresponding to the out-of-order packet header vector, and updates the flow state information and table state information; and The packet header vector reordering cache module is used to store the packet header vectors after execution and submit the disordered packet header vectors in order.

2. The FPGA-based data plane state programmable system according to claim 1, characterized in that, The output of each matching action table module can be used as the input of the subsequent matching action table module.

3. The FPGA-based data plane state programmable system according to claim 1, characterized in that, The stream state matching table is a tri-state content-addressable memory matching table, a hash matching table, or a longest prefix matching table.

4. The FPGA-based data plane state programmable system according to claim 1, characterized in that, The packet header vector transmission queue includes: The scoreboard is used to record the read and write operations of the stream state, and to determine whether the stream state of the header vector entering the header vector emission queue depends on the write-back results of other header vectors to be executed. The packet header vector emission queue is used to buffer the input packet header vectors into free entries. The selection logic is used to select the longest-running packet header vector with ready stream status information from the packet header vector transmission queue and transmit it to the action module every clock cycle, while packet header vectors with unread stream status information continue to wait.

5. The FPGA-based data plane state programmable system according to claim 1, characterized in that, The configuration instructions adopt an ultra-long instruction word structure, which encapsulates multiple instructions with no data dependency into a single ultra-long instruction word.

6. The FPGA-based data plane state programmable system according to claim 5, characterized in that, The action module includes a conditional branch judgment submodule, a state update submodule, and a packet header vector action submodule, wherein... The conditional branch judgment submodule is used to select fields from the packet header vector and state information according to the configuration instructions, input them into several parallel arithmetic logic units that support very long instruction words for calculating comparison results, and determine the corresponding specific data plane processing and forwarding algorithm in the conditional branch matching table according to the comparison results. The status update submodule is used to update status information according to configuration instructions; The packet header vector action submodule is used to modify the packet header vector.

7. A switch, characterized in that, Includes the FPGA-based data plane state programmable system as described in any one of claims 1-6.

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