Vertical synchronization signal synchronization processing methods, devices and electronic equipment

Abstract

This invention discloses a method, apparatus, and electronic device for processing vertical synchronization signals. The apparatus includes a system chip, a timeout timer, a base timer, and a capture timer. The method includes: outputting a second vertical synchronization signal following a first vertical synchronization signal output by the system chip, and detecting the frequency of the first vertical synchronization signal using the timeout timer and the capture timer; if the frequency of the first vertical synchronization signal is detected to be higher or lower, stopping the output of the second vertical synchronization signal following the system chip, and generating a signal as the second vertical synchronization signal by adjusting the timeout interrupt of the timeout timer; after detecting that the frequency of the first vertical synchronization signal is stable, calculating a preset time using the base timer, and synchronizing the second vertical synchronization signal with the first vertical synchronization signal on the rising edge at the preset time. This invention enables different solutions to use the same processing method to solve the problem of backlight flickering when synchronizing the vertical synchronization signal output by the system chip in the driving circuit.

Description

Technical Field

[0001] This invention relates to the field of vertical synchronization signal processing, and more particularly to a method, apparatus, and electronic device for vertical synchronization signal processing. Background Technology

[0002] Vertical synchronization (VSYNC) signal is used to synchronously update backlight brightness information during frame switching. It can synchronize backlight and LCD flipping, and even further enhance black frame insertion, thus improving image quality to some extent caused by LCD flipping. Synchronization refers to synchronizing the backlight's on / off state with the LCD flipping cycle. However, different manufacturers use different methods to handle changes in the vertical synchronization signal frequency, and different solutions cannot use the same method to avoid backlight flicker. Furthermore, even strictly synchronized solutions relying solely on hardware operation during changes can cause backlight flicker; while some maintain the original LED current, which prevents flicker, but the synchronization recovery process depends on customized solutions and cannot be applied to other chips or situations. Therefore, there is currently a lack of a universally applicable vertical synchronization signal processing method to avoid backlight flicker in various solutions. Summary of the Invention

[0003] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a vertical synchronization signal synchronization processing method, apparatus and electronic device, which aims to enable different solutions to use the same processing method to solve the problem of backlight flicker when the vertical synchronization signal output by the synchronization system chip in the driving circuit is displayed.

[0004] The technical solution of the present invention is as follows:

[0005] This invention provides a method for processing vertical synchronization signals, applied to a vertical synchronization signal processing device. The vertical synchronization signal processing device includes a system chip, a timeout timer, a basic timer, and a capture timer. The method includes the following steps:

[0006] The system chip outputs a second vertical synchronization signal following the first vertical synchronization signal, and the frequency of the first vertical synchronization signal is detected by a timeout timer and a capture timer.

[0007] If the frequency of the first vertical synchronization signal is detected to be higher or lower, the system chip stops outputting the second vertical synchronization signal and generates a signal as the second vertical synchronization signal by adjusting the timeout interrupt of the timeout timer.

[0008] After detecting that the frequency of the first vertical synchronization signal is stable, a preset time is calculated by the basic timer, and the second vertical synchronization signal is synchronized with the first vertical synchronization signal on the rising edge at the preset time.

[0009] Optionally, the step of detecting the frequency of the first vertical synchronization signal specifically includes:

[0010] The frequency of the vertical synchronization signal output by the system chip is detected by any one of the following: external interrupt mode of the input / output pin, timer capture mode of the capture timer, or timeout interrupt mode of the timeout timer.

[0011] Optionally, the step of generating the second vertical synchronization signal via a timeout interrupt of a timeout timer specifically includes:

[0012] The timeout interrupt time is changed by adjusting the reload value of the timeout timer, thereby changing the frequency of the vertical synchronization signal to generate a second vertical synchronization signal.

[0013] Optionally, the step of calculating a preset time using a base timer and synchronizing the second vertical synchronization signal with the first vertical synchronization signal at the preset time on the rising edge specifically includes:

[0014] The period after the frequency change of the second vertical synchronization signal is converted into the count value of the basic timer;

[0015] The preset time is calculated based on the count value of the base timer;

[0016] The count reached by the base timer at a preset time is converted into the reload value of the timeout timer. The reload value of the timeout timer is changed so that the rising edge of the second vertical synchronization signal starts to synchronize with the rising edge of the first vertical synchronization signal at a preset time.

[0017] Optionally, the vertical synchronization signal synchronization processing method further includes the following steps:

[0018] When the frequency of the first vertical synchronization signal is detected to be higher or lower, the frequency multiplication parameter under different timeout timer parameters is calculated, and the output frequency multiplication parameter is dynamically adjusted to keep the PWM frequency of the backlight current constant.

[0019] Optionally, after the step of synchronizing the second vertical synchronization signal at a preset time and the first vertical synchronization signal on the rising edge, the method further includes:

[0020] Transfer control of the input / output pins to the interrupt handler of the capture timer.

[0021] The present invention also proposes a vertical synchronization signal synchronization processing device based on the above-mentioned vertical synchronization signal synchronization processing method, including a controller, a system chip, a timeout timer, a basic timer and a capture timer. The controller is used to follow the first vertical synchronization signal output by the system chip to output a second vertical synchronization signal, and to detect the frequency of the first vertical synchronization signal through the timeout timer and the capture timer.

[0022] When the controller detects that the frequency of the first vertical synchronization signal becomes higher or lower, it stops following the system chip to output the second vertical synchronization signal and generates the second vertical synchronization signal by adjusting the timeout interrupt of the timeout timer.

[0023] After detecting that the frequency of the first vertical synchronization signal is stable, the controller calculates a preset time through the basic timer and synchronizes the second vertical synchronization signal with the first vertical synchronization signal on the rising edge at the preset time.

[0024] Optionally, the vertical synchronization signal synchronization processing device further includes:

[0025] A driving circuit is provided, the input terminal of which is connected to the output terminal of the controller. The output terminal of the driving circuit is used to connect to a light-emitting device. The controller is used to control the driving circuit to drive the light-emitting device to work.

[0026] Optionally, the vertical synchronization signal synchronization processing device further includes:

[0027] The memory is electrically connected to the controller and stores a vertical synchronization signal synchronization processing program. When the vertical synchronization signal synchronization processing program is executed by the controller, it implements the vertical synchronization signal synchronization processing method as described above.

[0028] The present invention also proposes an electronic device, including the vertical synchronization signal synchronization processing device as described above.

[0029] In this invention, a second vertical synchronization signal can be output following the first vertical synchronization signal output by the system chip. The frequency of the first vertical synchronization signal is detected using a timeout timer and a capture timer. When the frequency of the first vertical synchronization signal is detected to be higher or lower, the output of the second vertical synchronization signal following the system chip is stopped, and the second vertical synchronization signal is generated by adjusting the timeout interrupt of the timeout timer. After the frequency of the first vertical synchronization signal is detected to be stable, a preset time can be calculated using a base timer, and the second vertical synchronization signal is synchronized with the first vertical synchronization signal on the rising edge at the preset time. This ensures that the second vertical synchronization signal quickly adjusts to the same frequency as the first vertical synchronization signal after the frequency of the first vertical synchronization signal changes. This allows different solutions to use the same processing method to solve the backlight flickering problem when synchronizing the vertical synchronization signal output by the system chip in the drive circuit. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0031] Figure 1 This is a flowchart of the method steps of an embodiment of the vertical synchronization signal synchronization processing method of the present invention.

[0032] Figure 2 This is a flowchart of the method steps of another embodiment of the vertical synchronization signal synchronization processing method of the present invention.

[0033] Figure 3 This is a hardware circuit diagram of an embodiment of the vertical synchronization signal synchronization processing device of the present invention.

[0034] Figure 4 This is a software state machine transition diagram of an embodiment of the vertical synchronization signal synchronization processing device of the present invention.

[0035] Figure 5 This is a schematic diagram of the signal synchronization process when the vertical synchronization signal frequency changes from high to low and from low to high, according to an embodiment of the vertical synchronization signal synchronization processing device of the present invention.

[0036] Figure 6 This is a schematic diagram of the conventional vertical synchronization signal following process. Detailed Implementation

[0037] To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0038] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of the present invention involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0039] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any unit and all combinations of one or more associated listed items.

[0040] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0041] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0042] Vertical Synchronization (VSYNC) signals are used to synchronously update backlight brightness information during frame switching. They enable backlight and LCD flip-flopping synchronization, and even further enhance black frame insertion, mitigating image quality issues caused by LCD flip-flopping. However, different types of chips handle changes in the vertical synchronization signal frequency differently, which can cause backlight flicker. Even strictly synchronized solutions relying solely on hardware operation during changes can cause flicker; while some maintain the original LED current, preventing flicker, but restoring synchronization requires a custom solution and may not be applicable to other chips or situations.

[0043] Figure 6 In the current conventional vertical synchronization signal tracking process, SOC VSYNC is the vertical synchronization signal output by the system chip, and the driver's VSYNC is the vertical synchronization signal output by the controller. When the frequency of the vertical synchronization signal output by the system chip decreases, the processor will respond immediately in GPIO external interrupt mode. However, the parameters in the driver's registers have not yet been updated at the new vertical synchronization signal frequency. The period or number of cycles of the backlight current PWM waveform within this vertical synchronization signal cycle does not increase. Therefore, in the later stages, the current waveform is lost during the added time, and the backlight will flicker. This state lasts for two vertical synchronization signal cycles. The first time is the initial detection of a frequency change, and the second time is because after calculating the new data, for this hardware circuit, the data can only be updated at the rising edge of the next vertical synchronization signal, i.e., the third vertical synchronization signal.

[0044] When the frequency of the vertical synchronization signal output by the system chip increases, from Figure 6 Based on the demonstration, although the backlight current is not missing, the increased frequency and shorter period cause a segment where a PWM waveform should appear to be covered by the new vertical sync signal period, resulting in a low-frequency waveform different from the PWM frequency. This can cause slight flickering in the display in some cases. When using a timed-out interrupt to improve this, setting the timeout period appropriately based on the current stable vertical sync signal frequency output by the system chip can resolve the issue of a partial backlight current loss (after the timeout...). Figure 6 In the conventional vertical synchronization signal following process, the expected position of the vertical synchronization signal is slightly later (the processor actively sends the vertical synchronization signal). However, when the vertical synchronization signal output by the system chip stabilizes and the processor outputs the vertical synchronization signal again to attempt synchronization, the time interval between the vertical synchronization signal output by the processor last time and the vertical synchronization signal output by the system chip at the time of synchronization is random and cannot be reliably calculated.

[0045] To address the aforementioned problems, this invention proposes a vertical synchronization signal synchronization processing method, which is applied to a vertical synchronization signal synchronization processing device.

[0046] Reference Figure 1 In one embodiment, the vertical synchronization signal synchronization processing device includes a system chip, a timeout timer, a base timer, and a capture timer, and the vertical synchronization signal synchronization processing method includes the following steps:

[0047] S100: Following the first vertical synchronization signal output by the system chip, output the second vertical synchronization signal, and detect the frequency of the first vertical synchronization signal through a timeout timer and a capture timer;

[0048] S200. If the frequency of the first vertical synchronization signal is detected to be higher or lower, stop the follower system chip from outputting the second vertical synchronization signal, and use the timeout interrupt of the timeout timer as the second vertical synchronization signal.

[0049] S300: After detecting that the frequency of the first vertical synchronization signal is stable, calculate the preset time through the basic timer, and synchronize the second vertical synchronization signal with the first vertical synchronization signal on the rising edge at the preset time.

[0050] In this embodiment, following the first vertical synchronization signal output by the system chip allows for the output of a second vertical synchronization signal to synchronize data transmission with the image refresh cycle, thereby preventing data loss or misalignment and ensuring data consistency in each frame. However, the frequency of the first vertical synchronization signal may change during operation due to factors such as image resolution variations, frame rate adjustments, processing power changes, and software or firmware settings. Therefore, real-time detection of the first vertical synchronization signal's frequency is necessary to prevent video or image display desynchronization caused by differences in the frequency of the second vertical synchronization signal compared to the first. Detecting the frequency of the first vertical synchronization signal can be achieved using a timeout timer and a capture timer. For example, a capture timer can be configured to run at a higher frequency (significantly higher than the first vertical synchronization signal's frequency). When the capture timer captures the rising or falling edge of the first vertical synchronization signal, an interrupt is triggered. In the interrupt service routine, the period and frequency of the first vertical synchronization signal can be calculated by comparing the current capture time with the previous capture time. For the timeout timer, an overflow time close to the period of the first vertical synchronization signal can be set. When the timer overflows, it is considered that a first vertical synchronization signal has been missed, which can be used as an indirect detection of the frequency of the first vertical synchronization signal.

[0051] When the frequency of the first vertical synchronization signal is detected to increase or decrease, the output of the second vertical synchronization signal by the system chip can be stopped, and the timeout interrupt of the timeout timer can be adjusted to generate a new second vertical synchronization signal. It is understood that the second vertical synchronization signal generated by the timeout timer interrupt has the same parameters as the old second vertical synchronization signal and can be controlled, for example, by changing the reload value of the timeout timer. After the frequency of the first vertical synchronization signal is detected to be stable, a preset time can be calculated using the base timer, and the new second vertical synchronization signal output by the timeout timer can be synchronized with the first vertical synchronization signal on the rising edge at the preset time, thus completing the frequency synchronization of the second vertical synchronization signal and the first vertical synchronization signal after the frequency change. In this way, the frequencies of the first and second vertical synchronization signals remain the same, and the backlight flickering problem will not occur.

[0052] In this invention, a second vertical synchronization signal can be output following the first vertical synchronization signal output by the system chip. The frequency of the first vertical synchronization signal is detected using a timeout timer and a capture timer. When the frequency of the first vertical synchronization signal is detected to be higher or lower, the output of the second vertical synchronization signal following the system chip is stopped, and the second vertical synchronization signal is generated by adjusting the timeout interrupt of the timeout timer. After the frequency of the first vertical synchronization signal is detected to be stable, a preset time can be calculated using a base timer, and the second vertical synchronization signal is synchronized with the first vertical synchronization signal on the rising edge at the preset time. This ensures that the second vertical synchronization signal quickly adjusts to the same frequency as the first vertical synchronization signal after the frequency of the first vertical synchronization signal changes. This allows different solutions to use the same processing method to solve the backlight flickering problem when synchronizing the vertical synchronization signal output by the system chip in the drive circuit.

[0053] In one embodiment, the step of detecting the frequency of the first vertical synchronization signal specifically includes:

[0054] The frequency of the vertical synchronization signal output by the system chip is detected by any one of the following: external interrupt mode of the input / output pin, timer capture mode of the capture timer, or timeout interrupt mode of the timeout timer.

[0055] In this embodiment, the external interrupt mode is an interrupt triggered by external signals (such as button presses, sensor signals, etc.). External interrupts can be edge-triggered (rising or falling edge) or level-triggered (high or low level). External interrupt mode can respond to external events promptly, reducing the processor's polling burden and improving system response speed. The timing capture mode is typically used in conjunction with a timer to capture the state of an input signal at a specific time point. The timer can be configured to capture the state of the input signal (such as high or low level) within a specific time interval and store it in a register, which can then be used to measure the period of the vertical synchronization signal. The timeout interrupt mode generates an interrupt if a specific event does not occur within a specified time interval. Specifically, the timer counts within a set time; if the count reaches a preset value, a timeout interrupt is triggered. This can be used to detect whether an operation is completed within a specified time. These three interrupt modes can be selected and combined according to specific application requirements to achieve effective processing of various external events and timing operations.

[0056] In one embodiment, the step of generating a second vertical synchronization signal via a timeout interrupt of a timeout timer specifically includes:

[0057] The timeout interrupt time is changed by adjusting the reload value of the timeout timer, thereby changing the frequency of the vertical synchronization signal to generate a second vertical synchronization signal.

[0058] In this embodiment, the frequency of the second vertical synchronization signal can be changed by adjusting the reload value of the timeout timer to change the timeout interrupt time. For example, setting the timer's reload value to the desired new value will result in a longer timeout interrupt time, thereby reducing the frequency of the second vertical synchronization signal; while a smaller reload value will result in a shorter timeout interrupt time, increasing the frequency of the second vertical synchronization signal.

[0059] Reference Figure 2 In one embodiment, the step of calculating a preset time using a base timer and synchronizing the second vertical synchronization signal with the first vertical synchronization signal at the preset time on the rising edge specifically includes:

[0060] S310: Convert the period of the second vertical synchronization signal after frequency change into the count value of the basic timer;

[0061] S320. Calculate the preset time based on the count value of the basic timer;

[0062] S330. Convert the count reached by the basic timer at a preset time into the reload value of the timeout timer, and change the reload value of the timeout timer so that the rising edge of the second vertical synchronization signal starts to synchronize with the rising edge of the first vertical synchronization signal at a preset time.

[0063] In this embodiment, the preset time can be calculated. The preset time and the stable period after the change of the first vertical synchronization signal have a linear functional relationship. The period after the change of the first vertical synchronization signal can be converted into the count value of the base timer. Because there is a base timer count with the same time base and the clock frequency of each timer is also determined, by selecting a suitable time interval, the count that the base timer will reach at the preset time can be converted into the reload value required by the timeout timer. Then, by changing the reload value of the timeout timer, the second vertical synchronization signal can also be triggered at the preset time. Since the second vertical synchronization signal at each moment in this process is controlled by the timeout timer, by selecting an appropriate time to update the register value according to the characteristics of the driving scheme, it can be ensured that the current waveform fills each vertical synchronization signal cycle.

[0064] In one embodiment, the vertical synchronization signal synchronization processing method further includes the following steps:

[0065] When the frequency of the first vertical synchronization signal is detected to be higher or lower, the frequency multiplication parameter under different timeout timer parameters is calculated, and the output frequency multiplication parameter is dynamically adjusted to keep the PWM frequency of the backlight current constant.

[0066] In this embodiment, in practical applications, the PWM frequency is generally a multiple of the vertical synchronization signal. When the frequency of the first vertical synchronization signal changes, assuming no waveform loss, if the multiplication parameter at the driver end remains unchanged, the PWM frequency of the backlight current will also change. This may lead to observable changes in the display state under certain backlight conditions. Therefore, it is necessary to dynamically adjust this multiplication parameter, i.e., maintain the PWM frequency constant while ensuring that the PWM waveform can fill the entire vertical synchronization signal cycle. Therefore, in practical applications, the multiplication range supported by the driver scheme must be greater than or equal to the multiplication parameter within the required range of vertical synchronization signal frequency changes. As can be seen from the above, the second vertical synchronization signal is controllable and predictable during the signal synchronization period. Therefore, different timeout timer interrupt parameters, i.e., multiplication parameters at different second vertical synchronization signal frequencies, can be calculated during this period to maintain the PWM frequency of the backlight current constant.

[0067] In one embodiment, after the step of synchronizing the second vertical synchronization signal with the first vertical synchronization signal at a preset time and on the rising edge, the method further includes:

[0068] Transfer control of the input / output pins to the interrupt handler of the capture timer.

[0069] In this embodiment, by delegating control of the input / output pins to the interrupt handler, the microcontroller can respond immediately to signal changes. Furthermore, the interrupt handler can execute immediately upon signal arrival without waiting for polling by the main program. This significantly reduces system response latency and improves overall performance. Moreover, by using the interrupt handler, complex polling logic can be simplified. The microcontroller only needs to process the relevant event when an interrupt occurs, without continuously checking the state of the input / output pins, thus reducing the processor's burden. Centralizing control in the interrupt handler also reduces contention for the same input / output pins by multiple tasks, lowering potential conflicts and errors, and improving system stability and reliability. In this embodiment, delegating control of the input / output pins to the interrupt handler of the capture timer improves system response speed, efficiency, and stability, enabling the microcontroller to handle external events and signals more effectively.

[0070] The present invention also proposes a vertical synchronization signal synchronization processing device based on the above-mentioned vertical synchronization signal synchronization processing method.

[0071] In one embodiment, the vertical synchronization signal synchronization processing device includes a controller, a system chip, a timeout timer, a base timer, and a capture timer. The controller is used to output a second vertical synchronization signal following a first vertical synchronization signal output by the system chip, and to detect the frequency of the first vertical synchronization signal through the timeout timer and the capture timer.

[0072] When the controller detects that the frequency of the first vertical synchronization signal becomes higher or lower, it stops following the system chip to output the second vertical synchronization signal and generates the second vertical synchronization signal by adjusting the timeout interrupt of the timeout timer.

[0073] After detecting that the frequency of the first vertical synchronization signal is stable, the controller calculates a preset time through the basic timer and synchronizes the second vertical synchronization signal with the first vertical synchronization signal on the rising edge at the preset time.

[0074] In this embodiment, the controller can output a second vertical synchronization signal by following the first vertical synchronization signal output by the system chip. The frequency of the first vertical synchronization signal can be detected using a timeout timer and a capture timer. When the controller detects that the frequency of the first vertical synchronization signal has increased or decreased, it can stop following the system chip's output of the second vertical synchronization signal and adjust the timeout interrupt of the timeout timer to generate a new second vertical synchronization signal. It is understood that the second vertical synchronization signal generated in the timeout timer interrupt has the same parameters as the old second vertical synchronization signal and can be controlled; for example, the frequency of the second vertical synchronization signal can be changed by altering the timeout timer's reload value. After the controller detects that the frequency of the first vertical synchronization signal has stabilized, it can calculate a preset time using a base timer and synchronize the new second vertical synchronization signal output by the timeout timer with the first vertical synchronization signal on the rising edge at the preset time, thus completing the frequency synchronization of the second vertical synchronization signal and the first vertical synchronization signal after the frequency change. In this way, the frequencies of the first vertical synchronization signal output by the system chip and the second vertical synchronization signal output by the controller remain the same, preventing backlight flickering.

[0075] In one embodiment, the vertical synchronization signal synchronization processing device further includes:

[0076] A driving circuit is provided, the input terminal of which is connected to the output terminal of the controller. The output terminal of the driving circuit is used to connect to a light-emitting device. The controller is used to control the driving circuit to drive the light-emitting device to work.

[0077] In this embodiment, the driving circuit can be composed of transistors and driving chips, etc. The controller can control the driving circuit to drive the light-emitting device to work according to the second vertical synchronization signal to display the backlight. The hardware design of the vertical synchronization signal synchronization processing device is as follows: Figure 3 Specifically, it can be composed of a controller, a driver section, and an external MOS. The controller can be a 32-bit GD32F330C8T6, the driver chip can be a TC018 chip, and the external MOS can be flexibly adjusted according to the backlight current. Other chips with similar functions can also be used. The software design of the vertical synchronization signal processing device uses finite state machine programming, divided into normal operation mode and a phased synchronization process of the first vertical synchronization signal output by the system chip in timer interrupts. For details, please refer to [reference needed]. Figure 4 State machine transition diagram and Figure 5 Diagram of the vertical synchronization signal synchronization process. Figure 4 For t0 to t8, please refer to Figure 5 .

[0078] In one embodiment, the vertical synchronization signal synchronization processing device further includes:

[0079] The memory is electrically connected to the controller and stores a vertical synchronization signal synchronization processing program. When the vertical synchronization signal synchronization processing program is executed by the controller, it implements the vertical synchronization signal synchronization processing method as described above.

[0080] In this embodiment, the memory is a memory component that can be used to store programs and various data information, such as RAM or ROM. Storing the vertical synchronization signal synchronization processing program in the memory allows the controller to read the vertical synchronization signal synchronization processing program, thereby combining it with other peripheral devices and circuits such as the system chip, timeout timer, basic timer, capture timer, and drive circuit to realize the above-mentioned vertical synchronization signal synchronization processing method.

[0081] To better illustrate the technical concept of this invention, combined with Figures 1 to 5 The workflow of this invention will be described as follows:

[0082] When the capture timer detects that the frequency of the first vertical synchronization signal has increased, or the timeout timer detects that the frequency of the first vertical synchronization signal has decreased, the second vertical synchronization signal output by the controller will no longer follow the first vertical synchronization signal. Instead, a new second vertical synchronization signal, consistent with the old parameters, will be generated by the controller driver during the timeout timer interrupt. This new second vertical synchronization signal is controllable; its frequency can be changed by altering the timeout timer reload value. After the frequency of the first vertical synchronization signal output by the system chip stabilizes, the new second vertical synchronization signal will synchronize with the first vertical synchronization signal on the rising edge at a preset time. Then, the control authority of the corresponding GPIO on the controller side will gradually be transferred to the interrupt handler of the capture timer. The preset time can be calculated; the specific preset time can be found in [reference needed]. Figure 5 . Figure 5 The upper part of the diagram shows the synchronization process of the second vertical synchronization signal when the frequency of the first vertical synchronization signal decreases, and the lower part shows the synchronization process of the second vertical synchronization signal when the frequency of the first vertical synchronization signal increases. Taking the synchronization process of the second vertical synchronization signal when the frequency of the first vertical synchronization signal decreases as an example, SOC VSYNC is the first vertical synchronization signal output by the system chip, the driver VSYNC is the second vertical synchronization signal output by the controller, t0 is the period Tnew of the first vertical synchronization signal calculated by the capture timer after the frequency of the first vertical synchronization signal stabilizes, t1 is the time base data cnt1 of the base timer, t2 is the time base data cnt2 of the base timer, and t5 and t4 are calculated at time t2. The formula for calculating t5 can be referred to as follows:

[0083] timer_cnt(t5)=cnt1+timer_cnt(Tnew)*n&&t5-t3>time_limit, timer_cnt(t3)=cnt2+timer1_reload;

[0084] Where timer_cnt(t5) represents t5, the preset time; timer_cnt(Tnew) is the period of the first vertical synchronization signal; timer_cnt(t3) records a time base data of the base timer at time t3; timer1_reload is the preset timeout period of the timeout timer, which is updated at each time from t3 to t8 and triggers an interrupt. The formula for calculating t4 can be found in the following formula:

[0085] t4-t3=(t5-t3) / oz_pulse_number_tmp0;

[0086] Where oz_pulse_number_tmp0 represents the number of current pulses required within the time period t0, which is the frequency multiplication factor of the current VSYNC. Adjusting this value can change the backlight current dimming frequency.

[0087] To calculate t6 at time t4, the formula for t6 can be found as follows:

[0088] t6-t5=Tnew / oz_pulse_number_tmp1;

[0089] Here, oz_pulse_number_tmp1 represents the number of current pulses required during the time period t1. At times t4 and t6, redundant first vertical synchronization signals are inserted to prevent the problem of continuous writing to the drive register without timely updates. t4-t3 and t6-t5 are equal to the updated PWM current period, which is a multiple of the first vertical synchronization signal. Thus, at time t7, the capture timer can be set to follow the first vertical synchronization signal output by the system chip in the interrupt. At time t8, the new second vertical synchronization signal completes the synchronization with the first vertical synchronization signal. At this time, the count of the timeout timer can be cleared, and the synchronization is completed.

[0090] The principle of the synchronization process of the second vertical synchronization signal when the frequency of the first vertical synchronization signal becomes higher can be referred to the synchronization process of the second vertical synchronization signal when the frequency of the first vertical synchronization signal becomes lower.

[0091] The present invention also proposes an electronic device.

[0092] In one embodiment, the electronic device includes the vertical synchronization signal processing device as described above. It is understood that since the above-described vertical synchronization signal processing device is used in the electronic device of the present invention, the embodiments of the electronic device of the present invention include all the technical solutions of all embodiments of the above-described vertical synchronization signal processing device, and the achieved technical effects are completely the same, and will not be repeated here. It is understood that different electronic devices using the vertical synchronization signal processing device of this solution can all avoid the backlight flicker problem that occurs when the vertical synchronization signal frequency changes.

[0093] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for processing vertical synchronization signals, applied to a vertical synchronization signal processing device, characterized in that, The vertical synchronization signal synchronization processing device includes a system chip, a timeout timer, a basic timer, and a capture timer. The method includes the following steps: The system chip outputs a second vertical synchronization signal following the first vertical synchronization signal, and the frequency of the first vertical synchronization signal is detected by a timeout timer and a capture timer. If the frequency of the first vertical synchronization signal is detected to be higher or lower, the system chip stops outputting the second vertical synchronization signal and generates a signal as the second vertical synchronization signal by adjusting the timeout interrupt of the timeout timer. After detecting that the frequency of the first vertical synchronization signal is stable, a preset time is calculated by the basic timer, and the second vertical synchronization signal is synchronized with the first vertical synchronization signal on the rising edge at the preset time.

2. The vertical synchronization signal synchronization processing method as described in claim 1, characterized in that, The step of detecting the frequency of the first vertical synchronization signal specifically includes: The frequency of the vertical synchronization signal output by the system chip is detected by any one of the following: external interrupt mode of the input / output pin, timer capture mode of the capture timer, or timeout interrupt mode of the timeout timer.

3. The vertical synchronization signal synchronization processing method as described in claim 1, characterized in that, The step of generating the second vertical synchronization signal through a timeout interrupt of a timeout timer specifically includes: The timeout interrupt time is changed by adjusting the reload value of the timeout timer, thereby changing the frequency of the vertical synchronization signal to generate a second vertical synchronization signal.

4. The vertical synchronization signal synchronization processing method as described in claim 3, characterized in that, The step of calculating a preset time using a basic timer and synchronizing the second vertical synchronization signal with the first vertical synchronization signal at the preset time on the rising edge specifically includes: The period after the frequency change of the first vertical synchronization signal is converted into the count value of the basic timer; Calculate the preset time based on the count value of the base timer; The count reached by the base timer at a preset time is converted into the reload value of the timeout timer. The reload value of the timeout timer is changed so that the rising edge of the second vertical synchronization signal starts to synchronize with the rising edge of the first vertical synchronization signal at a preset time.

5. The vertical synchronization signal synchronization processing method as described in claim 1, characterized in that, It also includes the following steps: When the frequency of the first vertical synchronization signal is detected to be higher or lower, the frequency multiplication parameter under different timeout timer parameters is calculated, and the output frequency multiplication parameter is dynamically adjusted to keep the PWM frequency of the backlight current constant.

6. The vertical synchronization signal synchronization processing method as described in claim 1, characterized in that, After the step of synchronizing the second vertical synchronization signal with the first vertical synchronization signal at a preset time on the rising edge, the method further includes: Transfer control of the input / output pins to the interrupt handler of the capture timer.

7. A vertical synchronization signal synchronization processing apparatus based on the vertical synchronization signal synchronization processing method according to any one of claims 1-6, characterized in that, The system includes a controller, a system chip, a timeout timer, a base timer, and a capture timer. The controller is used to output a second vertical synchronization signal following the first vertical synchronization signal output by the system chip, and to detect the frequency of the first vertical synchronization signal through the timeout timer and the capture timer. When the controller detects that the frequency of the first vertical synchronization signal becomes higher or lower, it stops following the system chip to output the second vertical synchronization signal and generates the second vertical synchronization signal by adjusting the timeout interrupt of the timeout timer. After detecting that the frequency of the first vertical synchronization signal is stable, the controller calculates a preset time through the basic timer and synchronizes the second vertical synchronization signal with the first vertical synchronization signal on the rising edge at the preset time.

8. The vertical synchronization signal synchronization processing device as described in claim 7, characterized in that, Also includes: A driving circuit is provided, the input terminal of which is connected to the output terminal of the controller. The output terminal of the driving circuit is used to connect to a light-emitting device. The controller is used to control the driving circuit to drive the light-emitting device to work.

9. The vertical synchronization signal synchronization processing device as described in claim 7, characterized in that, Also includes: A memory electrically connected to the controller, the memory storing a vertical synchronization signal synchronization processing program, which, when executed by the controller, implements the vertical synchronization signal synchronization processing method as described in any one of claims 1-6.

10. An electronic device, characterized in that, Includes the vertical synchronization signal synchronization processing device as described in any one of claims 7-9.

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