Buffer circuit, method of operating buffer circuit, and image sensor system

Abstract

The invention relates to a snubber circuit, a method of operating the snubber circuit, and an image sensor system. The invention discloses a reference buffering system and a method and a device thereof. A reference buffer system or circuit includes an input circuit that may generate a replica of a reference voltage. The feedback circuit may generate the charging current using the current mirror circuit and the bias current. A value of the charging current may be greater than a value of the bias current. The feedback circuit may provide a buffered version of the reference voltage at the reference node using the charging current and the replica voltage. The output stage circuit may absorb the compensation current from the reference node.

Description

Technical Field

[0001] The present disclosure relates to electronic circuits, and more particularly to reference voltage drivers and buffer circuits, methods of operating buffer circuits, and image sensor systems. Background Art

[0002] Reference voltage buffer circuits (also called "reference buffer circuits") that buffer or drive a reference voltage that is independent of power supply and temperature variations can be used in a variety of applications. Such circuits can be used to drive the reference voltage of analog-to-digital converter (ADC) circuits, common-mode drivers in amplifier circuits, and other analog circuits. Reference buffer circuits can be used in motion sensor circuits, image sensor circuits, liquid crystal display (LCD) driver circuits, etc. Summary of the invention

[0003] Various embodiments of reference buffer circuits are disclosed. One example is a buffer circuit comprising: an input circuit configured to generate a replica voltage using a reference voltage, wherein the replica voltage is biased from the reference voltage; a feedback circuit; and an output stage circuit. The feedback circuit may be configured to: generate a bias current; generate a charging current using the bias current, wherein the value of the charging current is greater than the value of the bias current; and provide a buffered reference voltage at a reference node using the charging current and the replica voltage. The output stage circuit may be configured to sink a compensation current from the reference node based on the buffered reference voltage.

[0004] In the exemplary buffer circuit, to provide a buffered reference voltage, the feedback circuit may be further configured to: provide a charging current to a reference node; and sink a portion of the charging current from the reference node, wherein a value of the portion of the charging current is based on the replica voltage.

[0005] In the exemplary buffer circuit, the feedback circuit may include a current mirror circuit including a diode-connected transistor and a mirror transistor coupled between a power supply node and the reference node, wherein a first beta ratio of the diode-connected transistor is less than a second beta ratio of the mirror transistor, and wherein the mirror transistor is configured to provide the charging current to the reference node based on a current flowing in the diode-connected transistor.

[0006] In the exemplary buffer circuit, the output stage circuit includes a transistor coupled between the reference node and a ground supply node, wherein the transistor is configured to adjust conductance between the reference node and the ground supply node based on the buffered reference voltage and the replica voltage.

[0007] In the exemplary buffer circuit, the output stage circuit includes a transistor coupled between the reference node and the ground supply node, and wherein the output stage circuit can be further configured to: generate an adjustment current using the bias current, wherein the value of the adjustment current is less than the value of the bias current; and modify the voltage level of the control terminal of the transistor using the adjustment current.

[0008] In the exemplary buffer circuit, the replica voltage may be less than the reference voltage, and wherein to generate the replica voltage, the input circuit may be further configured to: convert the reference voltage into a first current; generate a second current using a bias voltage; and combine the first current and the second current to generate the replica voltage.

[0009] Yet another example is a method comprising: receiving a reference voltage by a buffer circuit; generating a replica voltage by the buffer circuit using the reference voltage, wherein the replica voltage is biased from the reference voltage; generating a bias current by the buffer circuit; generating a charging current by the buffer circuit using the bias current, wherein the charging current is greater than the bias current; and providing a buffered reference voltage at a reference node using the charging current and the replica voltage by the buffer circuit.

[0010] In the exemplary method of operating a buffer circuit, providing a buffered reference voltage may include: providing a charging current to a reference node; and sinking a portion of the charging current from the reference node, wherein a value of the portion of the charging current is based on the replica voltage.

[0011] In the exemplary method of operating a buffer circuit, the buffer circuit may include an output stage circuit, and the method may further include sinking a compensation current from a reference node by the output stage circuit. The output stage circuit may include a transistor coupled between the reference node and a ground supply node, and wherein sinking the compensation current may include adjusting, by the transistor, a conductance between the reference node and the ground supply node based on a value of the replica voltage. The output stage circuit may include a transistor coupled between the reference node and the ground supply node, and the method may further include: generating, by the output stage circuit, an adjustment current using the bias current, wherein a value of the adjustment current is less than a value of the bias current; and modifying, by the transistor, the conductance between the reference node and the ground supply node using the adjustment current. The method may further include disabling the output stage circuit by coupling a control terminal of the transistor to a power supply node.

[0012] In the exemplary method of operating a buffer circuit, generating the replica voltage may include: converting a reference voltage into a first current; generating a second current using a bias voltage; and combining the first current and the second current to generate the replica voltage.

[0013] Yet another example is a system that includes an image sensor circuit (coupled to a reference node), a reference buffer circuit, and the reference buffer circuit can be configured to: receive a reference voltage; generate a bias current; use the bias current to generate a charging current; and provide a buffered reference voltage at the reference node based on the reference voltage and using the charging current.

[0014] In the exemplary system, to provide a buffered reference voltage, the reference buffer circuit may be further configured to: generate a replica voltage using the reference voltage, wherein the replica voltage is biased from the reference voltage; provide the charging current to the reference node; and sink a portion of the charging current from the reference node, wherein the value of the portion of the charging current is based on the replica voltage. The reference buffer circuit may be further configured to sink a compensation current from the reference node. To sink the compensation current from the reference node, the reference buffer circuit may be further configured to adjust the conductance between the reference node and the ground supply node based on the value of the replica voltage and the buffered reference voltage. To sink the compensation current from the reference node, the reference buffer circuit may be further configured to: generate an adjustment current using the bias current, wherein the value of the adjustment current is less than the bias current; and modify the conductance between the reference node and the ground supply node using the adjustment current and the buffered reference voltage. To generate the replica voltage, the reference buffer circuit may be further configured to: convert the reference voltage into a first current; generate a second current using the bias voltage; and combine the first current and the second current to generate the replica voltage.

[0015] In the exemplary system, the image sensor circuit may be further configured to charge at least one capacitor using the buffered reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To describe in detail example embodiments, reference will now be made to the accompanying drawings, in which:

[0017] Figure 1 is a block diagram of one embodiment of a reference buffer circuit.

[0018] Figure 2 is a block diagram of one embodiment of an input circuit for a reference buffer circuit.

[0019] Figure 3 are block diagrams of various implementations of input circuits for reference buffer circuits.

[0020] Figure 4 is a block diagram of one embodiment of a feedback circuit for a reference buffer circuit.

[0021] Figure 5 is a block diagram of one embodiment of an output stage circuit for a reference buffer circuit.

[0022] Figure 6 is a block diagram of different implementations of output stage circuits for a reference buffer circuit.

[0023] Figure 7 is a block diagram of an image sensor system.

[0024] Figure 8 is a flow chart of one embodiment of a method for operating a reference buffer circuit. DETAILED DESCRIPTION

[0025] Many electrical connections in the drawings are shown as directly coupled without intervening devices, but are not explicitly described as such in the following description. However, for electrical connections shown in the drawings without intervening devices, this paragraph should serve as an antecedent basis for the claims for referring to any electrical connection as "directly coupled."

[0026] definition

[0027] Various terms are used to refer to specific system components. Different companies may refer to a component by different names - this document is not intended to distinguish between components that have different names but the same function. In the following discussion and in the claims, the terms "include" and "comprising" are used in an open form, and therefore, these terms should be interpreted to mean "including but not limited to...". In addition, the terms "couple" or "coupled" are intended to mean either an indirect connection or a direct connection. Thus, if a first device is coupled to a second device, that connection may be made through a direct connection or through an indirect connection via other devices and connections.

[0028] As used herein, "a", "an", and "the" refer to both singular and plural referents unless the context clearly indicates otherwise. For example, a "processor" programmed to perform various functions refers to one processor programmed to perform each function, or more than one processor that are collectively programmed to perform each of the various functions.

[0029] With respect to an electrical device (whether stand-alone or as part of an integrated circuit), the terms "input" and "output" refer to electrical connections to the electrical device and should not be construed as requiring verbs to operate. For example, a differential amplifier (such as an operational amplifier) ​​may have a first differential input and a second differential input, and these "inputs" define electrical connections to the operational amplifier and should not be construed as requiring signal inputs to the operational amplifier.

[0030] "Asserting" shall mean creating or maintaining a first predetermined state of a Boolean signal. At the discretion of the circuit designer, a Boolean signal may be asserted high or with a higher voltage, and a Boolean signal may be asserted low or with a lower voltage. Similarly, "de-asserting" shall mean creating or maintaining a second predetermined state of a Boolean signal that is opposite to the asserted state.

[0031] “FET” shall refer to a field effect transistor, such as a junction gate FET (JFET), a metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), or a gate-all-around field effect transistor (GAAFET).

[0032] "Closing" with respect to an electrically controlled switch (eg, a FET) shall mean turning the electrically controlled switch on. For example, closing a FET used as an electrically controlled switch may mean driving the FET to a fully on state.

[0033] "Off" with respect to an electronically controlled switch (eg, a FET) shall mean that the electronically controlled switch is not conducting.

[0034] “Controller” or “controller circuitry” shall mean, alone or in combination, an individual circuit component, an application specific integrated circuit (ASIC), a microcontroller with control software, a reduced instruction set computing (RISC) circuit with control software, a digital signal processor (DSP), a processor with control software, a programmable logic device (PLD), a field programmable gate array (FPGA), or a programmable system on a chip (PSOC), configured to read inputs and drive outputs in response to those inputs.

[0035] Various sensor circuits employ reference voltage buffer circuits that drive or buffer a reference voltage that is substantially independent of manufacturing variations, supply voltage variations, and temperature variations. Such sensor circuits may use the buffered reference voltage as a comparison point for generated signals, as well as to generate bias currents and voltages for analog circuits.

[0036] One type of sensor circuit that employs a reference voltage buffer circuit is an image sensor circuit. An image sensor circuit may include a plurality of pixel circuits that generate corresponding analog signals, the value of which corresponds to the amount of light shining on the pixel. The image sensor circuit converts the analog signals into digital bits, which may be further processed into an image for display.

[0037] To convert the analog signals generated by the pixel circuits into digital bits, the image sensor circuits employ analog-to-digital converter circuits. Various types of analog-to-digital converter circuits may be employed, including Wilkinson analog-to-digital converter circuits, direct conversion (or "flash") analog-to-digital converter circuits, and successive approximation analog-to-digital converter circuits.

[0038] In a successive approximation analog-to-digital converter circuit, an approximation value (i.e., the number of bits) is converted to a test analog value using a digital-to-analog converter circuit. The test analog value is compared to the analog signal to be converted. Based on the result of the comparison, the approximation value is adjusted. This process is repeated until the test analog value is substantially the same as the analog signal. At this point, the bits included in the approximation value correspond to the values ​​of the analog signal.

[0039] To generate the test analog value, the digital-to-analog converter circuit charges capacitors of different values ​​to a reference voltage. Once the capacitors are charged, the stored charge is combined at the input pins of the comparator circuit to generate the test analog value. As the capacitors are charged and discharged, currents may be drawn from and injected into the output nodes of the reference buffer circuit that drives the reference voltage. These currents may cause the reference voltage to fluctuate until the reference buffer circuit has time to re-adjust the reference voltage. The time that the reference voltage is not within its expected range may affect the bandwidth and / or accuracy of the analog-to-digital converter circuit.

[0040] The embodiments described herein may provide a technique for buffering a reference voltage of a load circuit to compensate for large transient and switching currents on its output using a reference buffer circuit having low output impedance or high unity gain bandwidth. By adopting such a reference buffer circuit, the variation of the reference voltage due to transient current and the output settling time of the reference voltage may be reduced, thereby improving the performance of the load circuit.

[0041] exist Figure 1 A block diagram of an embodiment of a reference buffer circuit is depicted in As shown, the reference buffer circuit 100 includes an input circuit 101 , a feedback circuit 102 , and an output stage circuit 103 .

[0042] Input circuit 101 is configured to generate replica voltage 105 using reference voltage 104. In some embodiments, the value of replica voltage 105 can be biased from the value of reference voltage 104. In some cases, such biasing can be a positive bias, resulting in the value of replica voltage 105 being greater than the value of reference voltage 104. In other cases, the biasing can be negative, resulting in the value of replica voltage 105 being less than the value of reference voltage 104. In various embodiments, the offset between the value of replica voltage 105 and the value of reference voltage 104 can correspond to a transistor threshold voltage.

[0043] The feedback circuit 102 is configured to provide a buffered reference voltage 106 at a reference node 107. As described below, the feedback circuit 102 may include a current mirror circuit configured to generate a charging current 108 by "mirroring" a bias current 109. In various embodiments, the value of the charging current may be greater than the value of the bias current. In some embodiments, the feedback circuit 102 may be configured to generate a buffered reference voltage 106 by providing a charging current to the reference node 107 and sinking another current from the reference node 107 whose value is determined by the replica voltage 105.

[0044] The output stage circuit 103 is configured to sink a compensation current 110 from the reference node 107. Sinking the compensation current 110 helps maintain the desired value of the buffered reference voltage 106 during the time period when the load circuit provides current to the reference node 107. As described below, different techniques can be used to sink the compensation current 110. It should be noted that in some embodiments, the feedback circuit 102 and the output circuit 103 can be used independently of the input circuit 101 by directly buffering the reference voltage rather than using a replica of the reference voltage.

[0045] Steering Figure 2 , depicts a block diagram of an implementation of an input circuit. In various implementations, the input circuit 200 may correspond to Figure 1 1. As shown in the figure, the input circuit 200 includes transistors 201-203, a capacitor 204 and an error amplifier circuit 205.

[0046] Transistor 201 is coupled between power supply node 206 and node 208 and is controlled by the voltage level of node 213. Transistor 203 is coupled between node 208 and node 209 and is controlled by replica voltage 105. Transistor 202 is coupled between node 209 and ground supply node 207 and is controlled by tail bias 210.

[0047] The error amplifier circuit 205 is configured to generate a voltage level on a node 213 using the reference voltage 104 and the voltage level of the node 208. To generate the voltage level on the node 213, in some embodiments, the error amplifier circuit 205 can be configured to perform a comparison between the reference voltage 104 and the voltage level of the node 208, and use the result of the comparison to generate the voltage level on the node 213. In various embodiments, the voltage level of the node 213 can be proportional to the difference between the reference voltage 104 and the voltage level of the node 208. In some embodiments, the error amplifier circuit 205 can be implemented using a differential amplifier circuit or any other suitable comparator circuit configured to generate an output voltage based on the difference between at least two input voltage levels.

[0048] Capacitor 204 is coupled between node 213 and ground supply node 207. In some embodiments, capacitor 204 is configured to filter noise on node 213 to improve the stability of input circuit 200. In various embodiments, capacitor 204 can be implemented using a metal-insulator-metal (MIM) structure, a metal-oxide-metal (MOM) structure, or any other suitable capacitor structure available on semiconductor manufacturing processes.

[0049] In various embodiments, error amplifier circuit 205 and transistor 201 together function as a voltage-to-current converter circuit that generates current 211 that flows from power supply node 206 into transistor 203. Transistor 202 is configured to sink current 212 from node 209. The value of current 212 may be based at least in part on tail bias 210. The difference between currents 211 and 212 generates a voltage drop across transistor 203 that corresponds to replica voltage 105. In various embodiments, the value of replica voltage 105 may be less than reference voltage 104 by a threshold associated with transistor 203.

[0050] In various embodiments, transistors 201 and 202 may be implemented as n-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices. In some embodiments, transistor 203 may be implemented as p-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices. Figure 2 In the embodiments of FIG. 2 , transistors 201 - 203 are depicted as single transistors, but in other embodiments, any suitable series and / or parallel combination of transistors may be used to implement any of transistors 201 - 203 .

[0051] In some cases, input circuit 101 should present a low impedance to the input of feedback circuit 102 . Figure 3 A block diagram of another embodiment of an input circuit that uses folding and mirroring techniques to reduce its output impedance is depicted in FIG. In various embodiments, the input circuit 300 may correspond to Figure 1 1. As shown in the figure, the input circuit 300 includes transistors 301-310, an error amplifier circuit 311 and a capacitor 322.

[0052] Transistor 301 is coupled between power supply node 206 and node 317 and is controlled by p bias 312. In a similar manner, transistor 302 is coupled between power supply node 206 and node 318 and is also controlled by p bias 312. Transistor 303 is coupled between node 318 and node 319 and is controlled by folding bias 314.

[0053] Transistor 305 is coupled between power supply node 206 and node 315, and is controlled by the voltage level of node 321. Transistor 304 is coupled between node 315 and node 316, and is controlled by the voltage level of node 316. In various implementations, transistor 304 is referred to as "diode connected". Transistor 307 is coupled between node 316 and ground supply node 207, and is controlled by n bias 313. Transistor 306 is coupled between node 317 and node 316, and is controlled by the voltage level of node 317. Transistor 306 may also be referred to as "diode connected".

[0054] Transistor 310 is coupled between node 318 and node 320, and is controlled by the voltage level of node 317. Transistor 308 is coupled between node 319 and ground supply node 207, and is controlled by the voltage level of node 319. Transistor 309 is coupled between node 320 and ground supply node 207, and is also controlled by the voltage level of node 319. In various implementations, transistors 308 and 309 may be configured to operate as a current mirror circuit, where mirror transistor 309 replicates (or "mirrors") the current flowing in diode-connected transistor 308.

[0055] The error amplifier circuit 311 is configured to generate a voltage level on a node 321 using the reference voltage 104 and the voltage level of the node 315. To generate the voltage level on the node 321, in some embodiments, the error amplifier circuit 311 may be configured to perform a comparison between the reference voltage 104 and the voltage level of the node 315, and use the result of the comparison to generate the voltage level on the node 321. In various embodiments, the voltage level of the node 321 may be proportional to the difference between the reference voltage 104 and the voltage level of the node 315. In some embodiments, the error amplifier circuit 311 may be implemented using a differential amplifier circuit or any other suitable comparator circuit configured to generate an output voltage based on the difference between at least two input voltage levels.

[0056] Capacitor 322 is coupled between node 321 and ground supply node 207. In some embodiments, capacitor 322 is configured to filter noise on node 321 to improve the stability of input circuit 300. In various embodiments, capacitor 322 can be implemented using a MIM structure, a MOM structure, or any other suitable capacitor structure available on a semiconductor manufacturing process.

[0057] In various embodiments, error amplifier circuit 311 and transistor 305 together act as a voltage-to-current converter circuit that generates current 323 flowing from power supply node 206 into transistor 305, which in turn flows via transistor 304 into node 316. Transistor 307 is configured to sink current from node 316 using n-bias 313.

[0058] Transistor 301 is configured to generate a current flowing from power supply node 206 into node 317 based on p-bias 312. A portion of the current flowing in node 317 flows through transistor 306 into node 316 based on the voltage level of node 317. In various embodiments, the voltage level on node 317 is based on the difference between the respective currents flowing through transistors 304 and 306.

[0059] Transistor 302 is configured to generate a current that flows from power supply node 206 into node 318 based on p-bias 312. A portion of the current that flows from transistor 302 into node 318 flows into transistor 303 based on folding bias 314. In various embodiments, transistors 306 and 310 may act as a current mirror circuit, where the current flowing in diode-connected transistor 306 is replicated (or "mirrored") in transistor 310. In a similar manner, transistors 308 and 309 are configured to act as a current mirror circuit, where the current that flows from transistor 303 into diode-connected transistor 308 is replicated (or "mirrored") in transistor 309.

[0060] The difference between the current flowing in transistor 310 and the current flowing in transistor 309 generates replica voltage 105. In various embodiments, the value of replica voltage 105 on node 320 is based on the difference in current flowing in transistors 309 and 310. Note that input circuit 300 also generates replica voltage 105 with an offset from reference voltage 104.

[0061] In various embodiments, transistors 301-304 may be implemented as p-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices, and transistors 305-310 may be implemented as n-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices. Figure 3 In the embodiments of FIG. 3 , transistors 301 - 310 are depicted as single transistors, but in other embodiments, any suitable series and / or parallel combination of transistors may be used to implement any of transistors 301 - 310 .

[0062] Steering Figure 4 , depicts a block diagram of an embodiment of the feedback circuit 102. As shown, the feedback circuit 102 includes transistors 401-406, a switch 415, and a capacitor 417.

[0063] Transistor 401 is coupled between power supply node 206 and node 407, and is controlled by the voltage level of node 407. Transistor 402 is coupled between power supply node 206 and reference node 107, and is controlled by the voltage level of node 407. In various embodiments, transistors 401 and 402 are configured to operate as a current mirror circuit, where the current flowing in transistor 401 is replicated in transistor 402. In some embodiments, transistor 401 is referred to as "diode connected" because its drain and gate are coupled together, and transistor 402 is referred to as a "mirror transistor" because the current flowing in transistor 401 is replicated (or "mirrored") in transistor 402.

[0064] In some implementations, the beta ratio of transistor 402 is greater than the beta ratio of transistor 401, resulting in a current flowing in transistor 402 that is greater than the current flowing in transistor 401 by an amount corresponding to the ratio of the two beta ratios. In some cases, the beta ratio of transistor 402 can be a factor greater than the beta ratio of transistor 401, i.e., beta 402 = kβ 401 , where β 401 is the β ratio of transistor 401, β 402 is the beta ratio of transistor 402 , and k is selected based on the desired change in charging current 108 for a corresponding change in buffered reference voltage 106 .

[0065] Transistor 403 is coupled between reference node 107 and node 408 and is controlled by replica voltage 105. Transistor 404 is coupled between node 407 and node 408 and is controlled by the voltage level of node 416.

[0066] Transistor 405 is coupled between node 408 and node 409 and is controlled by cascode bias 411. Transistor 406 is coupled between node 409 and ground supply node 207 and is controlled by tail bias 210.

[0067] In various embodiments, cascode bias 411 and tail bias 210 establish tail current 413 that flows through transistors 405 and 406. Folding bias 410 establishes a current flowing in transistor 404 that also flows through transistor 401. The current flowing through transistor 401 is replicated (or "mirrored") in transistor 402 to produce charging current 108. In various embodiments, the value of charging current 108 can be greater than the current flowing in transistor 401 by an amount corresponding to the difference between the respective beta ratios of transistors 401 and 402.

[0068] Charging current 108 is provided to reference node 107 as part of the generation of buffered reference voltage 106. When charging current 108 is provided to reference node 107, transistor 403 is configured to sink a portion of charging current 108 from reference node 107. In various embodiments, the value of the portion of charging current 108 is based at least in part on the value of replica voltage 105 and buffered reference voltage 106.

[0069] By utilizing the multiplication effect of the current mirror circuit formed by transistors 401 and 402, a high charging rate of reference node 107 can be achieved, thereby improving the response time of reference buffer circuit 100 to an increase in the current drawn from reference node 107 by the load circuit. Figure 4 The embodiments depict a current mirror circuit implemented using p-channel transistors, but in other embodiments, the current mirror circuit of feedback circuit 102 may be implemented using n-channel transistors. In such cases, charging current 108 may be sunk from reference node 107 rather than provided to reference node 107. In some embodiments, both a current mirror circuit implemented using p-channel transistors and another current mirror circuit implemented using n-channel transistors may be employed to allow current to be both provided to reference node 107 and sunk from reference node 107.

[0070] In the presence of a large capacitive load coupled to reference node 107, the dominant pole of the system will be reference node 107. The topology of feedback circuit 102 provides a low output impedance 1 / g at the non-dominant pole. m , making it easier to achieve stability of the reference buffer circuit 100 without adding a compensation network or increasing the power consumption of the circuit.

[0071] In addition, feedback circuit 102 can operate over a wide range of values ​​of power supply node 206. For example, in some cases, feedback circuit 102 can operate with the voltage level of power supply node 206 at or near 1.8V, thereby reducing power consumption. Using a current mirror circuit formed by transistors 401 and 402 also allows the value of reference voltage 104 to be close to the voltage level of power supply node 206, thereby allowing reference buffer circuit 100 to be used in a wide range of applications.

[0072] The switch 415 is configured to couple the folding bias 410 to a node 416, which in turn is coupled to the ground supply node 207 via a capacitor 417. In various embodiments, the switch 415 and the capacitor 417 are used as a sample-and-hold circuit. By sampling the folding bias 410, the kickback interaction with the feedback of the feedback circuit 102 can be reduced. In some embodiments, the switch 415 can be implemented using at least one MOSFET, FinFET, GAAFET, or any other suitable transconductance device. In various embodiments, the capacitor 417 can be implemented using a MIM structure, a MOM structure, or any other suitable capacitor structure available on a semiconductor manufacturing process.

[0073] In some embodiments, transistors 401-403 may be implemented as p-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices. In various embodiments, transistors 404-406 may be implemented as n-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices. Figure 4 In the embodiments of FIG. 4 , transistors 401 - 406 are depicted as single transistors, but in other embodiments, any suitable series and / or parallel combination of transistors may be used to implement any of transistors 401 - 406 .

[0074] Figure 5 A block diagram of an embodiment of an output stage circuit is depicted in . In various embodiments, output stage circuit 500 may correspond to output stage circuit 103 . As shown, output stage circuit 500 includes transistor 501 .

[0075] Transistor 501 is coupled between reference node 107 and ground supply node 207 and is controlled by replica voltage 105. In various embodiments, transistor 501 is configured to sink compensation current 110 from reference node 107 based on the voltage level of reference node 107 and replica voltage 105. In various embodiments, transistor 501 can be configured to act as a source follower during negative transitions.

[0076] It should be noted that transistor 501 will sink a portion of the current flowing in transistor 402 of feedback circuit 102. By sinking a portion of the current flowing in transistor 402, transistor 501 can limit the unity gain bandwidth of feedback circuit 102. In various implementations, the beta ratio of transistor 501 can be selected based on a tradeoff between unity gain bandwidth and negative transition performance.

[0077] In some embodiments, transistor 501 may be implemented as a p-channel MOSFET, FinFET, GAAFET, or any other suitable transconductance device. Figure 5In the embodiments of FIG. 5 , transistor 501 is depicted as a single transistor, but in other embodiments, transistor 501 can be implemented using any suitable series and / or parallel combination of transistors.

[0078] exist Figure 5 In an embodiment of the present invention, the control terminal of transistor 501 is maintained at the replica voltage 105, which limits the maximum value of the compensation current 110 that can be sunk from the reference node 107 during the negative transition. By adjusting the value of the control terminal, the output stage transistors (such as transistor 501) can be caused to change the amount of current sunk from the reference node 107. Figure 6 An embodiment of an output stage circuit that allows such varying current is depicted in .

[0079] As shown, the output stage circuit 600 includes transistors 601-604 and switches 605 and 606. In various embodiments, the output stage circuit 600 may correspond to Figure 1 The output stage circuit 103 is depicted in FIG.

[0080] Transistor 601 is coupled between power supply node 206 and node 607 and is controlled by node 407 of feedback circuit 102, such as Figure 4 Transistor 602 is coupled between reference node 107 and ground supply node 207 and is controlled by the voltage level of node 607 .

[0081] Transistor 603 is coupled between node 608 and node 609, while transistor 604 is coupled between node 609 and ground supply node 207. Respective control terminals of transistors 603 and 604 are coupled to node 608.

[0082] like Figure 4 As shown, transistor 601 replicates a small portion of the current flowing in transistor 401 to generate compensation current 110. In various embodiments, the beta ratio of transistor 601 is less than the beta ratio of transistor 401. Adjustment current 610 flows through transistors 603 and 604, thereby generating a voltage on node 607 that modulates the conductance of transistor 602. During negative transition conditions, the majority of tail current 413 flows through transistor 403, with little current flowing in transistor 401, resulting in a small value for compensation current 110. With little current supplied to node 607 by transistor 602, node 607 discharges via transistors 603 and 604, thereby increasing the activation level of transistor 601, thereby increasing the value of compensation current 110, which helps sink the current provided by the load circuit into reference node 107.

[0083] Switch 605 is coupled between power supply node 206 and node 607, and switch 606 is coupled between node 607 and node 608. In some embodiments, switches 605 and 606 may be employed to disable output stage circuit 600 to save static power when negative transitions are not a problem. To disable output stage circuit 600, switch 605 may be closed and switch 606 may be opened, which couples the control terminal of transistor 602 to power supply node 206, thereby rendering transistor 602 inactive. To enable output stage circuit 600, switch 605 may be opened and switch 606 may be closed, which allows the voltage level of the control terminal of transistor 602 to vary based on the current flowing through transistor 601.

[0084] In various embodiments, switches 605 and 606 may be implemented as metal switches that are programmed to open or close during manufacturing. Alternatively, switches 605 and 606 may be implemented with transistors that are controlled by signals determined at power-up, or based on the operating mode of a computer system that includes reference buffer circuit 100.

[0085] In some embodiments, transistors 601 and 602 may be implemented as p-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices, while transistors 603 and 604 may be implemented as n-channel MOSFETs, FinFETs, GAAFETs, or any other suitable transconductance devices. Although transistors 601-604 are depicted as single transistors, in other embodiments, any of transistors 601-604 may be implemented using any suitable series and / or parallel combination of transistors.

[0086] Steering Figure 7 , depicts a block diagram of an image sensor system. As shown in the figure, the image sensor system 700 includes a reference buffer circuit 100 and an image sensor 701 , which includes an analog-to-digital converter circuit 702 .

[0087] As described above, the reference buffer circuit 100 is configured to generate a buffered reference voltage 704 using the reference voltage 703. Figure 7 In embodiments, reference buffer circuit 100 may include different relative device sizes to select appropriate negative conversion performance and unity gain bandwidth based on the requirements of image sensor circuit 701 .

[0088] In various embodiments, analog-to-digital converter circuit 702 may correspond to a column analog-to-digital conversion circuit of image sensor 701. To achieve a desired level of performance, the conversion time of analog-to-digital converter circuit 702 should be low. In various embodiments, such conversion time may be limited by the settling time of buffered reference voltage 704.

[0089] In various embodiments, the analog-to-digital converter circuit 702 may include a plurality of capacitors as part of a digital-to-analog converter circuit also included in the analog-to-digital converter circuit 702. During sampling operations, bottom plates of the plurality of capacitors may be coupled to the buffered reference voltage 704. As described above, the reference buffer circuit 100 may be configured to sink the discharge conversion current in order to maintain a desired value of the buffered reference voltage 704.

[0090] Steering Figure 8 , a flow chart depicting an embodiment of a method for operating a reference buffer circuit is shown. Figure 1 The method of various reference buffer circuits of the reference buffer circuit 100 depicted in FIG. 8 begins in block 801 .

[0091] The method includes receiving a reference voltage by a buffer circuit (block 802). In various implementations, the method may also include generating the reference voltage by a bandgap reference circuit.

[0092] The method also includes generating, by the buffer circuit, a replica voltage using the reference voltage (block 803). In various embodiments, the replica voltage is biased from the reference voltage. As described above, the replica voltage may be greater than the reference voltage, or less than the reference voltage. In some cases, the difference between the replica voltage and the reference voltage may correspond to a transistor threshold voltage. In some embodiments, generating the replica voltage includes converting the reference voltage into a first current, generating a second current using the bias voltage, and combining the first current and the second current to generate the replica voltage.

[0093] The method also includes generating a bias current by the buffer circuit (block 804). In various embodiments, the buffer circuit includes a current mirror circuit including a diode-connected transistor (e.g., transistor 401) and a mirror transistor (e.g., transistor 402) coupled to a common control node. In some embodiments, generating the bias current may include adjusting a voltage of a control terminal of a transistor coupled to the diode-connected transistor.

[0094] The method also includes generating a charging current using the bias current by the buffer circuit (block 805). In various embodiments, the value of the charging current may be greater than the value of the bias current. In some cases, generating the charging current includes generating the charging current by a mirror transistor based on the bias current flowing in the diode-connected transistor.

[0095] The method also includes providing, by the buffer circuit, a buffered reference voltage at the reference node using the charging current and the replica voltage (block 806). In some embodiments, providing the buffered reference voltage includes providing the charging current to the reference node and drawing a portion of the charging current from the reference node. In some embodiments, a value of the portion of the charging current may be based on a value of the replica voltage.

[0096] In various embodiments, the buffer circuit includes an output stage circuit. In such cases, the method may further include sinking, by the output stage circuit, a compensation current from the reference node. In some embodiments, sinking the compensation current may include adjusting, by a transistor included in the output stage circuit, a conductance between the reference node and the ground supply node based on a value of the replica voltage. In other embodiments, sinking the compensation current may include generating, by the output stage circuit, an adjustment current (e.g., adjustment current 610) using a bias current, and modifying, by a transistor included in the output stage circuit, a conductance between the reference node and the ground supply node using the adjustment current. In various embodiments, the value of the adjustment current is less than the value of the bias current.

[0097] In some cases, the method may further include disabling the output stage circuit. In various embodiments, disabling the output stage circuit may include coupling a control terminal of a transistor included in the output stage circuit to a power supply node, the transistor being coupled between the reference node and the ground supply node. The method ends in block 807.

[0098] ****

[0099] The present disclosure includes references to "an embodiment" or "groups of embodiments." As used herein, an embodiment is a different specific implementation of an example of a disclosed concept. References to "an embodiment," "some embodiments," and the like do not necessarily refer to the same embodiment. Many embodiments are possible and contemplated, including those specifically disclosed as well as modifications or substitutions that fall within the spirit or scope of the present disclosure.

[0100] The above disclosure is intended to illustrate the principles of the disclosed concepts and some of the various embodiments. Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. The following claims are interpreted as being intended to include all such variations and modifications.

Claims

1. A buffer circuit, comprising: an input circuit configured to generate a replica voltage using a reference voltage, wherein the replica voltage is biased from the reference voltage; A feedback circuit, the feedback circuit being configured to: generate a bias current; generate a charging current using the bias current, wherein a value of the charging current is greater than a value of the bias current; and providing a buffered reference voltage at a reference node using the charging current and the replica voltage; and An output stage circuit is configured to sink a compensation current from the reference node based on the buffered reference voltage.

2. The buffer circuit according to claim 1, wherein in order to provide the buffered reference voltage, the feedback circuit is further configured to: providing the charging current to the reference node; and A portion of the charging current is sunk from the reference node, wherein a value of the portion of the charging current is based on the replica voltage.

3. The buffer circuit of claim 1 , wherein the feedback circuit comprises a current mirror circuit, the current mirror circuit comprising a diode-connected transistor and a mirror transistor coupled between a power supply node and the reference node, wherein a first beta ratio of the diode-connected transistor is less than a second beta ratio of the mirror transistor, and wherein the mirror transistor is configured to provide the charging current to the reference node based on a current flowing in the diode-connected transistor.

4. The buffer circuit of claim 1 , wherein the output stage circuit comprises a transistor coupled between the reference node and a ground supply node, wherein the transistor is configured to adjust conductance between the reference node and the ground supply node based on the buffered reference voltage and the replica voltage.

5. A method of operating a buffer circuit, comprising: receiving a reference voltage from a buffer circuit; generating, by the buffer circuit, a replica voltage using the reference voltage, wherein the replica voltage is biased from the reference voltage; generating a bias current by the buffer circuit; generating, by the buffer circuit, a charging current using the bias current, wherein the charging current is greater than the bias current; as well as A buffered reference voltage is provided by the buffer circuit at a reference node using the charging current and the replica voltage.

6. The method of claim 5, wherein providing the buffered reference voltage comprises: providing the charging current to the reference node; as well as A portion of the charging current is sunk from the reference node, wherein a value of the portion of the charging current is based on the replica voltage.

7. The method of claim 5 , wherein the buffer circuit comprises an output stage circuit including a transistor coupled between the reference node and a ground supply node, and further comprising sinking a compensation current from the reference node by the output stage circuit by adjusting, by the transistor, a conductance between the reference node and the ground supply node based on a value of the replica voltage.

8. An image sensor system, comprising: an image sensor circuit coupled to the reference node; and A reference buffer circuit, the reference buffer circuit being configured as: receiving a reference voltage; generating a bias current; generating a charging current using the bias current; as well as A buffered reference voltage is provided at the reference node based on the reference voltage and using the charging current.

9. The image sensor system of claim 8, wherein to provide the buffered reference voltage, the reference buffer circuit is further configured to: generating a replica voltage using the reference voltage, wherein the replica voltage is biased from the reference voltage; providing the charging current to the reference node; as well as A portion of the charging current is sunk from the reference node, wherein a value of the portion of the charging current is based on the replica voltage.

10. The image sensor system according to claim 9, wherein to generate the replica voltage, the reference buffer circuit is further configured to: converting the reference voltage into a first current; generating a second current using a bias voltage; and The first current and the second current are combined to generate the replica voltage.

Images