Semiconductor memory device

Abstract

The present disclosure relates to a semiconductor memory device. Embodiments provide a memory capable of reducing a cell size. A memory according to an embodiment includes a laminate including first conductive films and first insulating films alternately laminated in a first direction. The first columnar body includes a first semiconductor portion, a first insulator portion, a second insulator portion, a third insulator portion, and a fourth insulator portion extending in a first direction in the stacked body. The second insulator portion includes: a first portion provided between the first insulator portion and the first conductive film; and a second portion provided between the first insulator portion and the first insulating film, the second portion having a thickness smaller than that of the first portion in a second direction orthogonal to the first direction. The plurality of first insulating films are laminated films of a second insulating film and a third insulating film or are formed by the third insulating film.

Description

[0001] References to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-152639 (filing date: September 20, 2023), and this application incorporates all the contents of the basic application by reference. Technical Field

[0003] This embodiment relates to a semiconductor memory device. Background Art

[0004] Some semiconductor memory devices such as NAND (Not AND) flash memories have a three-dimensional memory cell array in which a plurality of memory cells are arranged three-dimensionally. In such a three-dimensional memory cell array, charge leakage between adjacent memory cells sharing a charge trapping film becomes a problem. Summary of the invention

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device which can suppress charge leakage between memory cells and reduce the cell size.

[0006] The semiconductor storage device of this embodiment has a laminated body including a plurality of first conductive films and a plurality of first insulating films alternately laminated in a first direction. The plurality of first columnar bodies include: a first semiconductor portion extending in the laminated body in the first direction; a first insulating portion disposed between the first semiconductor portion and the laminated body; a second insulating portion disposed between the first insulating portion and the laminated body; a third insulating portion disposed between the second insulating portion and the plurality of first conductive films; and a fourth insulating portion disposed between the second insulating portion and the plurality of first insulating films. The second insulating portion includes: a first portion disposed between the first insulating portion and the first conductive film; and a second portion disposed between the first insulating portion and the first insulating film, the thickness of which in a second direction orthogonal to the first direction is thinner than that of the first portion. The plurality of first insulating films are laminated films of the second insulating film and the third insulating film, or are composed of the third insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a cross-sectional view showing a configuration example of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 It is a schematic plan view showing a layered product.

[0009] Figure 3 is a schematic cross-sectional view illustrating a memory cell array.

[0010] Figure 4 is along Figure 3 A cross-sectional view of line 4-4.

[0011] Figure 5 is along Figure 3 A cross-sectional view of line 5-5.

[0012] Figure 6 Yes Figure 3 The dotted box portion is an enlarged cross-sectional view.

[0013] Figure 7 It is a schematic cross-sectional view illustrating a memory cell array according to the second embodiment.

[0014] Figure 8 This is a schematic cross-sectional view illustrating a memory cell array according to the third embodiment.

[0015] Fig. 9 It is a schematic cross-sectional view illustrating a memory cell array according to a fourth embodiment.

[0016] Fig.10 This is a schematic cross-sectional view illustrating a memory cell array according to the fifth embodiment.

[0017] Fig.11 It is a schematic cross-sectional view illustrating a memory cell array according to the sixth embodiment.

[0018] Fig.12 This is a schematic cross-sectional view illustrating a memory cell array according to the seventh embodiment.

[0019] Fig.13 It is a schematic cross-sectional view illustrating a stepped portion 2s of a memory cell array according to the eighth embodiment.

[0020] Fig.14 It is a cross-sectional view showing an example of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0021] Fig.15 is a continuation of Fig.14 A cross-sectional view showing an example of a method for manufacturing a semiconductor storage device.

[0022] Fig.16 is a continuation of Fig.15 A cross-sectional view showing an example of a method for manufacturing a semiconductor storage device.

[0023] Fig.17 is a continuation of Fig.16 A cross-sectional view showing an example of a method for manufacturing a semiconductor storage device.

[0024] Fig.18 is a continuation of Fig.17 A cross-sectional view showing an example of a method for manufacturing a semiconductor storage device.

[0025] Fig.19 is a continuation of Fig.18A cross-sectional view showing an example of a method for manufacturing a semiconductor storage device.

[0026] Fig. 20 is a continuation of Fig.19 A cross-sectional view showing an example of a method for manufacturing a semiconductor storage device.

[0027] Fig.21 It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the sixth embodiment.

[0028] Fig. 22 It is a schematic cross-sectional view illustrating a memory cell array according to the ninth embodiment.

[0029] Fig.23 It is a schematic cross-sectional view illustrating a memory cell array according to the tenth embodiment.

[0030] Fig.24 It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the ninth embodiment.

[0031] Fig.25 is a continuation of Fig.24 A cross-sectional view showing an example of a method for manufacturing a semiconductor storage device.

[0032] Fig.26 is a continuation of Fig.25 A cross-sectional view showing an example of a method for manufacturing a semiconductor storage device.

[0033] Fig. 27 is a continuation of Fig.26 A cross-sectional view showing an example of a method for manufacturing a semiconductor storage device.

[0034] Fig.28 is a continuation of Fig. 27 A cross-sectional view showing an example of a method for manufacturing a semiconductor storage device.

[0035] Fig.29 It is a schematic cross-sectional view illustrating a memory cell array according to the eleventh embodiment.

[0036] Fig.30 It is a cross-sectional view showing a configuration example of the lower end portion of the columnar body according to the first embodiment.

[0037] Fig.31 It is a cross-sectional view showing another configuration example of the lower end portion of the columnar body.

[0038] Fig.32 It is a cross-sectional view showing another configuration example of the lower end portion of the columnar body.

[0039] Fig.33It is a cross-sectional view showing a structural example in which structural example 1 of the lower end portion of a columnar body is applied to a structural example of the ninth embodiment.

[0040] Fig.34 It is a cross-sectional view showing a structural example in which structural example 2 of the lower end portion of a columnar body is applied to a structural example of the ninth embodiment.

[0041] Fig.35 It is a cross-sectional view showing a structural example in which structural example 2 of the lower end portion of a columnar body is applied to a structural example of the ninth embodiment. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments are not intended to limit the present invention. The accompanying drawings are schematic or conceptual. In the specification and the accompanying drawings, the same elements are denoted by the same reference numerals.

[0043] (First embodiment)

[0044] Figure 1 1 is a cross-sectional view showing a configuration example of the semiconductor memory device 1 according to the first embodiment. Hereinafter, the stacking direction of the stacked body 20 is referred to as the Z direction. A direction intersecting, for example, orthogonal to the Z direction is referred to as the Y direction. A direction intersecting, for example, orthogonal to each of the Z direction and the Y direction is referred to as the X direction. In addition, in this specification, the Z direction is an example of the first direction. The X direction or the Y direction is an example of the second direction.

[0045] The semiconductor memory device 1 includes an array chip 2 having a memory cell array and a CMOS chip 3 having a CMOS circuit. The array chip 2 and the CMOS chip 3 are bonded to each other on a bonding surface B1 and are electrically connected to each other via wiring bonded to the bonding surface. Figure 1 , a state where the array chip 2 is mounted on the CMOS chip 3 is shown.

[0046] The CMOS chip 3 includes a substrate 30 , a transistor 31 , a via 32 , wirings 33 and 34 , and an interlayer insulating layer 35 .

[0047] The substrate 30 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 31 is an NMOS (N-Metal Oxide Semiconductor: N-type metal oxide semiconductor) or PMOS (P-Metal Oxide Semiconductor: P-type metal oxide semiconductor) transistor disposed on the substrate 30. The transistor 31, for example, constitutes a CMOS circuit for controlling a memory cell array of the array chip 2. A plurality of transistors 31 constitute a logic circuit such as a sense amplifier, a row decoder, and a column decoder. Semiconductor elements such as resistors and capacitors other than the transistors 31 may also be formed on the substrate 30.

[0048] The through hole 32 electrically connects the transistor 31 and the wiring 33, or the wiring 33 and the wiring 34. The wirings 33 and 34 form a multilayer wiring structure in the interlayer insulating layer 35. The wiring 34 is embedded in the interlayer insulating layer 35 and exposed at a substantially flush surface of the interlayer insulating layer 35. The wirings 33 and 34 are electrically connected to the transistor 31 and the like. For example, low-resistance metals such as copper and tungsten are used for the through hole 32 and the wirings 33 and 34. The interlayer insulating layer 35 covers the transistor 31, the through hole 32, and the wirings 33 and 34 to protect them. For example, an insulating layer such as a silicon oxide film containing silicon and oxygen is used for the interlayer insulating layer 35.

[0049] The array chip 2 includes a laminate 20 , a columnar body CL, a slit ST(LI), a source layer BSL, a metal layer 40 , a contact CCw, a contact plug 29 , and a bonding pad 50 .

[0050] The laminate 20 is provided above the transistor 31 and is located in the Z direction relative to the substrate 30. The laminate 20 is formed by alternately laminating a plurality of conductive films 21 and a plurality of insulating films 22 along the Z direction. The laminate 20 forms a memory cell array. The conductive film 21 uses a conductive metal such as tungsten. The insulating film 22 uses an insulating layer such as a silicon oxide film containing silicon and oxygen. The insulating film 22 insulates the conductive films 21 from each other. That is, a plurality of conductive films 21 are laminated in a mutually insulated state. The number of laminates of each of the conductive film 21 and the insulating film 22 is arbitrary. The insulating film 22 may also be, for example, a porous insulating layer or an air gap.

[0051] One or more conductive films 21 at the upper and lower ends of the laminate 20 in the Z direction function as a source side selection gate SGS and a drain side selection gate SGD, respectively. The conductive film 21 between the source side selection gate SGS and the drain side selection gate SGD functions as a word line WL. The word line WL is the gate electrode of the memory cell MC. The drain side selection gate SGD is the gate electrode of the drain side selection transistor. The source side selection gate SGS is provided in the upper region of the laminate 20. The drain side selection gate SGD is provided in the lower region of the laminate 20. The upper region refers to the region of the laminate 20 close to the CMOS chip 3 side, and the lower region refers to the region of the laminate 20 away from the CMOS chip 3 side (close to the metal layer 40 side).

[0052] The semiconductor memory device 1 has a plurality of memory cells MC connected in series between a source side selection transistor and a drain side selection transistor. A structure in which the source side selection transistor, the memory cell MC, and the drain side selection transistor are connected in series is called a "memory string" or a "NAND string". The memory string is connected to a bit line BL via a through hole 28, for example. The bit line BL is a wiring 23 provided under the laminate 20 (on the upper region side) and extending in the X direction.

[0053] A plurality of columns CL are provided in the laminate 20. The columns CL extend in the laminate 20 in the lamination direction (Z direction) of the laminate, and extend from the through hole 28 connected to the bit line BL to the source layer BSL. The internal structure of the column CL is described below. In addition, in this embodiment, since the column CL has a high aspect ratio, it is formed in two sections in the Z direction. However, there is no problem even if the column CL is one section or three or more sections.

[0054] In addition, although Figure 1 Although not shown in the figure, a plurality of gaps ST are provided in the laminate 20 (refer to Figure 2 ). The slit ST extends in the Y direction and penetrates the laminated body 20 in the lamination direction (Z direction) of the laminated body 20. The slit ST is filled with an insulating material such as a silicon oxide film containing silicon and oxygen, and the insulating material is formed in a plate shape. The slit ST electrically separates the conductive film 21 of the laminated body 20. Alternatively, the inner wall of the slit ST may be covered with an insulating layer such as a silicon oxide film, and a conductive material may be further embedded inside the insulating layer. In the above case, the conductive material also functions as a source wiring reaching the source layer BSL.

[0055] A source layer BSL is provided on the laminate 20 (on the lower area side). The source layer BSL is an example of the first semiconductor layer. The source layer BSL is provided corresponding to the laminate 20. The source layer BSL has a first surface F1 and a second surface F2 on the opposite side to the first surface F1. The laminate 20 (memory cell array) is provided on the first surface F1 side of the source layer BSL, and a metal layer 40 is provided on the second surface F2 side. The source layer BSL is commonly connected to one end of a plurality of columnar bodies CL, and supplies a common source potential to a plurality of columnar bodies CL located on the same memory cell array 2m. In other words, the source layer BSL functions as a common source electrode of the memory cell array 2m. The source layer BSL uses a conductive material such as doped polysilicon. The metal layer 40 uses a metal material such as copper, aluminum, or tungsten that has a lower resistance than the source layer BSL. In addition, 2s is a step portion of the conductive film 21 provided to connect the contact point to each conductive film 21. Figure 2 Described below.

[0056] On the other hand, a bonding pad 50 is provided in a region on the laminate 20 where the source layer BSL is not provided. The bonding pad 50 is connected to a metal wire or the like (not shown) and receives power supply or a signal from the outside of the semiconductor memory device 1. The bonding pad 50 is provided in a manner connected to one end of the contact plug 29 in the Z direction. The bonding pad 50 is connected to the transistor 31 of the CMOS chip 3 via the contact plug 29, the wiring 24, and the wiring 34. Therefore, the external power supplied from the bonding pad 50 is supplied to the transistor 31. Alternatively, a signal is supplied to the transistor 31 or the memory cell array 2m via the bonding pad 50.

[0057] The contact CCw is provided at the outer periphery of the laminate 20 and extends in the Z direction in the interlayer insulating layer 25. The contact CCw is electrically connected between the conductive film 21 (word line WL) and the wiring 24. The contact CCw is provided at the step portion 2s formed in a step shape at the end of the laminate 20 and is electrically connected to each conductive film 21. The contact CCw is provided to transfer the word line voltage from the CMOS chip 3 to each conductive film 21. For example, a low-resistance metal such as copper or tungsten is used for the contact CCw.

[0058] The contact plug 29 is provided at the outer periphery of the laminated body 20 so that the interlayer insulating layer 25 extends in the Z direction. The contact plug 29 is provided from the wiring 24 to the bonding pad 50 .

[0059] The contact plug 29 is electrically connected between the bonding pad 50 and the wiring 24. The contact plug 29 is used to supply the power supply voltage or signal from the bonding pad 50 to the array chip 2 or the CMOS chip 3. The contact plug 29 uses a low resistance metal such as copper or tungsten. The power supply voltage can be a power supply voltage VDD of a high level voltage, or a reference voltage (such as a ground voltage) VSS of a low level voltage. The signal can be a control signal from the outside, or it can be write data or read data.

[0060] In this embodiment, the array chip 2 and the CMOS chip 3 are formed separately and bonded with the bonding surface B1. Therefore, the transistor 31 is not provided in the array chip 2. In addition, the laminated body 20 (memory cell array) is not provided in the CMOS chip 3. The transistor 31 and the laminated body 20 are both located on the first surface F1 side of the source layer BSL. The transistor 31 is located on the opposite side of the second surface F2 of the source layer BSL where the metal layer 40 is located.

[0061] Below the laminate 20 (on the upper region side), a through hole 28, wiring 23, and wiring 24 are provided. The wiring 23 and 24 are embedded in the interlayer insulating layer 25. The wiring 24 is exposed on the surface of the interlayer insulating layer 25 in a substantially flush manner. The wiring 23 and 24 are electrically connected to the semiconductor body 210 of the columnar body CL, etc. The through hole 28, wiring 23, and wiring 24 use a low-resistance metal such as copper or tungsten. The interlayer insulating layer 25 covers the laminate 20, the through hole 28, wiring 23, and wiring 24 to protect them. The interlayer insulating layer 25 uses an insulating layer such as a silicon oxide film containing silicon and oxygen.

[0062] The interlayer insulating layer 25 and the interlayer insulating layer 35 are bonded to each other on the bonding surface B1 , and the wirings 24 and the wirings 34 are also bonded to each other at substantially flush planes on the bonding surface B1 . Thus, the array chip 2 and the CMOS chip 3 are electrically connected via the wirings 24 and the wirings 34 .

[0063] Figure 2: is a schematic top view showing the laminate 20. The laminate 20 includes a step portion 2s and a memory cell array 2m. The step portion 2s is provided at the end of the laminate 20. The memory cell array 2m is sandwiched or surrounded by the step portion 2s. The gap ST (LI) is provided from the step portion 2s at one end of the laminate 20 to the step portion 2s at the other end of the laminate 20 via the memory cell array 2m. The gap SHE is provided at least in the memory cell array 2m. The gap SHE is shallower than the gap ST (LI) and extends approximately parallel to the gap ST (LI). The gap SHE is used to electrically separate the conductive film 21 according to each drain side selection gate SGD. Alternatively, the gap ST may be electrically separated from the conductive film 21 of the laminate 20 and electrically connected to the source wiring LI of the source layer BSL. That is, the slit ST may be electrically separated from the conductive film 21 of the stacked body 20 constituting the memory cell array and electrically connected to the source wiring LI of the source layer BSL.

[0064] Depend on Figure 2 The portion of the laminate 20 sandwiched between the two slits ST shown is called a block. The block constitutes the minimum unit of data erasure, for example. The slit SHE is provided in the block. The laminate 20 between the slit ST and the slit SHE is called a finger. The drain side selection gate SGD is separated for each finger. Therefore, when writing and reading data, one finger in the block can be set to a selected state through the drain side selection gate SGD.

[0065] Figure 3 is a schematic cross-sectional view illustrating a memory cell array. Figure 4 Indicates along Figure 3 The cross section of line 4-4, Figure 5 Indicates along Figure 3 The cross section of the 5-5 line. Figure 6 Indicates that Figure 3 The dotted box 6 is an enlarged cross section of the part.

[0066] like Figure 3As shown, each of the plurality of columnar bodies CL is disposed in a memory hole MH, and the memory hole MH is disposed in the laminate 20. Each columnar body CL penetrates the laminate 20 from the upper end of the laminate 20 along the Z direction and is disposed in the laminate 20 and the source layer BSL. Each of the plurality of columnar bodies CL includes a semiconductor body 210, a memory film 220, and a core layer 230. The columnar body CL includes a core layer 230 disposed in the center portion thereof, a semiconductor body (semiconductor layer 210) disposed around the core layer 230, and a memory film 220 disposed around the semiconductor body 210. The semiconductor body 210 extends in the lamination direction (Z direction) in the laminate 20. The semiconductor body 210 is electrically connected to the source layer BSL. The memory film 220 is disposed between the semiconductor body 210 and the conductive film 21, and has a charge capture film. A plurality of columnar bodies CL, one of which is selected from each finger, are connected via Figure 1 The through holes 28 are connected to one bit line BL in common. Each of the pillars CL is provided in a region of the memory cell array 2m, for example.

[0067] like Figure 3 and Figure 6 As shown, a blocking insulating layer 21a and a barrier film 21b constituting a part of the memory film 220 are provided between the conductive film 21 and the insulating film 22, and between the conductive film 21 and the blocking insulating layer 224. The blocking insulating layer 21a as the third insulator portion is provided between the conductive film 21 and the insulating film 22, and between the conductive film 21 and the blocking insulating layer 224 or the charge trapping film 222. The blocking insulating layer 21a is, for example, silicon oxide or metal oxide. An example of the metal oxide is aluminum oxide containing aluminum and oxygen. The blocking insulating layer 21a suppresses reverse tunneling of charges from the conductive film 21 to the memory film 220 side. For example, when the conductive film 21 is tungsten, the barrier film 21b is, for example, a laminated film of titanium nitride and titanium. The barrier film 21b is a conductive material that improves the adhesion between the conductive film 21 and the blocking insulating layer 21a. For the barrier film 21b, a conductive metal compound such as a laminated film of titanium nitride and titanium is used.

[0068] like Figure 4 and Figure 5 As shown, the shape of the memory hole MH in the XY plane is, for example, a circle or an ellipse. The center of the memory hole MH has a core layer 230, and around the core layer 230, a semiconductor body 210 and a memory film 220 are arranged.

[0069] The shape of the semiconductor body 210 is, for example, cylindrical. The semiconductor body 210 uses, for example, polycrystalline silicon. The semiconductor body 210 is, for example, undoped silicon. In addition, the semiconductor body 210 may also be p-type silicon. The semiconductor body 210 becomes a channel for each of the drain side selection transistor STD, the memory cell MC, and the source side selection transistor STS. One end of a plurality of semiconductor bodies 210 in the same memory cell array 2m is commonly connected to the source layer BSL.

[0070] The memory film 220 is provided between the inner wall of the memory hole MH and the semiconductor body 210. The shape of the memory film 220 is, for example, a cylindrical shape. A plurality of memory cells MC have a storage region between the semiconductor body 210 and the conductive film 21 serving as the word line WL, and are stacked in the Z direction. The memory film 220 includes, for example, Figure 4 The blocking insulating layer 224, Figure 5 The cap insulating layer 221, the charge trapping film 222 (222a, 222b) and the tunnel insulating layer 223 are formed. Each of the semiconductor body 210, the charge trapping film 222 and the tunnel insulating layer 223 extends in the Z direction.

[0071] like Figure 6 As shown, the cover insulating layer 221 as the fourth insulating portion is provided between a portion (222a) of the charge trapping film 222 as the second insulating portion and the plurality of insulating films 22. The cover insulating layer 221 is provided intermittently in the Z direction. The cover insulating layers 221 adjacent to each other in the Z direction are separated from a portion (222b) of the charge trapping film 222 by the blocking insulating layer 224.

[0072] In the memory hole MH, a cap insulating layer 221 and a blocking insulating layer 224 are provided around the charge trap film 222. The cap insulating layer 221 is a film different from the charge trap film, and an insulating layer such as silicon oxide containing silicon and oxygen, HfO, or ZrO is used.

[0073] The cap insulating layer 221 is provided between the blocking insulating layers 224 adjacent to each other in the Z direction and between the second charge trapping films 222 b adjacent to each other in the Z direction. The blocking insulating layer 221 is thicker than the blocking insulating layer 224 in the X direction or the Y direction.

[0074] The blocking insulating layer 224 is provided between the conductive film 21 and the charge trapping film 222. For example, an insulating layer such as silicon oxide containing silicon and oxygen is used for the blocking insulating layer 224. The blocking insulating layer 224 suppresses reverse tunneling of charges from the conductive film 21 to the memory film 220 side together with the blocking insulating layer 21a.

[0075] The charge capture film 222 as the second insulator portion is provided between the laminate 20 and the tunnel insulating layer 223. The charge capture film 222 is provided between the cover insulating layer 221 and the tunnel insulating layer 223, and between the blocking insulating layer 224 and the tunnel insulating layer 223. The charge capture film 222 includes a first charge capture film 222a and a second charge capture film 222b. The first charge capture film 222a is provided between the second charge capture film 222b or between the cover insulating layer 221 and the tunnel insulating layer 223, and extends continuously in the Z direction. The second charge capture film 222b is provided between the conductive film 21 or the blocking insulating layer 224 and the first charge capture film 222a, and is provided intermittently in the Z direction. The first and second charge capture films 222a and 222b use an insulating layer such as silicon nitride containing silicon and nitrogen.

[0076] The first and second charge trapping films 222a and 222b both have a trapping site for trapping charges in the film. That is, the first and second charge trapping films 222a and 222b are formed as one charge trapping film 222. In the charge trapping film 222, the first portion 222_1 sandwiched between the conductive film 21 (including the barrier film 21b) that becomes the word line WL and the semiconductor body 210, and / or between the blocking insulating layer 21a and the semiconductor body 210 is formed of the first and second charge trapping films 222a and 222b. The first portion 222_1 corresponding to each memory cell MC accumulates charges and functions as a storage area of ​​each memory cell MC. In the charge trapping film 222, the second portion 222_2 disposed between the insulating film 22 (cover insulating layer 221) and the tunnel insulating layer 223 is formed of the first charge trapping film 222a. The second portion 222_2 is disposed between adjacent first portions 222_1 in the Z direction. The thickness T2 of the second portion 222_2 of the charge capture film 222 in the Y direction or the X direction is thinner than the thickness T1 of the first portion 222_1 in the Y direction or the X direction by the amount of the thickness of the second charge capture film 222b. Thus, the first portions 222_1 of the plurality of adjacent memory cells MC in the Z direction are separated, and the charge accumulated in the charge capture film can be suppressed from moving in the first portions 222_1 adjacent in the Z direction. Thus, the interference of data between the plurality of adjacent memory cells MC in the Z direction can be suppressed. In addition, by making the capacitance of the first portion 222_1 larger than that of the second portion 222_2, each memory cell MC can accumulate more charge. The threshold voltage of the memory cell MC changes depending on whether there is charge in the first portion 222_1 of the charge capture film 222 or the amount of charge captured in the first portion 222_1. Thus, the memory cell MC can store data.

[0077] The tunnel insulating layer 223 as the first insulating portion is provided between the laminate 20 and the semiconductor body 210. More specifically, the tunnel insulating layer 223 is provided between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating layer 223 uses an insulating layer such as silicon oxide containing silicon and oxygen, or a silicon oxynitride film containing silicon oxide and silicon nitride. The tunnel insulating layer 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor body 210 to the charge trapping film 222 (writing operation), and when holes are injected from the semiconductor body 210 to the charge trapping film 222 (erasing operation), the electrons and holes respectively pass through the potential barrier of the tunnel insulating layer 223 (tunneling).

[0078] The core layer 230 is embedded in the inner space of the cylindrical semiconductor body 210. The core layer 230 is, for example, columnar. The core layer 230 is made of an insulating material such as silicon oxide containing silicon and oxygen.

[0079] The blocking insulating layer 21a as the fifth insulator portion is provided between the blocking insulating layer 224 and the barrier film 21b or the conductive film 21. The blocking insulating layer 21a is also provided between the insulating film 22 and the barrier film 21b or the conductive film 21. The blocking insulating layer 21a is formed of an insulating material (High-k (high dielectric constant) material) having a higher dielectric constant than the blocking insulating layer 224. For example, the blocking insulating layer 21a is made of an aluminum oxide film (Al2O3) having a higher dielectric constant than the silicon oxide film. 2 O 3 ).

[0080] The barrier film 21b is provided between the conductive film 21 and the blocking insulating layer 21a. As described above, when the conductive film 21 is tungsten, the barrier film 21b is, for example, a laminated film of titanium nitride and titanium. The barrier film 21b is very thin compared to the conductive film 21, and it is considered that it functions as a part of the conductive film 21. Therefore, there is a case where the conductive film 21 includes the barrier film 21b.

[0081] If the boundary between the blocking insulating layer 21a and the blocking insulating layer 224 is set to B21a_224, and the boundary between the insulating film 22 and the cover insulating layer 221 is set to B22_221, then Figure 6 As shown, the boundary B21a_224 is located at the same position as the boundary B22_221 or at a position closer to the inner side (center side) of the memory hole MH than the boundary B22_221 in the XY plane. That is, the radius R21a_224 of the memory hole MH or the columnar body CL of the boundary B21a_224 (reference Figure 4 ) in the XY plane, the radius R22_221 of the memory hole MH or the columnar body CL of the boundary B22_221 (reference Figure 5) is equal to or smaller than it. In addition, when the boundary B21a_224 and the boundary B22_221 are located at the same position, the boundary B21a_224 and the boundary B22_221 overlap in the XY plane.

[0082] According to the present embodiment, the boundary B21a_224 overlaps with the boundary B22_221 in the XY plane, or is located closer to the center Cmh side of the memory hole MH than the boundary B22_221. As a result, the conductive film 21 protrudes toward the memory hole MH and the columnar body CL, and the charge accumulated in the first part 222_1 of the charge capture film 222 can be well controlled. In addition, since the conductive film 21 protrudes toward the center Cmh of the memory hole MH from the side surface (boundary B22_221) of the memory hole MH at the beginning of formation, the embedding property of the metal material of the conductive film 21 will not deteriorate even if the distance between adjacent memory holes MH in the same WL plane is reduced. Therefore, even if the interval between multiple adjacent memory holes MH in the XY plane is narrowed, the material of the conductive film 21 can be embedded in the space between the insulating films 22, and the replacement step will not be adversely affected. As a result, the cell size of the memory cell array 2m can be reduced. In addition, the manufacturing method of the present embodiment is described below.

[0083] (Second embodiment)

[0084] Figure 7 is a schematic cross-sectional view of a memory cell array illustrating the second embodiment. In the seventh embodiment, the insulating film 22 is composed of a laminated film of insulating films 22a and 22b. The insulating film 22a as the second insulating film is disposed in the central portion of the insulating film 22 and is composed of, for example, an insulating material such as a silicon oxide film. The insulating film 22b is disposed on both sides of the insulating film 22a in the Z direction so as to sandwich the insulating film 22a. For example, the insulating film 22b uses an insulating material such as SiOC that makes the silicon oxide film contain carbon. When SiOC is used as the insulating film 22b, the elemental ratio of carbon can be adjusted in such a way that the etching rate of hydrofluoric acid is lower than that of the silicon oxide film. The carbon density of SiOC is, for example, 5E20 to 1E22 atoms / cm 3 .

[0085] Figure 7 In the cross section in the Z direction shown, the insulating film 22a is sandwiched by the insulating film 22b above and below the Z direction. The insulating film 22b is provided between the insulating film 22a and the block insulating layer 21a.

[0086] The other configurations of the second embodiment may be the same as those of the first embodiment. Therefore, the second embodiment can obtain the same effects as those of the first embodiment. In addition, the manufacturing method of the second embodiment is described below.

[0087] (Third embodiment)

[0088] Figure 8 2 is a schematic cross-sectional view illustrating a memory cell array according to Embodiment 3. In Embodiment 3, the insulating film 22 is entirely made of the material of the insulating film 22b described above. For example, the insulating film 22 uses an insulating material such as SiOC in which carbon is contained in a silicon oxide film.

[0089] The other configurations of the third embodiment may be the same as those of the first embodiment. Thus, the third embodiment can obtain the same effects as those of the first embodiment. In addition, the manufacturing method of the third embodiment will be described below.

[0090] (Fourth embodiment)

[0091] Fig. 9 2 is a schematic cross-sectional view of a memory cell array according to the fourth embodiment. In the fourth embodiment, the insulating film 22b is provided at the center of the insulating film 22. The insulating film 22a is provided on both sides of the insulating film 22b in the Z direction so as to sandwich the insulating film 22b. The insulating film 22a is provided around the insulating film 22b. The materials of the insulating films 22a and 22b may be the same as those of the second embodiment.

[0092] Fig. 9 In the cross section in the Z direction shown, the insulating film 22b is sandwiched by the insulating film 22a above and below the Z direction. The insulating film 22a is provided between the insulating film 22b and the block insulating layer 21a.

[0093] In this manner, among the insulating films 22 , the insulating films 22 b may be sandwiched by the insulating films 22 a in the upper and lower parts in the Z direction.

[0094] The other configurations of the fourth embodiment may be the same as those of the first embodiment. Therefore, the fourth embodiment can obtain the same effects as those of the first embodiment. In addition, the manufacturing method of the fourth embodiment will be described below.

[0095] (Fifth embodiment)

[0096] Fig.10 2 is a schematic cross-sectional view of a memory cell array illustrating the fifth embodiment. In the fifth embodiment, the first charge capture film 222a is not provided. Therefore, the charge capture film 222 is provided between the conductive film 21 or the blocking insulating layer 21a and the tunnel insulating layer 223, but is not provided between the insulating film 22 or the cover insulating layer 221 and the tunnel insulating layer 223. Thus, the charge capture film 222 is completely separated by the cover insulating layer 221 in the Z direction for each memory cell MC. Thus, the movement of charges in the charge capture film 222 of a plurality of memory cells MC adjacent to each other in the Z direction can be further reliably suppressed.

[0097] On the other hand, the seed insulating film 223a is disposed between the charge trapping film 222 and the tunnel insulating film 223 instead of the first charge trapping film 222a. The seed insulating film 223a may be a part of the tunnel insulating layer 223, and may be made of a high dielectric material such as an aluminum oxide film.

[0098] The other configurations of the fifth embodiment may be the same as those of the first embodiment. Thus, the fifth embodiment can obtain the same effects as those of the first embodiment. In addition, the fifth embodiment can be combined with any one of the second to fourth embodiments. Thus, the fifth embodiment can also obtain the effects of any one of the second to fourth embodiments.

[0099] (Sixth Implementation Method)

[0100] Fig.11 2 is a schematic cross-sectional view of a memory cell array illustrating the sixth embodiment. In the sixth embodiment, in the cross section in the Z direction, the cover insulating layer 221 has a T-shape with the -Y direction set upward. Accordingly, the second charge capture film 222b has a T-shape with the +Y direction set upward. Therefore, in the cross section in the Z direction, the length La at the boundary between the first portion 222_1 of the charge capture film 222 and the blocking insulating layer 224 is longer than the length Lb of the first portion 222_1 on the extension line of the boundary between the second portion 222_2 of the charge capture film 222 and the cover insulating layer 221. In addition, the length Lc at the boundary between the first portion 222_1 and the tunnel insulating layer 223 is longer than the length Lb. One end of the length Lc is located at the boundary between the insulating film 22 and the blocking insulating layer 21a in the Z direction, and the other end is located at the boundary between the insulating film 22 and the blocking insulating layer 21a adjacent thereto. Thus, the side surface of the first portion 222_1 in the Z direction has a recessed portion, and a part of the cover insulating layer 221 enters the recessed portion.

[0101] This has the effect of locally widening the distance between adjacent CTs, thereby reducing the parasitic capacitance generated between adjacent charge storage layers 222 b .

[0102] The other configurations of the sixth embodiment may be the same as those of the first embodiment. Therefore, the sixth embodiment can obtain the same effects as those of the first embodiment. In addition, the sixth embodiment can be combined with any one of the second to fifth embodiments. Therefore, the sixth embodiment can also obtain the effects of any one of the second to fifth embodiments.

[0103] (Seventh Implementation Method)

[0104] Fig.122 is a schematic cross-sectional view of a memory cell array according to the seventh embodiment. In the seventh embodiment, the cap insulating layer 221 is composed of a laminated film of a plurality of insulating layers 221a and 221b. The materials of the insulating layers 221a and 221b may be different from each other. For example, the insulating layer 221a may be a silicon oxide film containing silicon and oxygen, a hafnium oxide film containing hafnium and oxygen, or a zirconium oxide film containing zirconium and oxygen. The insulating layer 221b may be an aluminum oxide film containing aluminum and oxygen, or a hafnium oxide film containing hafnium and oxygen.

[0105] The other configurations of the seventh embodiment may be the same as those of the first embodiment. Therefore, the seventh embodiment can obtain the same effects as those of the first embodiment. In addition, the seventh embodiment can be combined with any one of the second to sixth embodiments. Thus, the seventh embodiment can also obtain the effects of any one of the second to sixth embodiments.

[0106] (Eighth Implementation Method)

[0107] Fig.13 : is a schematic cross-sectional view of a step portion 2s of a memory cell array according to the eighth embodiment. The step portion 2s of the eighth embodiment corresponds to the step portion 2s of the memory cell array according to the second embodiment. In the step portion 2s, the conductive film 21 and the insulating film 22 are formed in a step shape. In each tread (contact area of ​​the contact CCw) STP of the step portion 2s, the insulating film 22 covers the conductive film 21. The insulating film 22a of the insulating film 22 is disposed at the center of the insulating film 22 in the Z direction. The insulating film 22b is disposed on both sides of the insulating film 22a in the Z direction so as to sandwich the insulating film 22a. The material of the insulating films 22a and 22b may be different from the material of the insulating film 22a. Figure 7 The insulating films 22a and 22b are the same.

[0108] In the step portion 2 s , the plurality of contacts CCw penetrate the plurality of insulating films 22 in the contact region exposed from the laminate 20 , and are connected to the plurality of conductive films 21 located under each of the insulating films 22 .

[0109] The insulating film 22b includes insulating films 22b_1 and 22b_2 sandwiching the insulating film 22a from both sides in the Z direction. The insulating film 22b_1 is provided between the conductive film 21 and the insulating film 22a. The insulating film 22b_2 is located on the insulating film 22a and provided between the insulating film 22a and the interlayer insulating layer 25. Since the insulating film 22b_2 is etched when the step portion 2s is formed, it is thinner than the insulating film 22b_1. In other words, the insulating film 22b_1 is thicker than the insulating film 22b_2.

[0110] Next, the manufacturing method of the above-mentioned embodiment will be described.

[0111] Figures 14 to 20 It is a cross-sectional view showing an example of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0112] First, if Fig.14 As shown, a sacrificial film 21s and an insulating film 22 are alternately stacked in the Z direction on a semiconductor substrate 10 using, for example, a CVD (Chemical Vapor Deposition) method. Thus, a stacked body 20 stacked in the Z direction is formed. The sacrificial film 21s is, for example, an insulating film such as a silicon nitride film containing silicon and nitrogen. The sacrificial film 21s is replaced with the material of the conductive film 21 in a subsequent step. The insulating film 22 becomes an interlayer insulating layer between the conductive films 21. The insulating film 22 is a stacked film in which an insulating film 22a is sandwiched between two insulating films 22b. The insulating film 22a is, for example, a silicon oxide film containing silicon and oxygen. The insulating film 22b is, for example, a SiOC film containing silicon, oxygen and carbon. If the sacrificial films 21s and the insulating films 22 are alternately stacked, the sacrificial films 21s, the insulating films 22a, and 22b are stacked in the order of 22b, 22a, 22b, 21s, 22b, 22a, 22b, 21s, . . . .

[0113] Then, if Fig.15 As shown, a memory hole MH extending in the Z direction is formed in the laminate 20 using, for example, photolithography and RIE (Reactive Ion Etching) techniques. The memory hole MH penetrates the laminate 20 constituting the insulating film 22 and the sacrificial film 21s.

[0114] Then, if Fig.16 As shown, the ALD (Atomic Layer Deposition) method or the CVD method is used to deposit a cap insulating layer 221, a charge trapping film 222a, a tunnel insulating layer 223, and a semiconductor body 210 on the inner wall of the memory hole MH. The core layer 230 is embedded inside the semiconductor body 210 in the memory hole MH. The charge trapping film 222a is, for example, an insulating film such as a silicon nitride film containing silicon and nitrogen, and functions as a seed for the charge trapping film 222b to be selectively grown later. The cap insulating layer 221 and the tunnel insulating layer 223 are insulating layers such as a silicon oxide film containing silicon and oxygen. The tunnel insulating layer 223 can also be a silicon nitride oxide layer containing silicon, oxygen, and nitrogen. The semiconductor body 210 is a semiconductor layer containing a semiconductor such as polycrystalline silicon.

[0115] Next, the step of replacing the sacrificial film 21s is performed. Fig.17 As shown, the sacrificial film 21s is selectively etched and removed using a solution or gas containing phosphoric acid. The sacrificial film 21s is removed through the slit ST formed in the laminate 20 (see Figure 2 Thus, the cover insulating layer 221 is exposed in the space 21h after the sacrificial film 21s is removed.

[0116] Then, if Fig.18 As shown, the cover insulating layer 221 is isotropically etched using a solution or gas containing hydrofluoric acid, thereby exposing the charge trap film 222a in the space 21h.

[0117] Then, if Fig.19 As shown, the charge trapping film 222a exposed in the space 21h is used as a seed crystal to grow the charge trapping film 222b on the surface of the charge trapping film 222a. As a result, the charge trapping film 222 is thicker than the charge trapping film 222a between the cap insulating layer 221 and the tunnel insulating layer 223 in the formation region of the conductive film 21, that is, in the space 21h.

[0118] Then, if Fig. 20 As shown, a blocking insulating layer 224 is formed on the charge trap film 222b.

[0119] Next, using the ALD method or the CVD method, a blocking insulating layer 21a (for example, an insulating layer such as an aluminum oxide film containing aluminum and oxygen) and a barrier film 21b (for example, a multilayer film or a single layer film of titanium nitride and titanium) are deposited on the inner wall of the space 21h. Furthermore, a conductive film 21 (for example, tungsten) is embedded inside the barrier film 21b. By this replacement step, the sacrificial layer 21s is replaced by the conductive film 21. Thus, a Figure 7 The slit ST is filled with a silicon oxide film, or a silicon oxide film and a metal material.

[0120] Afterwards, the formation Figure 1 The array chip 2 is completed by forming the through hole 28, wiring 24, etc. The CMOS chip 3 is formed separately from the array chip 2. The array chip 2 and the CMOS chip 3 are bonded to each other at the bonding surface B1. Furthermore, by forming the metal layer 40 and the bonding pad 50, etc., the semiconductor storage device 1 is completed.

[0121] The inner wall surface when the memory hole MH is formed is the boundary between the cover insulating layer 221 and the insulating film 22. Therefore, the diameter of the memory hole MH can also be said to be the diameter at the boundary between the cover insulating layer 221 and the insulating film 22. In contrast, the conductive film 21, the barrier film 21b, and the blocking insulating layer 21a formed in the space 21h are Figure 6 As shown in FIG. 1 , the boundary between the cover insulating layer 221 and the insulating film 22 protrudes toward the center Cmh side of the memory hole MMH. Fig. 20 As shown, in the replacement step, the space 21h can be kept large, and the material of the conductive film 21 can be easily embedded in the space 21h. Therefore, the interval between the adjacent memory holes MH can be narrowed. As a result, the cell size of the memory cell array 2m can be reduced.

[0122] The semiconductor memory device of the third embodiment is Fig.14In the described steps, the insulating film 22 may be entirely formed of the insulating film 22b (eg, SiC film). The other steps of the third embodiment may be the same as those of the first embodiment.

[0123] The semiconductor memory device of the fourth embodiment is Fig.14 In the described steps, the entire insulating film 22 may be formed of the insulating film 22b (eg, SiOC film). Furthermore, the insulating film 22b may be partially oxidized. The other steps of the fourth embodiment may be the same as those of the first embodiment.

[0124] The semiconductor memory device of the fifth embodiment is Fig.16 In the steps described above, the charge trapping film 222a (the seed of the charge trapping film 222b) can be omitted and the seed insulating film 223a can be formed. Fig.18 and Fig.19 The charge capture film 222b is a seed crystal, but as long as it is replaced, Fig.10 The other steps of the fifth embodiment may be the same as those of the first embodiment.

[0125] The semiconductor memory device of the sixth embodiment is Fig.18 In the described steps, the cover insulating layer 221 located on the charge trap film 222 a in the space 21 h is not completely removed, but a portion thereof remains. Fig.21 FIG. 2 is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the sixth embodiment. Fig.21 As shown in FIG. 1 , in the center of the space 21h in the Z direction, the cover insulating layer 221 is first removed. In the end of the space 21h in the Z direction, etching is stopped while the cover insulating layer 221 is left. Fig.19 The next step is to obtain Fig.11 The other steps of the sixth embodiment may be the same as those of the first embodiment.

[0126] The semiconductor memory device of the seventh embodiment is Fig.16 In the described steps, the cover insulating layer 221 may be a laminated film of a plurality of insulating layers 221a and 221b made of different materials. The other steps of the seventh embodiment may be the same as those of the first embodiment.

[0127] (Ninth Implementation Method)

[0128] Fig. 222 is a schematic cross-sectional view of a memory cell array according to the ninth embodiment. In the ninth embodiment, the cover insulating layer 221 is composed of a laminated film of a plurality of insulating layers 221a, 221b, and 221c. The insulating layer 221b is sandwiched between the insulating layer 221a and the insulating layer 221c and is made of a material different from that of the insulating layers 221a and 221c. In addition, for example, the insulating layer 221b is made of Al 2 O 3 or HfO. For example, SiO 2 , HfO, or ZrO is used for the insulating layers 221 a and 221 c. For example, a silicon nitride film containing silicon and nitrogen is used for the charge trap film 222 .

[0129] The insulating layers 221b and 221c are shorter in the Z direction than the insulating layer 221a. In addition, both side surfaces in the Z direction of the insulating layer 221a are in contact with the blocking insulating layer 224. On the other hand, both side surfaces in the Z direction of the insulating layers 221b and 221c are in contact with the charge trapping film 222b (first portion 222_1).

[0130] Furthermore, the lengths (thicknesses) of the conductive film 21, the barrier film 21b, and the blocking insulating layer 21a in the Z direction are equal to or shorter than the length of the charge trap film 222b in the Z direction. Thus, the charge trap film 222 can accumulate more charges.

[0131] Between a plurality of charge trap films 222 b adjacent to each other in the Z direction, an insulating layer 221 b having a higher dielectric constant than the charge trap film 222 b is provided.

[0132] The other configurations of the ninth embodiment may be the same as those of the first embodiment. Therefore, the ninth embodiment can obtain the same effects as those of the first embodiment. In addition, the ninth embodiment can be combined with any one of the second to sixth embodiments. Thus, the ninth embodiment can also obtain the effects of any one of the second to sixth embodiments.

[0133] (10th embodiment)

[0134] Fig.23 1 is a schematic cross-sectional view of a memory cell array according to the tenth embodiment. In the tenth embodiment, the cap insulating layer 221 is composed of a laminated film of a plurality of insulating layers 221a and 221b. The insulating layer 221b is sandwiched between the insulating layer 221a and the charge trapping film 222a, and the material is different from that of the insulating layer 221a. In addition, the insulating layer 221b is composed of a material having a higher dielectric constant than the insulating layer 221a and the charge trapping film 222. For example, the material of the insulating layers 221a and 221b may be the same as that described in the ninth embodiment.

[0135] The insulating layer 221b is shorter in the Z direction than the insulating layer 221a. Both side surfaces in the Z direction of the insulating layer 221a are in contact with the blocking insulating layer 224. Both side surfaces in the Z direction of the insulating layer 221b are in contact with the charge trapping film 222b.

[0136] Between a plurality of charge trapping films 222 b adjacent to each other in the Z direction, an insulating layer 221 b having a higher dielectric constant than the charge trapping film 222 b is provided.

[0137] The other configurations of the tenth embodiment may be the same as those of the first embodiment. Therefore, the tenth embodiment can obtain the same effects as those of the first embodiment. In addition, the tenth embodiment can be combined with any one of the second to sixth embodiments. Thus, the tenth embodiment can also obtain the effects of any one of the second to sixth embodiments.

[0138] Next, the manufacturing method of the ninth embodiment is described.

[0139] Figure 24 to Figure 28 It is a cross-sectional view showing an example of a method for manufacturing a semiconductor memory device according to the ninth embodiment.

[0140] First, after reference Fig.14 and Fig.15 Instructions for use.

[0141] Then, if Fig.24 As shown, the cap insulating layer 221 is deposited on the inner wall of the memory hole MH by using the ALD method or the CVD method. At this time, the cap insulating layer 221 is deposited on the inner wall of the memory hole MH in the order of insulating layers 221a, 221b, and 221c.

[0142] Next, the charge trap film 222 a and the like are deposited on the inner wall of the memory hole MH in the same manner as in the first embodiment.

[0143] Next, the step of replacing the sacrificial film 21s is performed. Fig.25 As shown, the sacrificial film 21s is selectively etched and removed using a solution or gas containing phosphoric acid. The sacrificial film 21s is removed through the slit ST formed in the laminate 20 (see Figure 2 ) is performed. As a result, the insulating layer 221a is exposed in the space 21h after the sacrificial film 21s is removed.

[0144] Then, if Fig.26 As shown, the insulating layer 221a is isotropically etched. Thus, the insulating layer 221a exposed in the space 21h is selectively removed. At this time, the insulating layer 221b functions as an etching stopper. In addition, the processing performed in the space 21h is performed through the slit ST.

[0145] Then, if Fig. 27As shown, the insulating layer 221b is isotropically etched. Thus, the insulating layer 221b exposed in the space 21h is removed. At this time, the insulating layer 221c functions as an etching stopper. The insulating layer 221b is recessed in the Z direction, and the length in the Z direction is shorter than that of the insulating layer 221a.

[0146] Moreover, if Fig.28 As shown, the insulating layer 221c is further isotropically etched. Thus, the insulating layer 221c exposed in the space 21h is removed. In the insulating layer 221c, the insulating layer 221b is etched as a mask, and the length in the Z direction is shorter than that of the insulating layer 221a. Thus, the cap insulating layer 221 exposed in the space 21h is removed, and the charge capture film 222a is exposed in the space 21h.

[0147] Afterwards, after reference Fig.19 and Fig. 20 The steps described, Fig. 22 The semiconductor memory device 1 shown is completed. When the charge trap film 222b is selectively grown on the charge trap film 222a as a seed crystal, the side surfaces of the insulating layers 221b and 221c are in contact with the charge trap film 222b.

[0148] In addition, if the insulating layer 221c of the cover insulating layer 221 is omitted, it is possible to form Fig.23 The semiconductor memory device 1 is shown.

[0149] According to the ninth embodiment, the cover insulating layer 221 is composed of a laminated film of insulating layers 221a to 221c. The insulating layer 221b functions as an etching stopper in the etching step of the insulating layer 221a. The insulating layer 221c functions as an etching stopper in the etching step of the insulating layer 221b.

[0150] (11th embodiment)

[0151] Fig.29 11 is a schematic cross-sectional view illustrating a memory cell array according to the 11th embodiment. Fig. 22 In the structure of FIG. 1 , the insulating film 22 is composed of a laminated film of insulating films 22a and 22b. The insulating film 22a is provided at the center of the insulating film 22 and is composed of an insulating material such as a silicon oxide film. The insulating film 22b is provided on both sides of the insulating film 22a in the Z direction so as to sandwich the insulating film 22a. For example, the insulating film 22b uses an insulating material such as SiOC in which carbon is contained in the silicon oxide film.

[0152] The other configurations of the eleventh embodiment may be the same as those of the ninth embodiment. Therefore, the eleventh embodiment can obtain the same effects as those of the ninth embodiment.

[0153] (Configuration Example 1 of the Lower End of the Columnar Body)

[0154] Next, the structure of the lower end portion of the columnar body CL will be described.

[0155] Fig.30 It is a cross-sectional view showing an example of the structure of the lower end CLb of the columnar body CL of the first embodiment. The structure of the memory cell MC may be the same as that of the memory cell MC of the first embodiment. The lower end CLb of the columnar body CL reaches into the source layer BSL. The semiconductor body 210 of the columnar body CL is electrically connected to the source layer BSL in the lower end CLb of the columnar body CL. The source layer BSL is, for example, doped polysilicon and is directly connected to the semiconductor body 210.

[0156] In Configuration Example 1, the cap insulating layer 221, the charge trapping film 222a, and the tunnel insulating layer 223 are laterally removed through the slits ST to expose the semiconductor body 210. Then, a conductive material such as doped polysilicon is embedded through the slits ST to form a source layer BSL.

[0157] As mentioned above, Figure 6 The radius R21a_224 of the memory hole MH or the columnar body CL at the boundary B21a_224 is equal to or smaller than the radius R22_221 of the memory hole MH or the columnar body CL at the boundary B22_221.

[0158] Moreover, if Fig.30 As shown, if the radius of the memory hole MH or the columnar body CL at the lower end CLb is set to Rbsl_221, then the radius R21a_224 is equal to or smaller than the radius Rbsl_221. Since the columnar body CL becomes thinner as it approaches the lower end CLb, at least in the memory cell MC closest to the lower end CLb, the diameter R21a_224×2 of the columnar body CL is equal to or smaller than the diameter Rbsl_221×2 of the outer periphery of the cover insulating layer 221 at the lower end CLb.

[0159] When the diameter R21a_224×2 of the columnar body CL in the memory cell MC is small, the space 21h can be maintained large in the replacement step. This can narrow the interval between the adjacent memory holes MH, which helps to reduce the size of the memory cell array 2m.

[0160] Fig.30 The structure can also be applied to any one of the second to tenth embodiments.

[0161] (Configuration Example 2 of the Lower End of the Columnar Body)

[0162] Fig.31 and Fig.322 is a cross-sectional view showing another configuration example of the lower end CLb of the columnar body CL. The configuration of the memory cell MC may be the same as that of the memory cell MC of the first embodiment. In configuration example 2, the source layer BLS uses a conductive metal material such as tungsten. The barrier metal BM uses a conductive metal compound such as a laminated film of titanium nitride and titanium. In addition, the barrier metal BM and the source layer BSL are sometimes collectively referred to as the source layer BLS.

[0163] The lower end of the columnar body CL is removed, and a part of the core layer 230 is removed from the lower end. The source layer BSL and the barrier metal BM enter the region of the core layer 230 in the memory hole MH. Thus, the semiconductor body 210 is electrically connected to the source layer BSL.

[0164] In the configuration example 2, the cap insulating layer 221, the charge trapping film 222a, the tunnel insulating layer 223, and the semiconductor body 210 are removed from the lower end of the columnar body CL, and a portion of the core layer 230 located inside the semiconductor body 210 is etched. As a result, the semiconductor body 210 is exposed inside the memory hole MH. Next, the materials of the barrier metal BM and the source layer BSL are embedded inside the memory hole MH, and the semiconductor body 210 is connected to the barrier metal BM and the source layer BSL.

[0165] In the configuration example 2, Figure 6 The radius R21a_224 of the memory hole MH or the columnar body CL at the boundary B21a_224 is equal to or smaller than the radius R22_221 of the memory hole MH or the columnar body CL at the boundary B22_221.

[0166] Fig.32 2 is a cross-sectional view showing another example of the structure of the lower end CLb of the dummy column CLd. The dummy column CLd as the second column has a structure substantially the same as that of the column CL. However, the semiconductor body 210 is electrically separated from the source layer BSL located thereunder. Therefore, the dummy column CLd is not used to store data. In other words, the lower end of the dummy column CLd is electrically separated from the source layer BSL located thereunder. Fig.31 The source layer BSL is in contact with the cover insulating layer 221 .

[0167] In the virtual columnar body CLd, Figure 6 The radius R21a_224 of the memory hole MH or the columnar body CL at the boundary B21a_224 is equal to or smaller than the radius R22_221 of the memory hole MH or the columnar body CL at the boundary B22_221.

[0168] Moreover, if Fig.32As shown, if the radius of the memory hole MH or the columnar body CL at the lower end CLb of the dummy columnar body CLd is set to R22_221, then the radius R21a_224 is equal to or smaller than the radius R22_221. Since the columnar body CL becomes thinner as it approaches the lower end CLb, at least in the memory cell MC closest to the lower end CLb, the diameter R21a_224×2 of the columnar body CL is equal to or smaller than the diameter R22_221×2 at the lower end CLb.

[0169] In addition, when the radius of the conductor (that is, the source layer BSL and the barrier metal BM) protruding in the -Z direction directly below the virtual columnar body CLd is set to Rbsl_22, and the radius of the memory hole MH is equal to Rbsl_22, in the memory cell MC closest to the lower end CLb, the diameter R21a_224×2 of the columnar body CL is equal to or smaller than the diameter Rbsl_22×2.

[0170] When the diameter R21a_224×2 of the columnar body CL in the memory cell MC is small, the space 21h can be maintained large in the replacement step. Therefore, the interval between the adjacent memory holes MH can be narrowed, which contributes to the reduction of the memory cell array 2m.

[0171] Fig.32 The structure can also be applied to any one of the second to tenth embodiments.

[0172] In addition, when the configuration examples 1 and 2 of the lower end of the columnar body are applied to the ninth embodiment, the lower end of the columnar body becomes Figure 33 to Figure 35 The composition shown.

[0173] (Configuration Example 3 of the Lower End of the Columnar Body)

[0174] Fig.33 2 is a cross-sectional view showing a configuration example in which the configuration example 1 of the lower end of the columnar body is applied to the configuration example of the ninth embodiment. In this case, the cover insulating layer 221 is a laminated film of insulating layers 221a to 221c. The other configurations of the configuration example 3 may be the same as those of the configuration example 1.

[0175] (Configuration Example 4 of the Lower End of the Columnar Body)

[0176] Fig.34 and Fig.35 It is a cross-sectional view of a structural example in which structural example 2 of the lower end portion of a columnar body is applied to a structural example of the ninth embodiment. Fig.34 Indicates the composition of the columnar body CL, Fig.35 2 shows the structure of the dummy columnar body CLd. In this case, the cover insulating layer 221 is a laminated film of the insulating layers 221a to 221c. The other structures of the structural example 4 can be the same as those of the structural example 2.

[0177] Although not shown in the drawings, Configuration Example 1 and Configuration Example 2 can also be applied to the tenth embodiment. In such a case, the cover insulating layer 221 is a laminated film of the insulating layers 221 a and 221 b .

[0178] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The embodiments or their variations are included in the invention described in the claims and their equivalents as long as they are included in the scope or spirit of the invention.

[0179] [Explanation of symbols]

[0180] 1 Semiconductor storage device

[0181] 2 Array Chip

[0182] 3 CMOS chip

[0183] 20 Layered

[0184] 21 Conductive film

[0185] 22 Insulation film

[0186] CL column

[0187] ST(LI) gap

[0188] BSL Source Layer

[0189] CCw contact

[0190] 210 Semiconductor body

[0191] 220 Memory Film

[0192] 230 Core Layer

[0193] 224,21a Blocking insulating layer

[0194] 221 Cover insulation layer

[0195] 222 Charge Trapping Film

[0196] 223 Tunnel insulation layer

[0197] 21b Barrier membrane.

Claims

1. A semiconductor storage device comprising: A laminate including a plurality of first conductive films and a plurality of first insulating films alternately laminated in a first direction; and A plurality of first columnar bodies, comprising: a first semiconductor portion extending in the first direction in the laminate; a first insulator portion disposed between the first semiconductor portion and the laminate; a second insulator portion disposed between the first insulator portion and the laminate; a third insulator portion disposed between the second insulator portion and the plurality of first conductive films; and a fourth insulator portion disposed between the second insulator portion and the plurality of first insulating films; and The second insulator portion includes: a first portion provided between the first insulator portion and the first conductive film; and a second portion provided between the first insulator portion and the first insulating film, the thickness of which in a second direction perpendicular to the first direction is thinner than that of the first portion; The plurality of first insulating films are laminated films of a second insulating film and a third insulating film, or are formed of the third insulating film.

2. The semiconductor memory device according to claim 1, wherein The third insulating film is an insulating film containing carbon.

3. The semiconductor memory device according to claim 2, wherein The third insulating film is an insulating film containing SiOC.

4. The semiconductor memory device according to claim 1, further comprising: a fifth insulator portion, provided between the third insulator portion and the plurality of first conductive films, and having a higher dielectric constant than the third insulator portion; The diameter of the plurality of first columnar bodies at the boundary between the third insulator part and the fifth insulator part closest to the lower end of the plurality of first columnar bodies is equal to or smaller than the diameter of the outer periphery of the fourth insulator part at the lower end of the plurality of first columnar bodies.

5. The semiconductor memory device according to claim 1, further comprising: A second columnar body having the same structure as the first columnar body, wherein the first semiconductor portion is electrically isolated from the source layer located below the stacked body; The diameter of the second columnar body at the boundary between the fifth insulator portion and the third insulator portion closest to the lower end portion of the second columnar body is equal to or smaller than the diameter of the outer periphery of the conductor protruding in the first direction directly below the second columnar body located in the source layer.

6. The semiconductor memory device according to claim 1, further comprising: a fifth insulator portion, provided between the third insulator portion and the plurality of first conductive films, and having a higher dielectric constant than the third insulator portion; In a cross section in a vertical direction perpendicular to the first direction, a diameter of the first column at a boundary between the third insulator portion and the fifth insulator portion is equal to or smaller than a diameter of the first column at a boundary between the plurality of first insulating films and the fourth insulator portion.

7. The semiconductor memory device according to claim 1, wherein The third insulating film is provided on both sides of the second insulating film in the first direction so as to sandwich the second insulating film, or the third insulating film is provided at the center of the second insulating film in the first direction so as to be sandwiched by the second insulating film.

8. The semiconductor memory device according to claim 1, further comprising: a plurality of contacts penetrating the plurality of first insulating films in contact regions exposed from the laminated body and connected to the plurality of first conductive films covered by each of the plurality of first insulating films; In the contact region, the third insulating film includes a fourth insulating film between the plurality of first conductive films and the second insulating film, and a fifth insulating film on the second insulating film. The fourth insulating film is thicker than the fifth insulating film.

9. A semiconductor storage device comprising: A laminate including a plurality of first conductive films and a plurality of first insulating films alternately laminated in a first direction; and A plurality of first columnar bodies, comprising: a first semiconductor portion extending in the first direction in the laminate; a first insulator portion disposed between the first semiconductor portion and the laminate; a second insulator portion disposed between the first insulator portion and the laminate; a third insulator portion disposed between the second insulator portion and the plurality of first conductive films; and a fourth insulator portion disposed between the second insulator portion and the plurality of first insulating films; and The second insulator portion includes: a first portion provided between the first insulator portion and the first conductive film; and a second portion provided between the first insulator portion and the first insulating film, the thickness of which in a second direction perpendicular to the first direction is thinner than that of the first portion; The plurality of first insulating films are laminated films of second insulating films and third insulating films, or are composed of the third insulating films. In the cross section in the first direction, a first length in the first direction of a boundary between the first portion and the third insulator portion is longer than a second length of the first portion on an extension line of a boundary between the second portion and the fourth insulator portion.

10. The semiconductor memory device according to claim 9, wherein In the cross section in the first direction, a third length in the first direction of the first portion at a boundary between the first portion and the first insulator portion is longer than the second length.

11. A semiconductor storage device comprising: A laminate including a plurality of first conductive films and a plurality of first insulating films alternately laminated in a first direction; and A plurality of first columnar bodies, comprising: a first semiconductor portion extending in the first direction in the laminate; a first insulator portion disposed between the first semiconductor portion and the laminate; a second insulator portion disposed between the first insulator portion and the laminate; a third insulator portion disposed between the second insulator portion and the plurality of first conductive films; and a fourth insulator portion disposed between the second insulator portion and the plurality of first insulating films; and The second insulator portion includes: a first portion provided between the first insulator portion and the first conductive film; and a second portion provided between the first insulator portion and the first insulating film, the thickness of which in a second direction perpendicular to the first direction is thinner than that of the first portion; The plurality of first insulating films are laminated films of second insulating films and third insulating films, or are composed of the third insulating films. The fourth insulator portion includes a sixth insulator portion and a seventh insulator portion which are stacked in the second direction and made of different materials.

12. The semiconductor memory device according to claim 11, further comprising: a fifth insulator portion, provided between the third insulator portion and the plurality of first conductive films, and having a higher dielectric constant than the third insulator portion; The diameter of the plurality of first columnar bodies at the boundary between the third insulator portion and the fifth insulator portion closest to the lower end of the plurality of first columnar bodies is equal to or smaller than the diameter of the outer periphery of the fourth insulator portion at the lower end of the plurality of first columnar bodies.

13. The semiconductor memory device according to claim 11, further comprising: a fifth insulator portion provided between the third insulator portion and the plurality of first conductive films and having a higher dielectric constant than the third insulator portion; and a second columnar body having the same structure as the first columnar body, wherein the first semiconductor portion is not electrically connected to the source layer located below the stacked body; At the position of the first conductive film closest to the lower end of the second columnar body, the diameter of the plurality of second columnar bodies at the boundary between the fifth insulator portion and the third insulator portion is equal to or smaller than the diameter of the outer periphery of the fourth insulator portion at the lower end of the second columnar body.

14. The semiconductor memory device according to claim 11, further comprising: a fifth insulator portion, provided between the third insulator portion and the plurality of first conductive films, and having a higher dielectric constant than the third insulator portion; In a cross section taken in a direction perpendicular to the first direction, a diameter of a boundary between the fifth insulator portion and the third insulator portion is equal to or smaller than a diameter of a boundary between the first insulating film and the fourth insulator portion.

15. The semiconductor memory device according to claim 11, wherein The fourth insulator portion includes the sixth and seventh insulator portions stacked in the second direction, The sixth insulator portion and the seventh insulator portion are made of different materials.

16. The semiconductor memory device according to claim 11, wherein The fourth insulator portion includes the sixth to eighth insulator portions stacked in the second direction, The sixth and eighth insulator portions are made of materials different from those of the seventh insulator portion.

17. The semiconductor memory device according to claim 11, further comprising: a fifth insulator portion, provided between the plurality of first insulating films and the plurality of first conductive films, and between the third insulator portion and the plurality of first conductive films, and having a higher dielectric constant than the first insulating films and the third insulator portion; A length in the first direction of the stacked structure of the first conductive film and the fifth insulator portion is equal to or shorter than a length of the first portion in the first direction.

18. The semiconductor memory device according to claim 11, wherein The seventh insulator portion is in contact with the first portion in the first direction.

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