A gallium oxide heterojunction mosfet device and method of fabrication

Abstract

The application discloses a gallium oxide heterojunction MOSFET device and a manufacturing method, and mainly solves the problem of high on-resistance of the existing similar devices. The device comprises a drain (1), a Ga2O3 substrate (2), a Ga2O3 epitaxial layer (3), a Ga2O3 layer (4) into which acceptor ions are injected, a gate (8) and a source (9), wherein the Ga2O3 layer (4) into which acceptor ions are injected is sequentially provided with an unintentionally doped Ga2O3 layer (5) and an AlGaO layer (6) to form a heterojunction; a groove is arranged in the middle of the AlGaO layer (6), and an insulating gate dielectric layer (7) is arranged on the inner wall of the groove; the gate (8) is located on the upper portion of the insulating gate dielectric layer; and the source (9) is located at both ends of the AlGaO layer (6). The two-dimensional electron gas (2DEG) is generated by the introduced heterojunction, the mobility of the carrier is improved, the on-resistance is reduced, the on-current is improved, and the device can be used as a power and high-voltage switching device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to a gallium oxide heterojunction metal-oxide-semiconductor field-effect transistor, which can be used in power devices and switching devices. Background Technology

[0002] Compared to SiC and GaN semiconductor materials, β-Ga2O3 has many unique advantages. β-Ga2O3 has a bandgap of 4.8-4.9 eV and a theoretical breakdown field strength as high as 8 MV / cm, which is more than twice the theoretical limits of SiC and GaN. Its Baliga figure of merit is also far superior to other semiconductor materials. Furthermore, high-quality single-crystal β-Ga2O3 can be mass-produced using melting methods, including optical floating zone method, mode-guided method, Czochralski method, and vertical Bridgman method, which will significantly reduce the cost of future materials. Moreover, β-Ga2O3 can be produced at a density of 1×10⁻⁶ eV. 15 -1×10 20 cm -3 Precise electron concentration control can be achieved over an ultra-wide range. To fully utilize β-Ga2O3 materials, vertical devices have become mainstream because they offer higher power density chips. Furthermore, increasing the breakdown voltage of vertical MOSFETs does not require sacrificing chip area, as the breakdown voltage is proportional to the thickness of the drift layer. However, the lack of p-type doping technology limits the development of bipolar power devices, resulting in limited research on β-Ga2O3 vertical transistors. More effort is needed to achieve high-performance enhancement-mode transistors.

[0003] Early vertical β-Ga2O3 field-effect transistors (FETs) could be categorized into FinFETs and current aperture vertical pad transistors (CAVETs). More recently, U-gate trench MOSFETs based on N-ion implantation have been fabricated. In this structure, a trench is etched from the source to the drift layer, and a gate oxide is grown on the sidewalls, then filled with a suitable conductive material. When a gate voltage is applied, current flows along the channel on the trench sidewalls.

[0004] Yongjian Ma et al. published an article titled "702.3 A·cm" in IEEE Electron Device Letters, vol.44, no.3, pp.384-387, March 2023. -2 / 10.4mΩ·cm 2 The paper "β-Ga2O3 U-Shape Trench Gate MOSFET With N-Ion Implantation" presents a U-shaped gate trench MOSFET device structure, such as... Figure 1As shown, from bottom to top, it includes a drain, a Ga2O3 substrate, a Ga2O3 epitaxial layer, a Ga2O3 layer implanted with host ions, a highly doped n-type Ga2O3 layer, and a source. The surface of the highly doped n-type Ga2O3 layer has grooves recessed towards the Ga2O3 substrate, with the bottom of the grooves reaching into the Ga2O3 epitaxial layer. The grooves contain an insulating gate dielectric layer and a gate electrode. Etching the trenches introduces numerous etching defects, resulting in poor channel surface quality, reduced channel carrier mobility, and a very high on-resistance. Reverse breakdown characteristics... Summary of the Invention

[0005] The purpose of this invention is to address the shortcomings of the prior art by proposing a gallium oxide heterojunction MOSFET device and its fabrication method, thereby increasing the channel carrier mobility and improving the device's conduction performance.

[0006] The key technology to achieve the purpose of this invention is to increase the carrier concentration and mobility in the device channel by changing the device structure in order to compensate for the low conductivity caused by etching damage.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows:

[0008] 1. A gallium oxide heterojunction MOSFET device, comprising: a drain, a Ga2O3 substrate, a Ga2O3 epitaxial layer, a Ga2O3 layer implanted with acceptor ions, a gate, and a source, characterized in that: an unintentionally doped Ga2O3 layer and an AlGaO layer are sequentially disposed on the Ga2O3 layer implanted with acceptor ions to improve carrier concentration and carrier mobility; a trench is provided in the middle of the AlGaO layer, and an insulating gate dielectric layer is provided on the inner wall of the trench; the gate is located on the upper part of the insulating gate dielectric layer; and the source is located at both ends of the AlGaO layer.

[0009] Furthermore, the trench is oriented downwards from the surface of the AlGaO layer, with its bottom reaching into the Ga2O3 epitaxial layer, and has a depth of 4µm-6µm.

[0010] Furthermore, the Ga2O3 substrate is highly n-doped with Sn or Si. + β-Ga2O3 material with a doping concentration of 1×10 18 -5×10 19 cm -3 The thickness is 300-600 nm; the Ga2O3 epitaxial layer is made of low-n doped material doped with Sn or Si. - β-Ga2O3 material with a doping concentration of 5×10 15 -1×10 17 cm -3 The thickness is 6-10um.

[0011] Furthermore, the Ga2O3 layer implanted with acceptor ions is a high-resistivity β-Ga2O3 material doped with N or Mg, with a doping concentration of 1×10⁻⁶. 18 -5×10 18 pcs / cm 3 The thickness is 400-800 nm; the highly doped n-type Ga2O3 layer is made of Sn or Si with high n-doping. + β-Ga2O3 material with a doping concentration of 1×10 19 -5×10 19 cm -3 The thickness is 100-200 nm; the AlGaO layer is made of highly doped AlGaO material with Si doping concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 The thickness is 20-30nm; the insulating gate dielectric layer is made of Al2O3 material with a thickness of 20-60nm.

[0012] 2. A method for manufacturing a gallium oxide heterojunction MOSFET device, characterized by comprising the following steps:

[0013] S1) Using the MBE process, β-Ga2O3 material with a thickness of 4-10 μm is deposited on a Ga2O3 substrate to form a Ga2O3 epitaxial layer;

[0014] S2) Using MOCVD and ion implantation processes, β-Ga2O3 material with a thickness of 400-800 nm is deposited on the Ga2O3 epitaxial layer to form a Ga2O3 layer implanted with acceptor ions.

[0015] S3) Using MOCVD process, β-Ga2O3 material with a thickness of 100-200nm is deposited on Ga2O3 layer implanted with host acceptor ions to form unintentionally doped n-type Ga2O3 layer.

[0016] S4) Using MOCVD process, AlGaO material with a thickness of 20-30nm is deposited on an unintentionally doped n-type Ga2O3 layer to form a highly doped AlGaO layer;

[0017] S5) Using the RIE process, trenches are etched on the surface of the highly doped n-type Ga2O3 layer, with the bottom of the trenches reaching into the Ga2O3 epitaxial layer and a depth of 4um-6um.

[0018] S6) Using the ALD process, Al2O3 with a thickness of 20-60nm is deposited on the inner wall of the trench and the AlGaO layer to form an insulating gate dielectric layer;

[0019] S7) Using E-Beam and stripping processes, Ni / Au of 20-60nm / 120-250nm is deposited on the insulating gate dielectric layer, and then stripped in acetone solution to form the gate.

[0020] S8) Using the E-Beam process, 20-60nm / 120-250nm Ti / Au is deposited on both ends of the AlGaO layer, and then annealed in a N2 atmosphere at 300-550℃ for 1-3 minutes to form the source electrode;

[0021] S9) Using the E-Beam process, after depositing 20-60nm / 120-250nm Ti / Au on the back side of the Ga2O3 substrate, the substrate is annealed for 1-3 minutes in an N2 atmosphere at 300-550℃ to form the drain and complete the device fabrication.

[0022] This invention comprises an unintentionally doped Ga2O3 layer and an AlGaO layer sequentially disposed on a Ga2O3 layer implanted with acceptor ions, forming a heterojunction to generate a two-dimensional electron gas. Since the two-dimensional electron gas moves only within a thin layer of 4 nm thickness, it exhibits high carrier concentration and high carrier mobility, effectively reducing lattice scattering between impurities. This results in electrons in the two-dimensional electron gas possessing an extremely high maximum saturation velocity, effectively reducing on-resistance and improving the device's conductivity. Furthermore, because this invention incorporates a trench in the middle of the AlGaO layer, with a high-k insulating gate dielectric layer on the inner wall of the trench, it not only significantly reduces electron tunneling effects, lowering gate leakage current and device power consumption, but also results in lower gate-source capacitance, significantly improving the device's switching speed. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of an existing gallium oxide MOSFET device;

[0024] Figure 2 This is a schematic diagram of the gallium oxide heterojunction MOSFET of the present invention;

[0025] Figure 3 This is a schematic diagram of the fabrication process of the gallium oxide heterojunction MOSFET device of the present invention. Detailed Implementation

[0026] The following accompanying drawings illustrate embodiments of the present invention in detail, but are not limited to the embodiments described herein.

[0027] refer to Figure 2 The gallium oxide heterojunction MOSFET device in this example includes: a drain 1, a Ga2O3 substrate 2, a Ga2O3 epitaxial layer 3, a Ga2O3 layer implanted with host acceptor ions 4, an unintentionally doped Ga2O3 layer 5, an AlGaO layer 6, an insulating gate dielectric layer 7, a gate 8, and a source 9. Wherein:

[0028] The Ga2O3 substrate 2 is made of highly n-doped Sn or Si. + β-Ga2O3 material with a doping concentration of 1×10 18 -5×10 19 cm -3 The thickness is 300-600nm;

[0029] The drain 1 is located on the back of the Ga2O3 substrate 2 and is made of Ti / Au metal material with a wavelength of 20-60nm / 120-250nm.

[0030] The Ga2O3 epitaxial layer 3 is located on top of the Ga2O3 substrate 2, and it is made of low-n-doped material with Sn or Si. - β-Ga2O3 material with a doping concentration of 5×10 15 -1×10 17 cm -3 The thickness is 4-10 μm;

[0031] The Ga2O3 layer 4, implanted with acceptor ions, is located above the Ga2O3 epitaxial layer 3. It is made of high-resistivity β-Ga2O3 material doped with N or Mg, with a doping concentration of 1×10⁻⁶. 18 -5×10 18 pcs / cm 3 The thickness is 400-800 nm;

[0032] The unintentionally doped n-type Ga2O3 layer 5 is located above the Ga2O3 layer 4 implanted with acceptor ions. It is made of β-Ga2O3 material and has a carrier concentration of 1×10⁻⁶. 15 -1×10 16 cm -3 The thickness is 100-200nm;

[0033] The AlGaO layer 6, located above the unintentionally doped n-type Ga2O3 layer 5, is made of Si-doped AlGaO material with a doping concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 The thickness is 20-30nm; the AlGaO layer has a trench in the middle to be used to make an insulating gate dielectric layer;

[0034] The insulating gate dielectric layer 7 is located at the bottom and sidewalls of the trench in the AlGaO layer 6. It is made of Al2O3 material and has a thickness of 20-60nm.

[0035] The gate 8 is located on top of the insulating gate dielectric layer 7, and it is made of Ni / Au metal material with a wavelength of 20-60nm / 120-250nm.

[0036] The source electrode 9 is located at both ends of the AlGaO layer 6 and is made of Ti / Au metal material with a wavelength of 20-60nm / 120-250nm.

[0037] Reference Figure 3 The present invention provides three embodiments of the method for fabricating gallium oxide heterojunction MOSFET devices:

[0038] Example 1: Sn doping with n + On a β-Ga2O3 substrate, a 100 nm thick substrate with a carrier concentration of 1 × 10⁻⁶ was fabricated. 15 cm -3 An unintentionally doped Ga2O3 layer with a thickness of 20 nm and a Si doping concentration of 1×10⁻⁶ 18 cm -3 Gallium oxide heterojunction MOSFET devices with AlGaO layers.

[0039] Step 1: Using the MBE process, grow a Ga2O3 epitaxial layer on a Ga2O3 substrate, such as... Figure 3 (a).

[0040] 1.1) For Sn doping concentration of 1×10 18 cm -3 n with a thickness of 300nm + β-Ga2O3 substrate 2 was sequentially cleaned with organic matter and deionized water, and then dried with high-purity N2.

[0041] 1.2) The cleaned high-doped n + A β-Ga2O3 substrate was placed in a molecular beam epitaxy (MBE) growth chamber. High-purity 6N Ga and high-purity 4N SnO2 powders were heated in a K chamber to provide Ga and Sn elements. A mixed gas with 5% O3 and 95% O2 was used to provide oxygen.

[0042] 1.3) Set 2×10 for Ga elements -4 A pressure of Pa was applied to force it into the reaction chamber, and a mixed gas with a flow rate of 5 sccm was introduced into the reaction chamber. The substrate was heated to 560°C to obtain a doping concentration of 5 × 10⁻⁶. 15 cm -3 Sn-doped n with a thickness of 6 μm - β-Ga2O3 epitaxial layer 3.

[0043] Step 2: Using MOCVD and ion implantation processes, a Ga2O3 layer implanted with acceptor ions is grown on the Ga2O3 epitaxial layer, such as... Figure 3 (b)

[0044] 2.1) Using TEGa and O2 as gallium and oxygen sources, and N2 as carrier gas, a thin film was epitaxially deposited on the β-Ga2O3 epitaxial layer by chemical vapor deposition (MOCVD).

[0045] 2.2) Place the thin film into an ion implanter, and at an implantation dose of 1×10⁻⁶. 14 cm -3 Under the process condition of implantation energy of 380 KeV, ion implantation is performed on the thin film to form a β-Ga2O3 layer with N ion implantation;

[0046] 2.3) The sample after N ion implantation was placed in a tubular annealing furnace at 1100℃ for 25 min to activate the N ions, resulting in an implantation concentration of 1×10⁻⁶. 18 pcs / cm 3 4. A Ga2O3 layer with acceptor ions with a thickness of 400 nm.

[0047] Step 3 uses MOCVD technology to grow an unintentionally doped Ga2O3 layer on the Ga2O3 layer implanted with acceptor ions, such as... Figure 3 (c)

[0048] Using chemical vapor deposition (MOCVD), with TEGa and O2 as gallium and oxygen sources respectively, and N2 as the carrier gas, and TEGa and O2 flow rates of 50 sccm and 2000 sccm respectively, a reaction chamber temperature of 600℃, and a growth pressure of 20 Torr, an epitaxial carrier concentration of 1×10⁻⁶ was achieved on a Ga₂O₃ layer with acceptor ions. 15 cm -3 5. An unintentionally doped Ga2O3 layer with a thickness of 100 nm.

[0049] Step 4 uses MOCVD technology to grow an AlGaO layer on an unintentionally doped Ga2O3 layer, such as... Figure 3 (d)

[0050] Using chemical vapor deposition (MOCVD), with TEGa, TMAl, and O2 as gallium, aluminum, and oxygen sources respectively, and N2 as the carrier gas, and flow rates of TEGa, TMAl, and O2 at 50 sccm, 20 sccm, and 2000 sccm respectively, a reaction chamber temperature of 600℃, and a growth pressure of 20 Torr, an epitaxial doping concentration of 1×10⁻⁶ was achieved on an unintentionally doped Ga₂O₃ layer. 18 cm -3 6. An AlGaO layer with a thickness of 20nm.

[0051] Step 5: Using the RIE process, trenches are etched on the surface of the AlGaO layer, such as... Figure 3 (e).

[0052] Reactive ion etching (RIE) was used to etch trenches with a depth of 4 μm on the surface of an AlGaO layer under the following process conditions: chamber pressure of 5.0 Pa, plasma power of 150 W, and flow rates of BCl3 and Ar of 20 sccm and 10 sccm, respectively. The etching damage was then repaired with hot phosphoric acid.

[0053] Step 6: Using the ALD process, fabricate the insulating gate dielectric layer, such as... Figure 3 (f).

[0054] Using atomic layer deposition (ALD) technology, under the process conditions of using trimethylaluminum (TMA) and H2O as aluminum and oxygen sources, a reaction chamber temperature of 200℃, and a growth rate of 0.07 nm / cycle, an Al2O3 layer with a thickness of 20 nm was deposited on the inner wall of the trench to form an insulating gate dielectric layer 7.

[0055] Step 7, fabricate the gate electrode, such as Figure 3 (g)

[0056] 7.1) Ni with a thickness of 20 nm and Au with a thickness of 120 nm are sequentially deposited on the insulating gate dielectric layer by electron beam evaporation E-Beam process. After the metal deposition is completed, it is placed in acetone solution for stripping to form the gate electrode 8.

[0057] 7.2) Place the stripped sample in acetone solution, anhydrous ethanol solution, and deionized water in sequence and ultrasonically clean for 5 minutes each, then dry with pure N2.

[0058] Step 8, fabricate the source electrode, such as Figure 3 (h).

[0059] 8.1) Ti with a thickness of 20 nm and Au with a thickness of 120 nm were sequentially deposited in the source region by electron beam evaporation (E-Beam) process;

[0060] 8.2) The deposited metal was ultrasonically cleaned in acetone and anhydrous ethanol solutions for 5 minutes, and then cleaned with plasma water for 5 minutes. After drying with high-purity N2, the source electrode 9 was formed.

[0061] 8.3) At a temperature of 470℃ and a nitrogen flow rate of 3L / min, heat anneal for 1 minute to form a good ohmic resistance.

[0062] Step 9, fabricate the drain electrode, such as Figure 3 (i).

[0063] 9.1) Ti with a thickness of 20 nm and Au with a thickness of 120 nm were sequentially deposited in the drain region by electron beam evaporation (E-Beam) process;

[0064] 9.2) The deposited metal was ultrasonically cleaned in acetone and anhydrous ethanol solutions for 5 minutes, and then cleaned with plasma water for 5 minutes. After drying with high-purity N2, the drain electrode 1 was formed. Then, it was thermally annealed for 1 minute at a temperature of 470℃ and a nitrogen flow rate of 3L / min to form a good ohmic resistance, thus completing the device fabrication.

[0065] Example 2, Sn doped with n + On a β-Ga2O3 substrate, a 150 nm thick substrate with a carrier concentration of 5 × 10⁻⁶ was fabricated. 15 cm -3 An unintentionally doped Ga2O3 layer with a thickness of 25 nm and a Si doping concentration of 3 × 10⁻⁶ 18 cm -3 Gallium oxide heterojunction MOSFET devices with AlGaO layers.

[0066] Step 1: Using the MBE process, grow a Ga2O3 epitaxial layer on a Ga2O3 substrate, such as... Figure 3 (a).

[0067] Sn doping concentration of 5×10 19 cm -3 n with a thickness of 600nm + β-Ga2O3 substrate 2 was sequentially cleaned with organic matter and then with deionized water, and dried with high-purity N2; then the cleaned highly n-doped substrate was... + A β-Ga2O3 substrate was placed in a molecular beam epitaxy (MBE) growth chamber. High-purity 6N Ga and high-purity 4N SnO2 powders were heated in a K chamber to provide Ga and Sn elements. A mixed gas with 5% O3 and 95% O2 was used to provide oxygen.

[0068] Set 2×10 for Ga elements -4 A pressure of Pa was applied to force it into the reaction chamber, and a mixed gas with a flow rate of 5 sccm was introduced into the reaction chamber. The substrate was heated to 700°C to obtain a doping concentration of 1×10⁻⁶. 17 cm -3 Sn-doped n with a thickness of 10 μm - β-Ga2O3 epitaxial layer 3.

[0069] Step two: Using MOCVD and ion implantation processes, a Ga2O3 layer implanted with acceptor ions is grown on the Ga2O3 epitaxial layer, such as... Figure 3 (b)

[0070] The process conditions were set up with TEGa and O2 as gallium and oxygen sources, and N2 as carrier gas, and a thin film was epitaxially deposited on the β-Ga2O3 epitaxial layer using chemical vapor deposition (MOCVD).

[0071] The thin film was placed in an ion implanter, and the implantation dose was set to 5 × 10⁻⁶. 14 cm -3 Under process conditions with an implantation energy of 380 KeV, ion implantation was performed on the thin film to form a β-Ga2O3 layer with N ion implantation.

[0072] The sample after N ion implantation was then placed in a tubular annealing furnace at 1100℃ for 25 min to activate the N ions, resulting in an implantation concentration of 5×10⁻⁶. 18 pcs / cm 3 4. A Ga2O3 layer with acceptor ions with a thickness of 800 nm.

[0073] Step 3: Using MOCVD technology, an unintentionally doped Ga2O3 layer is grown on the Ga2O3 layer implanted with acceptor ions, such as... Figure 3 (c)

[0074] The process conditions were set as follows: TEGa and O2 were used as gallium and oxygen sources, respectively; N2 was used as the carrier gas; the flow rates of TEGa and O2 were 50 sccm and 2000 sccm, respectively; the reaction chamber temperature was 600℃; and the growth pressure was 20 Torr. Using chemical vapor deposition (MOCVD), a carrier concentration of 5 × 10⁻⁶ was achieved on a Ga₂O₃ layer with acceptor ions. 15 cm -3 5. An unintentionally doped Ga2O3 layer with a thickness of 150nm.

[0075] Step four: Using MOCVD technology, grow an AlGaO layer on the unintentionally doped Ga2O3 layer, such as... Figure 3 (d)

[0076] The process conditions were set as follows: gallium source TEGa, aluminum source TMAl, and oxygen source O2; carrier gas N2; flow rates of TEGa, TMAl, and O2 were 50 sccm, 20 sccm, and 2000 sccm, respectively; reaction chamber temperature was 600℃; and growth pressure was 20 Torr. Using MOCVD (Metal-Oxygen Chemical Vapor Deposition), an epitaxial doping concentration of 3 × 10⁻⁶ was achieved on an unintentionally doped Ga₂O₃ layer. 18 cm -3 6. An AlGaO layer with a thickness of 25nm.

[0077] Step 5: Using the RIE process, trenches are etched on the surface of the AlGaO layer, such as... Figure 3 (e).

[0078] With the process conditions set at a chamber pressure of 5.0 Pa, plasma power of 150 W, and flow rates of BCl3 and Ar of 20 sccm and 10 sccm respectively, reactive ion etching (RIE) was used to etch trenches of approximately 6 μm on the surface of the AlGaO layer. The etching damage was then repaired with hot phosphoric acid.

[0079] Step six: Using the ALD process, fabricate the insulating gate dielectric layer, such as... Figure 3 (f).

[0080] With the aluminum source set as trimethylaluminum (TMA), the oxygen source as H2O, the reaction chamber temperature as 400℃, and the growth rate as 0.1 nm / cycle, an atomic layer deposition (ALD) process was used to deposit a 60 nm thick Al2O3 layer on the inner wall of the trench to form an insulating gate dielectric layer 7.

[0081] Step 7, fabricate the gate electrode, such as Figure 3 (g)

[0082] Ni with a thickness of 60 nm and Au with a thickness of 250 nm were sequentially deposited on the insulating gate dielectric layer using the E-Beam process. After the metal deposition was completed, the metal was stripped in acetone solution to form the gate electrode 8. The stripped sample was then ultrasonically cleaned in acetone solution, anhydrous ethanol solution, and deionized water for 5 min each, and dried with pure N2.

[0083] Step 8: Fabricate the source electrode, such as... Figure 3 (h).

[0084] In the source region, Ti with a thickness of 60 nm and Au with a thickness of 250 nm were deposited sequentially using the E-Beam process. The deposited metals were then ultrasonically cleaned in acetone and anhydrous ethanol solutions for 5 minutes, followed by cleaning with plasma water for 5 minutes. After drying with high-purity N2, the source electrode 9 was formed. Subsequently, the electrode was thermally annealed for 1 minute at a temperature of 470 °C and a nitrogen flow rate of 3 L / min to form a good ohmic resistance.

[0085] Step nine, fabricate the drain electrode, such as Figure 3 (i).

[0086] The drain region was first deposited with Ti with a thickness of 60 nm and Au with a thickness of 250 nm using the E-Beam process. The deposited metals were then ultrasonically cleaned in acetone and anhydrous ethanol solutions for 5 minutes, followed by cleaning with plasma water for 5 minutes. After drying with high-purity N2, the drain electrode 1 was formed. Finally, the device was thermally annealed for 1 minute at 470 °C and a nitrogen flow rate of 3 L / min to form a good ohmic resistance, thus completing the device fabrication.

[0087] Example 3, Sn doped with n +On a β-Ga2O3 substrate, a 200 nm thick substrate with a carrier concentration of 1 × 10⁻⁶ was fabricated. 16 cm -3 An unintentionally doped Ga2O3 layer with a thickness of 30 nm and a Si doping concentration of 5 × 10⁻⁶ 18 cm -3 Gallium oxide heterojunction MOSFET devices with AlGaO layers.

[0088] Step A: Using the MBE process, a Ga2O3 epitaxial layer is grown on the Ga2O3 substrate, such as... Figure 3 (a).

[0089] A1) For Sn doping concentration of 1×10 19 cm -3 n with a thickness of 400nm + β-Ga2O3 substrate 2 was sequentially cleaned with organic matter and deionized water, and then dried with high-purity N2.

[0090] A2) The cleaned highly n-doped + A β-Ga2O3 substrate was placed in a molecular beam epitaxy (MBE) growth chamber. High-purity 6N Ga and high-purity 4N SnO2 powders were heated in a K chamber to provide Ga and Sn elements. A mixed gas with 5% O3 and 95% O2 was used to provide oxygen.

[0091] A3) Set the Ga element to 2×10 -4 A pressure of Pa was applied to force it into the reaction chamber, and a mixed gas with a flow rate of 5 sccm was introduced into the reaction chamber. The substrate was heated to 660°C to obtain a doping concentration of 5 × 10⁻⁶. 16 cm -3 Sn-doped n with a thickness of 8 μm - β-Ga2O3 epitaxial layer 3.

[0092] Step B involves using MOCVD and ion implantation to grow a Ga2O3 layer implanted with acceptor ions on a Ga2O3 epitaxial layer, such as... Figure 3 (b)

[0093] B1) Using TEGa and O2 as gallium and oxygen sources, and N2 as carrier gas, a thin film was epitaxially deposited on the β-Ga2O3 epitaxial layer by chemical vapor deposition (MOCVD).

[0094] B2) Place the thin film into an ion implanter and implant it at a dose of 5 × 10⁻⁶. 14 cm -3 Under the process condition of implantation energy of 380 KeV, ion implantation is performed on the thin film to form a β-Ga2O3 layer with N ion implantation;

[0095] B3) The sample after N ion implantation was placed in a tube annealing furnace at 1100℃ for 25 min to activate the N ions, resulting in an implantation concentration of 3×10⁻⁶. 18 pcs / cm 3 4. A Ga2O3 layer with acceptor ions with a thickness of 600 nm.

[0096] Step C: Using MOCVD technology, an unintentionally doped Ga2O3 layer is grown on the Ga2O3 layer implanted with acceptor ions, such as... Figure 3 (c)

[0097] Using the chemical vapor deposition (MOCVD) method, a carrier concentration of 1×10⁻⁶ was epitaxially grown on a Ga₂O₃ layer with acceptor ions. 16 cm -3 An unintentionally doped Ga2O3 layer 5 with a thickness of 200 nm was deposited under the following process conditions:

[0098] Using TEGa as the gallium source, O2 as the oxygen source, and N2 as the carrier gas, the flow rates of TEGa and O2 are set to 50 sccm and 2000 sccm, respectively, the reaction chamber temperature is 600℃, and the growth pressure is 20 Torr.

[0099] Step D: Using MOCVD technology, an AlGaO layer is grown on the unintentionally doped Ga2O3 layer, such as... Figure 3 (d)

[0100] Using the chemical vapor deposition (MOCVD) method, an epitaxial doping concentration of 5 × 10⁻⁶ was achieved on an unintentionally doped Ga₂O₃ layer. 18 cm -3 The AlGaO layer 6 has a thickness of 30 nm, and the deposition process conditions are as follows:

[0101] Using TEGa as the gallium source, TMAl as the aluminum source, O2 as the oxygen source, and N2 as the carrier gas, the flow rates of TEGa, TMAl, and O2 were set to 50 sccm, 20 sccm, and 2000 sccm, respectively. The reaction chamber temperature was 600℃, and the growth pressure was 20 Torr.

[0102] Step E: Using the RIE process, trenches are etched on the surface of the AlGaO layer, such as... Figure 3 (e).

[0103] Reactive ion etching (RIE) was used to etch trenches of approximately 4 μm on the surface of the AlGaO layer. The etch damage was then repaired with hot phosphoric acid. The etching process conditions were as follows:

[0104] The chamber pressure was 5.0 Pa, the plasma power was 150 W, and the flow rates of BCl3 and Ar were 20 sccm and 10 sccm, respectively.

[0105] Step F: Using the ALD process, fabricate the insulating gate dielectric layer, such as... Figure 3 (f).

[0106] Atomic layer deposition (ALD) was used to deposit a 40 nm thick Al2O3 layer on the inner wall of the trench to form an insulating gate dielectric layer 7. The deposition process conditions are as follows:

[0107] Trimethylaluminum (TMA) was used as the aluminum source and H2O as the oxygen source. The reaction chamber temperature was set at 300℃ and the growth rate was 0.08 nm / cycle.

[0108] Step G: Fabricate the gate electrode, such as... Figure 3 (g)

[0109] G1) Ni with a thickness of 50 nm and Au with a thickness of 150 nm are sequentially deposited on the insulating gate dielectric layer by E-Beam process. After the metal deposition is completed, it is placed in acetone solution for stripping to form gate electrode 8.

[0110] G2) Place the stripped sample sequentially into acetone solution, anhydrous ethanol solution, and deionized water for ultrasonic cleaning for 5 minutes each, and then dry it with pure N2.

[0111] Step H, fabricate the source electrode, such as Figure 3 (h).

[0112] H1) Ti with a thickness of 50 nm and Au with a thickness of 150 nm are sequentially deposited in the source region using the E-Beam process;

[0113] H2) The deposited metal was ultrasonically cleaned in acetone and anhydrous ethanol solutions for 5 minutes, and then cleaned with plasma water for 5 minutes. After drying with high-purity N2, the source electrode 9 was formed. Then, it was thermally annealed for 1 minute at a temperature of 470℃ and a nitrogen flow rate of 3L / min to form a good ohmic resistance.

[0114] Step I, fabricate the drain electrode, such as Figure 3 (i).

[0115] I1) Ti with a thickness of 50 nm and Au with a thickness of 150 nm are sequentially deposited in the drain region using the E-Beam process;

[0116] I2) The deposited metal was ultrasonically cleaned in acetone and anhydrous ethanol solutions for 5 minutes, and then cleaned with plasma water for 5 minutes. After drying with high-purity N2, the drain electrode 1 was formed. Then, it was thermally annealed for 1 minute at a temperature of 470℃ and a nitrogen flow rate of 3L / min to form a good ohmic resistance and complete the device fabrication.

[0117] The above descriptions are merely three specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes to the parameters in form and detail without departing from the principles and structure of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing a gallium oxide heterojunction MOSFET device, characterized in that, Includes the following steps: S1) Using the MBE process, in n + A β-Ga2O3 material with a thickness of 4-10 μm is deposited on a β-Ga2O3 substrate (2) to form n - β-Ga2O3 epitaxial layer (3); S2) Using MOCVD process, β-Ga2O3 material with a thickness of 400-800nm ​​is deposited on Ga2O3 epitaxial layer (3) to form Ga2O3 layer (4) implanted with host acceptor ions. S3) Using MOCVD process, a β-Ga2O3 material with a thickness of 100-200nm is deposited on the Ga2O3 layer (4) implanted with acceptor ions to form an unintentionally doped n-type Ga2O3 layer (5). S4) Using MOCVD process, AlGaO material with a thickness of 20-30nm is deposited on an unintentionally doped n-type Ga2O3 layer (5) to form a highly doped AlGaO layer (6) with Si. S5) Using the RIE process, trenches are etched on the surface of the AlGaO layer (6), with the bottom of the trenches reaching into the Ga2O3 epitaxial layer (3) at a depth of 4um-6um; S6) Using the ALD process, Al2O3 with a thickness of 20-60nm is deposited on the inner wall of the trench and the AlGaO layer (6) to form an insulating gate dielectric layer (7). S7) Using the E-Beam process, Ni / Au of 20-60nm / 120-250nm is deposited on the insulating gate dielectric layer (7), and then stripped in acetone solution to form the gate (8). S8) Using the E-Beam process, 20-60nm / 120-250nm Ti / Au is deposited on both ends of the AlGaO layer (6), and then annealed for 1-3 minutes in a N2 atmosphere at 300-550℃ to form the source electrode (9). S9) Using the E-Beam process, after depositing 20-60nm / 120-250nm Ti / Au on the back side of the Ga2O3 substrate (2), the device is annealed for 1-3 minutes in an N2 atmosphere at 300-550℃ to form the drain (1) and complete the device fabrication.

2. The method according to claim 1, characterized in that, The conditions for the MBE process in step S1) are as follows: 6N Ga and high-purity 4N SnO2 powders are used to provide Ga and Sn elements; The pressure corresponding to the Ga source is 2 × 10⁻⁶. -4 Pa; The substrate temperature is 560-700℃; The gas used is a mixture of ozone and oxygen, with ozone accounting for 5% and oxygen accounting for 95%, and the flow rate is 5 sccm.

3. The method according to claim 1, characterized in that, The MOCVD process conditions in steps S2), S3), and S4) are as follows: TEGa and O2 are used to provide Ga and O elements; The flow rates of TEGa, TMA1, and O2 were 50 sccm, 20 sccm, and 2000 sccm, respectively. The reaction chamber temperature is 600-700℃, and the growth pressure is 20 Torr.

4. The method according to claim 1, characterized in that, The parameters for the RIE process in step S5) are set as follows: The RIE chamber pressure is 5.0 Pa; The plasma power is 100W-150W; The flow rates of BCl3 and Ar were 20 sccm and 10 sccm, respectively.

5. The method according to claim 1, characterized in that, The ALD process in step S6) has the following conditions: Trimethylaluminum (TMA) and H₂O are used to provide Al and O elements; The reaction chamber temperature is 200-400℃; The growth rate is 0.07~0.1 nm / cycle.

6. A MOSFET device prepared according to the method of claim 1, comprising: The structure comprises a drain (1), a Ga2O3 substrate (2), a Ga2O3 epitaxial layer (3), a Ga2O3 layer implanted with host ions (4), a gate (8), and a source (9), characterized in that: The Ga2O3 layer (4) implanted with acceptor ions is provided with an unintentionally doped n-type Ga2O3 layer (5) and an AlGaO layer (6) in sequence to improve the carrier concentration and carrier mobility; the AlGaO layer (6) has a trench in the middle, and an insulating gate dielectric layer (7) is provided on the inner wall of the trench. The gate (8) is located on top of the insulating gate dielectric layer (7); The source electrode (9) is located at both ends of the AlGaO layer (6).

7. The device according to claim 6, characterized in that: The unintentionally doped n-type Ga2O3 layer (5) is made of β-Ga2O3 material with a doping concentration of 1×10⁻⁶. 15 -1×10 16 cm -3 The thickness is 100-200nm; The AlGaO layer (6) is made of highly doped AlGaO material with Si doping concentration of 1×10⁻⁶. 18 -5×10 18 cm -3 The thickness is 20-30nm.

8. The device according to claim 6, characterized in that: The trench is oriented downwards from the surface of the AlGaO layer (6), with its bottom reaching into the Ga2O3 epitaxial layer (3), and has a depth of 4um-6um.

9. The device according to claim 6, characterized in that: The Ga2O3 substrate (2) is highly n-doped with Sn or Si. + β-Ga2O3 material with a doping concentration of 1×10 18 -5×10 19 cm -3 The thickness is 300-600nm; The Ga2O3 epitaxial layer (3) is made of low-n doped Sn or Si. - β-Ga2O3 material with a doping concentration of 5×10 15 -1×10 17 cm -3 The thickness is 4-10um.

10. The device according to claim 6, characterized in that: The Ga2O3 layer (4) implanted with acceptor ions is made of high-resistivity β-Ga2O3 material doped with N or Mg, and its doping concentration is 1×10⁻⁶. 18 -5×10 18 pcs / cm 3 The thickness is 400-800 nm; The insulating gate dielectric layer (7) is made of Al2O3 material with a thickness of 20-60nm.

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