Semiconductor structure and method of manufacturing the same, memory device

Abstract

The embodiments of the present application provide a semiconductor structure, a manufacturing method thereof and a memory device. The semiconductor structure comprises a substrate, a well region in the substrate, a threshold voltage doping region above the well region, a lightly doped region on both sides of the threshold voltage doping region, a source region and a drain region on both sides of the lightly doped region respectively, a halo region between the source region and the drain region and the threshold voltage doping region respectively, and a gate structure on the surface of the threshold voltage doping region. The conductivity type of the threshold voltage doping region is different from that of the well region, the doping concentration of the lightly doped region is 8×10 19 ~9×10 19 / cm 3 , and the doping concentration of the halo region is 5×10 18 ~6×10 18 / cm 3 .

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and its manufacturing method, and a memory device. Background Technology

[0002] With the continuous development of integrated circuit manufacturing processes, the size of integrated circuit devices is constantly shrinking. While this brings about performance improvements and reduced power consumption, the reliability issues arising from this miniaturization are becoming increasingly serious. Among these, device mismatch severely affects the realization of circuit functions. Device (e.g., MOS transistor) mismatch typically refers to the situation where, when a group of devices with identical design dimensions are placed in a very close area, their electrical characteristics (e.g., threshold voltage V) are affected. th These differences will be apparent. Device mismatch is often related to its intrinsic physical structure and is difficult to improve. Summary of the Invention

[0003] This application provides a semiconductor structure, its manufacturing method, and a memory device that can at least partially solve the above-mentioned problems in related technologies or other problems in the art.

[0004] Firstly, some embodiments of this application provide a semiconductor structure. The semiconductor structure includes: a substrate; a well region located within the substrate; a threshold voltage doped region located above the well region; lightly doped regions located on either side of the threshold voltage doped region; a source region and a drain region located on either side of the lightly doped region; a halo region located between the source region and the drain region and the threshold voltage doped region; and a gate structure located on the surface of the threshold voltage doped region; wherein the conductivity type of the threshold voltage doped region is different from that of the well region, and the doping concentration of the lightly doped region is 8 × 10⁻⁶. 19 ~9×10 19 / cm 3 The doping concentration in the halo region is 5 × 10⁻⁶. 18 ~6×10 18 / cm 3 .

[0005] In some implementations, the conductivity type of the well region is P-type, and the conductivity type of the threshold voltage doped region is N-type.

[0006] In some implementations, the doping element in the threshold voltage doped region is phosphorus or arsenic.

[0007] In some implementations, the doping element in the lightly doped region is arsenic, and the doping element in the halo region is boron.

[0008] In some implementations, the doping concentrations of both the source and drain regions are greater than the doping concentration of the lightly doped region.

[0009] In some implementations, the semiconductor structure also includes an isolation structure located on both sides of the source and drain regions away from the threshold voltage doped regions.

[0010] In some embodiments, the gate structure includes a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer is located on the surface of the threshold voltage doped region, and the gate conductive layer is located on the surface of the gate dielectric layer.

[0011] Secondly, some embodiments of this application provide a memory device. This memory device includes at least one semiconductor structure as mentioned in any of the embodiments described above.

[0012] In some implementations, the memory device is a DRAM memory, and the semiconductor structure is used to form a sense amplifier.

[0013] Thirdly, some embodiments of this application provide a method for manufacturing a semiconductor structure. The method includes: forming a well region in a substrate; forming a threshold voltage doped region above the well region; forming a gate structure on the surface of the threshold voltage doped region; forming lightly doped regions on both sides of the threshold voltage doped region; forming a source region and a drain region on both sides of the lightly doped region; and forming a halo region between the source region and the drain region and the threshold voltage doped region, respectively; wherein the conductivity type of the threshold voltage doped region is different from that of the well region, and the doping concentration of the lightly doped region is 8 × 10⁻⁶. 19 ~9×10 19 / cm 3 The doping concentration in the halo region is 5 × 10⁻⁶. 18 ~6×10 18 / cm 3 .

[0014] Fourthly, some embodiments of this application provide another method for manufacturing a semiconductor structure. This method includes: forming a well region in a substrate; forming an initial gate dielectric layer on the surface of the well region; forming an initial gate conductive layer on the surface of the initial gate dielectric layer; and etching the initial gate dielectric layer and the initial gate conductive layer to form a gate structure; wherein, after forming the initial gate dielectric layer, a threshold voltage doped region is formed above the well region.

[0015] In some implementations, a threshold voltage doped region is formed after the initial gate conductive layer is formed and before the initial gate dielectric layer and the initial gate conductive layer are etched to form the gate structure.

[0016] In some embodiments, forming a threshold voltage doped region above the well region after forming the initial gate dielectric layer includes: implanting ions of dopant elements having P-type conductivity type into the surface of the well region by an ion implantation process to form the threshold voltage doped region.

[0017] In some implementations, the dopant element having P-type conductivity is boron, and the ion source for the ion implantation process is boron atoms.

[0018] In some embodiments, forming a threshold voltage doped region above the well region after forming the initial gate dielectric layer includes: implanting ions of a dopant element having an N-type conductivity type into the surface of the well region by an ion implantation process to form the threshold voltage doped region; wherein, after etching the initial gate dielectric layer and the initial gate conductive layer to form the gate structure, the method further includes: forming a lightly doped region and a halo region on both sides of the threshold voltage doped region covered by the gate structure, wherein the halo region extends below the threshold voltage doped region, and the doping concentration of the lightly doped region is 8 × 10⁻⁶. 19 ~9×10 19 / cm 3 The doping concentration in the halo region is 5 × 10⁻⁶. 18 ~6×10 18 / cm 3 .

[0019] In some embodiments, the doping element having N-type conductivity is phosphorus or arsenic.

[0020] In some embodiments, forming a well region in a substrate includes: implanting ions of a dopant element having a P-type conductivity type into the substrate by an ion implantation process; and annealing the well region.

[0021] In some embodiments, the substrate is made of silicon, the initial gate dielectric layer is made of silicon oxide, and forming the initial gate dielectric layer on the surface of the well region includes forming a silicon oxide layer on the surface of the well region by thermal oxidation.

[0022] In some embodiments, the method further includes forming a source region and a drain region on both sides of the threshold voltage doped region covered by the gate structure by means of an ion implantation process. Attached Figure Description

[0023] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0024] Figure 1 This is a schematic diagram of the semiconductor structure provided in the embodiments of this application;

[0025] Figure 2 This is a circuit diagram of the memory device provided in an embodiment of this application;

[0026] Figure 3 This is a flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of this application;

[0027] Figure 4This is a flowchart of a method for manufacturing a semiconductor structure according to another embodiment of this application;

[0028] Figures 5A to 5H This is a schematic diagram of the semiconductor structure provided in the embodiments of this application during the manufacturing process; and

[0029] Figures 6A to 6C This is a schematic diagram of the semiconductor structure during the manufacturing process provided in another embodiment of this application. Detailed Implementation

[0030] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0032] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0033] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0034] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0035] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0036] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] Figure 1 This is a schematic diagram of the semiconductor structure provided in an embodiment of this application. For example... Figure 1 As shown, the semiconductor structure 100 includes a substrate 111. For example, the substrate 111 may be a thin sheet structure extending laterally along the x and y directions. In some examples, the substrate 111 may be a semiconductor substrate such as silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), or indium phosphide (InP). In other examples, the substrate 111 may be a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrate. In one implementation of this application, the material of the substrate 111 may be single-crystal silicon.

[0038] The semiconductor structure 100 also includes a well region 112 located in the substrate 111. In some embodiments, the well region 112 may have a smaller extension dimension in the x and y directions compared to the substrate 111, and the size of the well region 112 in the z direction is smaller than the size of the substrate 111. For example, the well region 112 may serve as a "local substrate". In some embodiments, the well region 112 and the substrate 111 may have the same or different conductivity types; for example, the conductivity type of the well region 112 may be N-type or P-type. In one implementation of this application, the conductivity type of the well region 112 may be P-type. For example, the doping element of the well region 112 may include boron (B).

[0039] The semiconductor structure 100 also includes a threshold voltage doped region 113 located above the well region 112. In some embodiments, the threshold voltage doped region 113 may have a smaller extension dimension in the x-direction compared to the well region 112, and the size of the threshold voltage doped region 113 in the z-direction is smaller than the size of the well region 112. Viewed from the z-direction, the threshold voltage doped region 113 may be located approximately in the central region of the well region 112. For example, the threshold voltage doped region 113 can be used to adjust the threshold voltage V of the device. thThe conductivity type of the threshold voltage doped region 113 differs from that of the well region 112. In one implementation of this application, when the conductivity type of the well region 112 is P-type, the conductivity type of the threshold voltage doped region 113 is N-type. For example, the dopant element of the threshold voltage doped region 113 can be phosphorus (P) or arsenic (As).

[0040] The semiconductor structure 100 also includes lightly doped regions 116-1 and 116-2 located on either side of the threshold voltage doped region 113, and source region 114 and drain region 115 located on either side of the lightly doped regions 116-1 and 116-2, respectively. In some embodiments, the lightly doped regions 116-1 and 116-2 are symmetrically arranged in the x-direction relative to the threshold voltage doped region 113. In the z-direction, the size of the lightly doped regions 116-1 and 116-2 may be larger than the size of the threshold voltage doped region 113 and smaller than the size of the well region 112. In some embodiments, the source region 114 and drain region 115 are symmetrically arranged relative to the threshold voltage doped region 113. For example, one lightly doped region 116-1 is located between the source region 114 and the threshold voltage doped region 113, and another lightly doped region 116-2 is located between the drain region 115 and the threshold voltage doped region 113. Furthermore, in the z-direction, the dimensions of the source region 114 and drain region 115 may be larger than the dimensions of the lightly doped regions 116-1 and 116-2, and smaller than the dimension of the well region 112. In some embodiments, the top surfaces of the source region 114, drain region 115, threshold voltage doped region 113, and lightly doped regions 116-1 and 116-2 may be substantially flush. It should be noted that... Figure 1 The locations of source region 114 and drain region 115 are illustrated exemplarily. However, in other examples, the locations of source region 114 and drain region 115 can be interchanged; in other words, Figure 1 The source region 114 shown can be called the drain region. Figure 1 The drain region 115 shown can be called the source region.

[0041] In some embodiments, the conductivity types of the source region 114, drain region 115, and lightly doped regions 116-1 and 116-2 may differ from the conductivity type of the well region 112. In one implementation of this application, when the conductivity type of the well region 112 is P-type, the conductivity types of the source region 114, drain region 115, and lightly doped regions 116-1 and 116-2 are all N-type. For example, the doping elements of the source region 114, drain region 115, and lightly doped regions 116-1 and 116-2 may include phosphorus (P), arsenic (As), or antimony (Pb). More specifically, the doping element of the source region 114, drain region 115, and lightly doped regions 116-1 and 116-2 may all be arsenic (As). The doping concentration of the lightly doped regions 116-1 and 116-2 is 8 × 10⁻⁶. 19 ~9×10 19 / cm 3 .

[0042] In some embodiments, the doping concentrations of the source region 114 and the drain region 115 are both greater than the doping concentrations of the lightly doped regions 116-1 and 116-2, so as to form a concentration gradient between the source region 114 and the threshold voltage doped region 113, and between the drain region 115 and the threshold voltage doped region 113, thereby reducing the peak electric field near the drain region 115 and achieving the purpose of improving the hot carrier injection (HCI) effect and device reliability.

[0043] Continue to refer to Figure 1 The semiconductor structure 100 also includes halo regions 117-1 and 117-2. Halo regions 117-1 and 117-2 are located between the source region 114 and the drain region 115, respectively, and the threshold voltage doped region 113. In some embodiments, halo regions 117-1 and 117-2 are symmetrically arranged relative to the threshold voltage doped region 113. For example, halo region 117-1 may be located below the lightly doped region 116-1 and extend obliquely relative to the z-direction below the threshold voltage doped region 113, while directly contacting the source region 114. For example, halo regions 117-1 and 117-2 can reduce the lateral expansion of the source / drain depletion regions and prevent source / drain punch-through.

[0044] In some embodiments, the conductivity type of halo regions 117-1 and 117-2 may be the same as that of well region 112. In one implementation of this application, when the conductivity type of well region 112 is P-type, the conductivity type of halo regions 117-1 and 117-2 may also be P-type. For example, the doping element of halo regions 117-1 and 117-2 may include boron (B), gallium (Ga), or indium (In). More specifically, the doping element of halo regions 117-1 and 117-2 may be boron (B). The doping concentration of halo regions 117-1 and 117-2 is 5 × 10⁻⁶. 18 ~6×10 18 / cm 3

[0045] Continue to refer to Figure 1 The semiconductor structure 100 also includes a gate structure 118 located on the surface of the threshold voltage doped region 113. In some embodiments, the gate structure 118 may include a gate dielectric layer 119 and a gate conductive layer 120 stacked in the z-direction. The gate dielectric layer 119 is located on the surface of the threshold voltage doped region 113, and the gate conductive layer 120 is located on the surface of the gate dielectric layer 119. For example, the material of the gate dielectric layer 119 may include silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N yThe material of the gate conductive layer 120 may be one or more of aluminum (Al), copper (Gu), tungsten (W), titanium (Ti), titanium nitride (TiN), polycrystalline silicon (poly-Si), or any other suitable insulating material. For example, the material of the gate dielectric layer 119 may be silicon oxide (SiO2), and the material of the gate conductive layer 120 may be polycrystalline silicon (poly-Si). In one implementation of this application, the material of the gate dielectric layer 119 may be silicon oxide (SiO2), and the material of the gate conductive layer 120 may be polycrystalline silicon (poly-Si).

[0046] In some embodiments, the semiconductor structure 100 may further include sidewalls 122-1 and 122-2. Sidewalls 122-1 and 122-2 may be located on both sides of the gate structure 118 in the x-direction and above the lightly doped regions 116-1 and 116-2. For example, the materials of sidewalls 122-1 and 122-2 may include silicon oxide (SiO2), silicon nitride (Si3N4), and silicon oxynitride (SiO2). x N y One or more of the following: ) or any other suitable insulating material. Sidewalls 122-1 and 122-2 may serve as masking layers during the formation of lightly doped regions 116-1 and 116-2.

[0047] In some embodiments, the semiconductor structure 100 further includes an isolation structure 121. The isolation structure 121 may be located on either side of the source region 114 and drain region 115, away from the threshold voltage doped region 113. For example, the material of the isolation structure 121 may include silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y One or more of the following: (e.g., or any other suitable insulating material). Exemplarily, viewed in the z-direction, the isolation structure 121 may surround the well region 112. Furthermore, in some embodiments, the bottom surface of the isolation structure 121 may be substantially flush with or spaced from the bottom surface of the well region 112; this application is not specifically limited in this regard. In some embodiments, the top surface of the isolation structure 121 is substantially flush with the top surface of the source region 114 or the drain region 115, or the top surface of the isolation structure 121 is higher than the top surface of the source region 114 or the drain region 115. For example, the isolation structure 121 may be implemented as a shallow trench isolation structure or a field oxygen isolation structure (LOCOS). The isolation structure 121 can be used to improve parasitic field-effect transistors and latch-up effects.

[0048] As described above, in some embodiments, the well region 112, the threshold voltage doped region 113, the lightly doped regions 116-1 and 116-2, the source region 114, the drain region 115, the halo regions 117-1 and 117-2, and the gate structure 118 can constitute a transistor. For example, the transistor can be a metal-oxide-semiconductor field-effect transistor (MOSFET). In some examples, when the conductivity type of the well region 112 is P-type, the conductivity type of the halo regions 117-1 and 117-2 is also P-type, and the conductivity type of the source region 114, the drain region 115, and the lightly doped regions 116-1 and 116-2 is N-type, the transistor can be an NMOS transistor. In other examples, the transistor may be a PMOS transistor, where the conductivity type of the well region 112 is N-type, the conductivity type of the halo regions 117-1 and 117-2 is also N-type, and the conductivity type of the source region 114, the drain region 115, and the lightly doped regions 116-1 and 116-2 is P-type.

[0049] In some exemplary embodiments, a threshold voltage doped region with the same conductivity type as the well region is set, and the doping concentration of the threshold voltage doped region is adjusted to ensure that the threshold voltage of the transistor meets design requirements. For example, when the transistor is an NMOS transistor, boron (B) is typically used as the dopant element in the threshold voltage doped region. The inventors have found that one of the important factors leading to device mismatch is random dopant fluctuations (RDF), and the strength of RDF is closely related to the type of dopant ions in the threshold voltage doped region. When boron (B) ions are used as dopant ions, RDF is more likely to occur due to their small size, resulting in severe device mismatch problems. In addition, ions of other dopant elements with P-type conductivity (e.g., gallium (Ga) or indium (In)) have poor diffusion after doping due to their large ion size, making it difficult to meet device performance requirements.

[0050] According to the semiconductor structure provided in the embodiments of this application, by selecting doping elements for the threshold voltage doping region that have the opposite conductivity type to the well region, for example, when the conductivity type of the well region is P-type, phosphorus (P) or arsenic (As) is selected as the doping element for the threshold voltage doping region. Since phosphorus (P) ions or arsenic (As) ions have a larger volume, they are less prone to RDF (Reverse Deposition Factor), thereby improving the device mismatch problem. Furthermore, by increasing the doping concentration of the lightly doped region and the halo region (i.e., the doping concentration of the lightly doped region is 8 × 10⁻⁶), the device mismatch problem can be improved. 19 ~9×10 19 / cm 3 The doping concentration in the halo region is 5 × 10⁻⁶. 18~6×10 18 / cm 3 This is used to compensate for the dopant concentration in the threshold voltage doped region, which has the opposite conductivity type to the well region, thereby meeting the device design requirements.

[0051] This application also provides a memory device. Figure 2 This is a circuit diagram of a memory device provided in an embodiment of this application. For example, the memory device may be a DRAM memory.

[0052] like Figure 2 As shown, the memory device 200 may include a plurality of memory cells 201. For example, the plurality of memory cells 201 may form a memory cell array. In some embodiments, each memory cell 201 may include a transistor 202 and a capacitor 203. One of the source or drain terminals of the transistor 202 is connected to a first terminal of the capacitor 203, and the second terminal of the capacitor 203 is grounded. Another of the source or drain terminals of a row of transistors 202 is connected to each other and to the same bit line BL, and the gates of a row of transistors 202 are connected to each other and to the same word line WL. For example, the capacitor 203 may be used to store binary data, and the transistor 202 may act as a switch to access the capacitor 203.

[0053] In some implementations, one end of bit line BL may be connected to a sense amplifier (SA) 204. For example, during a read operation, a small voltage change occurs on bit line BL when transistor 202 is turned on and capacitor 203 charges bit line BL, or bit line BL charges capacitor 203. The sense amplifier 204 compares the voltage on bit line BL with a reference voltage provided on another separate bit line (not shown) and amplifies the voltage difference so that binary data is interpreted as 1 or 0, thereby reading the stored data in memory cell 201.

[0054] In some implementations, the sensing amplifier 204 may be a differential amplifier and include a set of devices (e.g., MOS devices) placed in a close proximity and with identical design dimensions. The inventors have found that device mismatch in the sensing amplifier 204 is closely related to the sensing margin and affects readout accuracy.

[0055] The memory device according to the embodiments of this application uses the semiconductor structure mentioned in any of the above embodiments (e.g., Figure 1 The semiconductor structure 100 shown is used in memory devices (e.g., sense amplifiers) to improve device mismatch problems, increase the sense margin of DRAM memory devices, and improve the read accuracy of DRAM memory devices.

[0056] It should be noted that in some implementation methods, Figure 1 The semiconductor structure 100 shown can be applied to sense amplifiers or other peripheral circuits of other types of memory devices to improve device mismatch problems. For example, the types of memory devices may include, but are not limited to, NAND flash memory, NOR flash memory, ferroelectric memory, magnetic variable memory, phase change memory, and resistive random access memory.

[0057] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this application. Figure 3 As shown, a method for manufacturing a semiconductor structure 300 (hereinafter referred to as manufacturing method 300) includes the following steps. For example, manufacturing method 300 can be used to form... Figure 1 The semiconductor structure 100 is shown.

[0058] S310 forms a well region in the substrate.

[0059] S320 forms a threshold voltage doped region above the well region.

[0060] S330 forms a gate structure on the surface of the threshold voltage doped region.

[0061] S340 forms lightly doped regions on both sides of the threshold voltage doped region.

[0062] S350 forms source and drain regions on both sides of the lightly doped region.

[0063] S360 forms a halo region between the source region and the drain region and the threshold voltage doped region, respectively.

[0064] The conductivity type of the threshold voltage doped region differs from that of the well region, and the doping concentration of the lightly doped region is 8 × 10⁻⁶. 19 ~9×10 19 / cm 3 The doping concentration in the halo region is 5 × 10⁻⁶. 18 ~6×10 18 / cm 3 .

[0065] According to the above embodiment, a semiconductor structure manufacturing method 300 is provided. A threshold voltage doped region with a conductivity type opposite to that of the well region is formed. For example, when the conductivity type of the well region is P-type, phosphorus (P) or arsenic (As) is selected as the doping element for the threshold voltage doped region. Since phosphorus (P) ions or arsenic (As) ions have a larger volume, they are less prone to RDF (Reverse Diffusion), thereby improving the device mismatch problem. Furthermore, by increasing the doping concentration of the lightly doped region and the halo region (i.e., the doping concentration of the lightly doped region is 8 × 10⁻⁶), the device structure can be further improved. 19 ~9×10 19 / cm 3 The doping concentration in the halo region is 5 × 10⁻⁶.18 ~6×10 18 / cm 3 This is used to compensate for the dopant concentration in the threshold voltage doped region, which has the opposite conductivity type to the well region, thereby meeting the device design requirements.

[0066] Figure 4 This is a flowchart illustrating a method for manufacturing a semiconductor structure according to another embodiment of this application. Figure 4 As shown, a method for manufacturing a semiconductor structure 400 (hereinafter referred to as manufacturing method 400) includes the following steps. For example, manufacturing method 400 can be used to form... Figure 1 The semiconductor structure 100 is shown.

[0067] S410 forms a well region in the substrate.

[0068] S420, an initial gate dielectric layer is formed on the surface of the well region.

[0069] S430, an initial gate conductive layer is formed on the surface of the initial gate dielectric layer.

[0070] S440, etching the initial gate dielectric layer and the initial gate conductive layer to form the gate structure.

[0071] In this process, after the initial gate dielectric layer is formed, a threshold voltage doped region is formed above the well region.

[0072] According to the above embodiment, a semiconductor structure manufacturing method 400 is provided. By arranging the step of forming the threshold voltage doped region after forming the initial gate dielectric layer, the thermal budget for forming the threshold voltage doped region can be reduced, the probability of RDF occurrence can be reduced, and the device mismatch problem can be improved.

[0073] The following is combined with Figures 5A to 5H as well as Figures 6A to 6C Examples of manufacturing methods 300 and 400 are provided.

[0074] Figures 5A to 5H This is a schematic diagram of the semiconductor structure provided in the embodiments of this application during the manufacturing process. The structure of the semiconductor structure during the manufacturing process is referred to as the intermediate structure.

[0075] Figure 5A An intermediate structure 500a is shown after the formation of the isolation structure 521. In some embodiments, such as Figure 5A As shown, firstly, the substrate 511 can be etched using photolithography and etching (e.g., dry etching and / or wet etching) processes to form isolation trenches (corresponding to the outer contour of the isolation structure 521). For example, viewed from the z-direction, the isolation trenches can surround the well region 512 to be formed (see reference). Figure 5BThen, a thin film deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, can be used to fill the isolation trench with an insulating material (e.g., silicon oxide (SiO2)) to form an isolation structure 521.

[0076] Figure 5B The intermediate structure 500b after the formation of the trap region 512 is shown. In some embodiments, such as Figure 5B As shown, firstly, a photoresist layer 523 covering the top surface of the intermediate structure 500b can be patterned using photolithography to expose the well region 512 while covering the area other than the well region 512. Then, using the photoresist layer 523 as a masking layer, ions with P-type or N-type conductivity dopants are implanted into the substrate 511 via ion implantation to form the well region 512. For example, the design requirements for the depth (i.e., the dimension in the z-direction) of the well region 512 can be met by adjusting the ion implantation energy. In one implementation of this application, ions with P-type conductivity dopants can be implanted into the substrate 511, thus the well region 512 can be referred to as a P-well region. For example, the P-type conductivity dopant may include boron (B). Next, the well region 512 can be annealed by heating to repair lattice damage caused by ion implantation.

[0077] Figure 5C An intermediate structure 500c is shown after the formation of the threshold voltage doped region 513 and the initial gate dielectric layer 519'. In some embodiments, such as Figure 5B and Figure 5C As shown, after forming the well region 512, the photoresist layer 523 can be removed, and then an initial gate dielectric layer 519' can be formed on the surface of the well region 512. In some examples, the substrate 511 can be made of silicon (Si), and an initial gate dielectric layer 519' made of silicon oxide (SiO2) can be formed on the surface of the well region 512 under heated conditions using an oxidation method (e.g., dry oxidation and / or wet oxidation). In other examples, an initial gate dielectric layer 519' made of other insulating materials can be formed on the surface of the well region 512 using a nitriding method or a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, other insulating materials may include silicon nitride (Si3N4), silicon oxynitride (SiO2), etc. x N y It can be one or more of the following: aluminum oxide (Al2O3), zirconium oxide (ZrO2), and hafnium oxide (HfO2).

[0078] In some embodiments, when the dopant element in the well region 512 has a P-type conductivity, ions of the P-type dopant element can be implanted into the surface of the well region 512 to form a threshold voltage doped region 513. For example, the P-type dopant element can be boron (B). The ion source for the ion implantation process is boron (B) atoms. In this embodiment, compared to ion sources such as BF2 plasma, boron atoms, as the ion source for the ion implantation process, have stronger penetration capabilities, increasing the ion implantation energy and allowing them to penetrate the initial gate dielectric layer 519' to reach the surface of the well region 512.

[0079] In other embodiments, when the dopant element in the well region 512 has a P-type conductivity, ions of a dopant element with an N-type conductivity can be implanted into the surface of the well region 512 to form a threshold voltage doped region 513. For example, the dopant element with an N-type conductivity can be phosphorus (P) or arsenic (As). In this embodiment, when the well region 512 has a P-type conductivity, phosphorus (P) or arsenic (As) is selected as the dopant element for the threshold voltage doped region 513. Since phosphorus (P) ions or arsenic (As) ions have a larger volume, they are less prone to RDF (Reverse Deposition Factor), thereby improving the device mismatch problem.

[0080] In some exemplary embodiments, after forming the well region, the photoresist layer may not be removed immediately. Instead, the photoresist layer is used as a masking layer, and ions of dopants with P-type or N-type conductivity are implanted into the surface of the well region via ion implantation to form a threshold voltage doped region. Next, an initial gate dielectric layer is formed on the surface of the well region. In this exemplary embodiment, the inventors discovered that the strength of RDF (Residual Defects), a significant factor leading to device mismatch, is also closely related to the thermal budget. That is, if the threshold voltage doped region is formed before the initial gate dielectric layer, the ions of the dopants in the threshold voltage doped region will undergo a heating process following the fabrication process of forming the initial gate dielectric layer, making RDF more likely to occur and thus exacerbating the device mismatch problem.

[0081] According to the manufacturing method provided in the embodiments of this application, compared with the exemplary embodiments described above, by arranging the step of forming the threshold voltage doped region after forming the initial gate dielectric layer, the thermal budget for forming the threshold voltage doped region can be reduced, the probability of RDF occurrence can be reduced, and the device mismatch problem can be improved.

[0082] Figure 5D An intermediate structure 500d is shown after the initial gate conductive layer 520' is formed. In some embodiments, such as Figure 5DAs shown, an initial gate conductive layer 520' can be formed on the surface of the initial gate dielectric layer 519' using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. For example, if the material of the initial gate conductive layer 520' is polysilicon (poly-Si), undoped polysilicon (poly-Si) can be deposited on the surface of the initial gate dielectric layer 519' by decomposing silane (SiH4) under heating conditions.

[0083] Figure 5E An intermediate structure 500e is shown after the formation of the gate structure 518. In some embodiments, such as Figure 5D and Figure 5E As shown, an etching process (e.g., dry etching and / or wet etching) can be used to etch the initial gate conductive layer 520' and the initial gate dielectric layer 519' to form the gate structure 518. During the formation of the gate structure 518, a portion of the initial gate conductive layer 520' and the initial gate dielectric layer 519' can be removed, leaving the remaining initial gate conductive layer 520' and the initial gate dielectric layer 519' as the gate conductive layer 520 and the gate dielectric layer 519, respectively (i.e., the gate structure 518).

[0084] Figure 5F The intermediate structure 500f is shown after the formation of lightly doped regions 516-1 and 516-2 and halo regions 517-1 and 517-2. In some embodiments, such as Figure 5F As shown, firstly, using the gate structure 518 as a masking layer, ions of doped elements with P-type or N-type conductivity are implanted into the threshold voltage doped region 513 and well region 512 on both sides of the gate structure 518 through an ion implantation process to form lightly doped regions 516-1 and 516-2. For example, the depth (i.e., the dimension in the z-direction) of the lightly doped regions 516-1 and 516-2 can be greater than the depth (i.e., the dimension in the z-direction) of the threshold voltage doped region 513. Then, using the gate structure 518 as a masking layer, halo regions 517-1 and 517-2 are formed through an ion implantation process. During halo ion implantation, the direction of ion implantation is not perpendicular to the thickness direction (i.e., the z-direction) of the substrate 511, but at a certain angle, while rotating the intermediate structure 500f, thereby forming pocket-like halo regions 517-1 and 517-2. Among them, the ion implantation depth of the halo regions 517-1 and 517-2 is deeper than that of the lightly doped regions 516-1 and 516-2, so that the halo regions 517-1 and 517-2 extend below the threshold voltage doped region 513.

[0085] In some embodiments, as described above, when the conductivity type of the doped element in the well region 512 is P-type and the conductivity type of the doped element in the threshold voltage doped region 513 is N-type, the doping concentrations of the lightly doped regions 516-1 and 516-2 and the halo regions 517-1 and 517-2 can be increased during the formation of the lightly doped regions 516-1 and 516-2 and the halo regions 517-1 and 517-2 (i.e., the doping concentration of the lightly doped regions 516-1 and 516-2 is 8 × 10⁻⁶). 19 ~9×10 19 / cm 3 The doping concentration of halo regions 517-1 and 517-2 is 5 × 10⁻⁶. 18 ~6×10 18 / cm 3 This is used to compensate for the doping ion concentration of the threshold voltage doped region 513, which has the opposite conductivity type to the well region 512, thereby meeting the device design requirements.

[0086] Figure 5G The intermediate structure 500g is shown after the sidewalls 522-1 and 522-2 are formed. In some embodiments, such as Figure 5F and Figure 5G As shown, a dielectric layer (not shown) is first formed on the top surface of the intermediate structure 500f using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Then, an etching process (e.g., dry etching) is used to remove the portion of the dielectric layer covering the top surface of the gate structure 518, the portion covering the top surfaces of the lightly doped regions 516-1 and 516-2 and located away from the gate structure 518 in the x-direction, and the portion covering the isolation structure 521, such that the remaining dielectric layer covers the top surfaces of the lightly doped regions 516-1 and 516-2 and is located on both sides of the gate structure 518 in the x-direction. That is, the remaining dielectric layer serves as sidewalls 522-1 and 522-2 and is used for the subsequent formation of the source region 514 and the drain region 515 (see reference). Figure 5H During the process, it serves as a masking layer for the lightly doped regions 516-1 and 516-2.

[0087] Figure 5H A semiconductor structure 500 is shown after the source region 514 and drain region 515 have been formed. In some embodiments, such as Figure 5HAs shown, ions of doped elements with P-type or N-type conductivity can be implanted into both sides of the threshold voltage doped region 513 covered by the gate structure 518 and sidewalls 522-1 and 522-2 via ion implantation to form the source region 514 and drain region 515, respectively. The ion implantation depth of the source region 514 and drain region 515 is deeper than that of the lightly doped regions 516-1 and 516-2. For example, if the gate conductive layer 520 in the gate structure 518 is made of undoped polysilicon (poly-Si), the gate conductive layer 520 can be doped during the formation of the source region 514 and drain region 515 to improve conductivity.

[0088] Figures 6A to 6C This is a schematic diagram of the semiconductor structure provided in another embodiment of this application during the manufacturing process. For the purpose of brevity, it is not shown here. Figures 5A to 5H The same content as shown in the embodiments will not be repeated here.

[0089] Figure 6A An intermediate structure 600a is shown after the initial gate dielectric layer 619' and the initial gate conductive layer 620' have been formed. In some embodiments, such as Figure 5B and Figure 6A As shown, after forming the well region 612, an initial gate dielectric layer 619' is formed on the surface of the well region 612. In some examples, the substrate 611 may be made of silicon (Si), and the initial gate dielectric layer 619' made of silicon oxide (SiO2) may be formed on the surface of the well region 612 under heated conditions using an oxidation method (e.g., dry oxidation and / or wet oxidation). In other examples, an initial gate dielectric layer 619' made of other insulating materials may be formed on the surface of the well region 612 using a nitriding method or a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, other insulating materials may include silicon nitride (Si3N4), silicon oxynitride (SiO2), etc. x N y It can be one or more of the following: aluminum oxide (Al2O3), zirconium oxide (ZrO2), and hafnium oxide (HfO2).

[0090] Furthermore, an initial gate conductive layer 620' can be formed on the surface of the initial gate dielectric layer 619' using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, if the material of the initial gate conductive layer 620' is polysilicon (poly-Si), undoped polysilicon (poly-Si) can be deposited on the surface of the initial gate dielectric layer 619' by decomposing silane (SiH4) under heating conditions.

[0091] Figure 6BAn intermediate structure 600b is shown after the initial gate dielectric layer 619' and the initial gate conductive layer 620' have been formed. In some embodiments, such as Figure 6B As shown, when the dopant element in the well region 612 has a P-type conductivity, ions of the P-type dopant element can be implanted into the surface of the well region 612 to form a threshold voltage doped region 613. For example, the P-type dopant element can be boron (B). The ion source for the ion implantation process is boron (B) atoms. In this embodiment, compared to ion sources such as BF2 plasma, boron atoms, as the ion source for the ion implantation process, have stronger penetration capabilities, increasing the ion implantation energy, thereby allowing them to penetrate the initial conductive layer 620' and the initial gate dielectric layer 619' to reach the surface of the well region 612.

[0092] In other embodiments, when the dopant element in the well region 612 has a P-type conductivity, ions of a dopant element with an N-type conductivity can be implanted into the surface of the well region 612 to form a threshold voltage doped region 613. For example, the dopant element with an N-type conductivity can be phosphorus (P) or arsenic (As). In this embodiment, when the well region 612 has a P-type conductivity, phosphorus (P) or arsenic (As) is selected as the dopant element for the threshold voltage doped region 613. Since phosphorus (P) ions or arsenic (As) ions have a larger volume, they are less prone to RDF (Reverse Deposition Factor), thereby improving the device mismatch problem.

[0093] Figure 6C An intermediate structure 600c is shown after the formation of the gate structure 618. In some embodiments, such as Figure 6B and Figure 6C As shown, an etching process (e.g., dry etching and / or wet etching) can be used to etch the initial gate conductive layer 620' and the initial gate dielectric layer 619' to form the gate structure 618. During the formation of the gate structure 618, a portion of the initial gate conductive layer 620' and the initial gate dielectric layer 619' can be removed, leaving the remaining initial gate conductive layer 620' and the initial gate dielectric layer 619' as the gate conductive layer 620 and the gate dielectric layer 619, respectively (i.e., the gate structure 618).

[0094] In some implementations, the following methods may be used: Figures 5F to 5H The method shown forms lightly doped regions, halo regions, sidewalls, source regions, and drain regions, thereby forming a semiconductor structure.

[0095] According to the manufacturing method provided in the embodiments of this application, by arranging the step of forming the threshold voltage doped region after forming the initial gate conductive layer, not only can the thermal budget for forming the threshold voltage doped region be reduced, and the probability of RDF occurrence be reduced, thereby improving the device mismatch problem, but the initial gate conductive layer can also be used as an ion implantation barrier layer for forming the threshold voltage doped region, thereby reducing the difficulty of ion implantation energy control. On the other hand, arranging the step of forming the threshold voltage doped region before etching the initial gate conductive layer and the initial gate dielectric layer to form the gate structure can avoid the implantation depth of the threshold voltage doped region being different due to the different thicknesses of the areas not covered by the gate structure and the areas covered by the gate structure after the gate structure is formed, thus affecting the implantation depth of the subsequently formed lightly doped region, halo region, source region, and drain region.

[0096] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, characterized by, include: Substrate; The well region is located in the substrate; A threshold voltage doped region is located above the well region; The lightly doped region is located on both sides of the threshold voltage doped region; The source region and drain region are located on both sides of the lightly doped region, respectively; The halo region is located between the source region and the drain region and the threshold voltage doped region, respectively. as well as A gate structure is located on the surface of the threshold voltage doped region; The conductivity type of the threshold voltage doped region is different from that of the well region, and the doping concentration of the lightly doped region is 8 × 10⁻⁶. 19 ~9×10 19 / cm 3 The doping concentration of the halo region is 5 × 10⁻⁶. 18 ~6×10 18 / cm 3 .

2. The semiconductor structure of claim 1, wherein, The conductivity type of the well region is P-type, and the conductivity type of the threshold voltage doped region is N-type.

3. The semiconductor structure of claim 2, wherein, The doping element in the threshold voltage doping region is phosphorus or arsenic.

4. The semiconductor structure of claim 2, wherein, The lightly doped region is doped with arsenic, and the halo region is doped with boron.

5. The semiconductor structure according to claim 1, wherein, The doping concentrations of the source region and the drain region are both greater than the doping concentration of the lightly doped region.

6. The semiconductor structure of claim 1, wherein, It also includes isolation structures located on both sides of the source region and the drain region away from the threshold voltage doped region.

7. The semiconductor structure of claim 1, wherein, The gate structure includes a gate dielectric layer and a gate conductive layer, wherein the gate dielectric layer is located on the surface of the threshold voltage doped region, and the gate conductive layer is located on the surface of the gate dielectric layer.

8. A memory device, comprising: include: At least one semiconductor structure as described in any one of claims 1 to 7.

9. The memory device of claim 8, wherein, The memory device is a DRAM memory, and the semiconductor structure is used to form a sense amplifier.

10. A method for manufacturing a semiconductor structure, characterized in that, include: A well region is formed in the substrate; A threshold voltage doped region is formed above the well region; A gate structure is formed on the surface of the threshold voltage doped region; Lightly doped regions are formed on both sides of the threshold voltage doped region; A source region and a drain region are formed on both sides of the lightly doped region, respectively; as well as A halo region is formed between the source region and the drain region and the threshold voltage doped region, respectively. The conductivity type of the threshold voltage doped region is different from that of the well region, and the doping concentration of the lightly doped region is 8 × 10⁻⁶. 19 ~9×10 19 / cm 3 The doping concentration of the halo region is 5 × 10⁻⁶. 18 ~6×10 18 / cm 3 .

11. A method of manufacturing a semiconductor structure, characterized by, include: A well region is formed in the substrate; An initial gate dielectric layer is formed on the surface of the well region; An initial gate conductive layer is formed on the surface of the initial gate dielectric layer; as well as The initial gate dielectric layer and the initial gate conductive layer are etched to form a gate structure; Specifically, after the initial gate dielectric layer is formed, a threshold voltage doped region is formed above the well region.

12. The manufacturing method of claim 11, wherein, The threshold voltage doped region is formed after the initial gate conductive layer is formed and before the initial gate dielectric layer and the initial gate conductive layer are etched to form the gate structure.

13. The manufacturing method of claim 11, wherein, After forming the initial gate dielectric layer, forming a threshold voltage doped region above the well region includes: The threshold voltage doped region is formed by implanting ions of dopants with P-type conductivity onto the surface of the well region using an ion implantation process.

14. The manufacturing method according to claim 13, wherein, The doping element with P-type conductivity is boron, and the ion source for the ion implantation process is boron atoms.

15. The manufacturing method of claim 11, wherein, After forming the initial gate dielectric layer, forming a threshold voltage doped region above the well region includes: The threshold voltage doped region is formed by implanting ions of doped elements with N-type conductivity onto the surface of the well region through an ion implantation process. The method further includes, after etching the initial gate dielectric layer and the initial gate conductive layer to form the gate structure: A lightly doped region and a halo region are formed on both sides of the threshold voltage doped region covered by the gate structure, wherein the halo region extends below the threshold voltage doped region, and the doping concentration of the lightly doped region is 8 × 10⁻⁶. 19 ~9×10 19 / cm 3 The doping concentration of the halo region is 5 × 10⁻⁶. 18 ~6×10 18 / cm 3 .

16. The manufacturing method of claim 15, wherein, The doping element having N-type conductivity is phosphorus or arsenic.

17. The manufacturing method of claim 11, wherein, Forming a well region in the substrate includes: Ions of a dopant element with P-type conductivity are implanted into the substrate using an ion implantation process; and The well region is then annealed.

18. The manufacturing method of claim 11, wherein, The substrate is made of silicon, the initial gate dielectric layer is made of silicon oxide, and forming the initial gate dielectric layer on the surface of the well region includes: A silicon oxide layer is formed on the surface of the well region by thermal oxidation.

19. The manufacturing method of claim 11, wherein, Also includes: Source and drain regions are formed on both sides of the threshold voltage doped region covered by the gate structure using an ion implantation process.

Images