TFT substrate and display device

Abstract

The invention relates to a TFT substrate and a display device. A thin film transistor (TFT) substrate includes a TFT on a substrate and including a gate electrode, a first semiconductor layer and a second semiconductor layer, where the first semiconductor layer and the second semiconductor layer are made of polycrystalline silicon, vertically stacked with the gate electrode therebetween, where the first semiconductor layer and the second semiconductor layer are electrically connected in series with each other, the first channel portion and the second channel portion respectively include a first channel portion and a second channel portion, and wherein at least one of the first channel portion and the second channel portion has a curved structure in a top view.

Description

[0001] This application is a divisional application of the original invention patent application with application number 201910837242.9 (application date: September 5, 2019, invention name: TFT substrate and light-emitting display device including the TFT substrate). Technical Field

[0002] The present disclosure relates to a thin film transistor (TFT) substrate and a light emitting display device including the substrate. Background Art

[0003] Generally, a thin film transistor (TFT) substrate having a TFT formed therein is used for a light-emitting display device including an organic light-emitting display device (OLED) which is a self-light-emitting device.

[0004] The TFT uses amorphous silicon or polycrystalline silicon for its active layer. Since polycrystalline silicon has excellent mobility, etc. compared with amorphous silicon, a display device requiring high performance (such as high resolution) uses a TFT substrate including polycrystalline silicon.

[0005] The driving TFT in the pixel is an element which is connected to the light emitting diode and drives the light emitting diode, and needs to have a long length of the channel to ensure stable driving characteristics.

[0006] However, as the resolution of a display device increases, the size of a pixel decreases. Therefore, there is a problem that the driving TFT does not have a required channel length. Summary of the invention

[0007] Accordingly, the present invention is directed to a TFT substrate and a light emitting display device including the same that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0008] An advantage of the present invention is to provide a TFT substrate and a light emitting display device including the TFT substrate, which can ensure a channel length of a driving TFT using polysilicon and realize stable driving characteristics.

[0009] Other features and advantages of the present invention will be set forth in the following description, and in part will be apparent from the description, or may be learned through practice of the present invention. These and other advantages of the present invention will be realized and obtained through the structures particularly pointed out in the written description and its claims as well as the accompanying drawings.

[0010] To achieve these and other advantages, and in accordance with the purposes of the present invention, as illustrated and broadly described herein, a thin film transistor (TFT) substrate includes: a TFT located on the substrate and including a gate, a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are made of polycrystalline silicon, are vertically stacked with the gate therebetween, wherein the first semiconductor layer and the second semiconductor layer are electrically connected in series to each other and include a first channel portion and a second channel portion, respectively, and wherein at least one of the first channel portion and the second channel portion has a curved structure in a top view.

[0011] On the other hand, a display device includes: a thin film transistor (TFT) substrate, the TFT substrate including a TFT on the substrate; and a first electrode, the first electrode connected to the source of the TFT, wherein the TFT includes a gate, a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are made of polycrystalline silicon, vertically stacked with the gate therebetween, wherein the first semiconductor layer and the second semiconductor layer are electrically connected to each other in series and respectively include a first channel portion and a second channel portion, and wherein at least one of the first channel portion and the second channel portion has a curved structure in a top view.

[0012] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention. In the drawings:

[0014] Figure 1 is a top view schematically showing a TFT substrate of an OLED display device according to the present invention;

[0015] Figure 2 It is schematically shown Figure 1 A circuit diagram of a pixel area;

[0016] Figure 3 is a diagram schematically showing a planar structure of a driving TFT in a pixel region according to a first embodiment of the present invention;

[0017] Figure 4 is along Figure 3 The cross-sectional view obtained along the IV-IV' line;

[0018] Figure 5 is along Figure 3 The cross-sectional view obtained along the V-V' line;

[0019] Figure 6 is a cross-sectional view schematically showing the structure of a driving TFT in a pixel region according to a second embodiment of the present invention;

[0020] Figure 7 and Figure 8 are a top view and a cross-sectional view schematically showing the structure of a driving TFT in a pixel region according to a third embodiment of the present invention, respectively; and

[0021] Fig. 9 is a plan view schematically showing the structure of a driving TFT in a pixel region according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0022] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings.Throughout the drawings, the same reference numerals may be used to refer to the same or similar parts.

[0023] The TFT substrate according to the embodiment of the present invention can be applied to all kinds of electronic devices using TFTs. For example, the TFT substrate can be applied to various electronic devices including display devices and sensor panels.

[0024] For explanation purposes, the embodiments of the present invention are described by taking a TFT substrate for an organic light emitting display (OLED) as an example.

[0025] Figure 1 FIG. 1 is a top view schematically showing a TFT substrate of an OLED display device according to the present invention. Figure 2 It is schematically shown Figure 1 Circuit diagram of the pixel area.

[0026] Reference Figure 1 and Figure 2 The TFT 10 may include a display area AA as an active area to display an image, and a non-display area NA as an inactive area located around (or surrounding) the display area AA.

[0027] The TFT substrate 10 includes array elements for driving the OLED and may be referred to as an array substrate.

[0028] In the display area AA, a plurality of pixel regions P may be arranged in a matrix form. The plurality of pixel regions P may include, for example, a red pixel region, a green pixel region, and a blue pixel region P that display red, green, and blue, respectively. The red pixel region, the green pixel region, and the blue pixel region P may be alternately arranged in one direction.

[0029] Each of the pixel regions P may include a driving element for operating the pixel region P. For example, a plurality of TFTs and light emitting diodes OP may be formed in the pixel region P.

[0030] In the non-display area NA, a driving circuit for driving the pixel area P in the display area AA may be disposed.

[0031] For example, a scan driving circuit SDC that outputs a scan signal such as a gate signal and supplies the scan signal to the pixel area P may be located in the non-display area NA. The scan driving circuit SDC may be directly formed in the TFT substrate 10 .

[0032] The scan driving circuit SDC directly formed in the TFT substrate 10 may be referred to as a GIP (gate in panel) type driving circuit, which may be formed in the process of manufacturing the TFT 10. The GIP type scan driving circuit SDC may include a plurality of TFTs for driving circuits, and the plurality of TFTs for driving circuits may have a structure that is the same as or similar to that of the TFTs of the pixel region P.

[0033] Reference Figure 2 and Figure 3 The structure of the pixel region P is described in detail. For the purpose of explanation, an N (negative) type TFT is used in the pixel region P as an example.

[0034] In the pixel region P, a plurality of TFTs for pixels including a switching TFT STr and a driving TFT DTr, a light emitting diode OD as a light emitting element, and a storage capacitor Cst may be formed.

[0035] The switching TFT STr may be connected to the gate line GL and the data line DL which cross each other to define the pixel region P. For example, a gate electrode of the switching TFT STr may be connected to the gate line GL, and a drain electrode of the switching TFT STr may be connected to the data line DL.

[0036] The switching TFT STr is turned on in response to a gate voltage applied through the gate line GL located at a corresponding row line, and thus, a data voltage supplied through the data line DL is applied to the driving TFT DTr.

[0037] The driving TFT DTr may be connected to the switching TFT STr and the light emitting diode OD. For example, the gate electrode of the driving TFT DTr may be electrically connected to the source electrode of the switching TFT STr, and the source electrode of the driving TFT DTr may be electrically connected to the light emitting diode OD. The drain electrode of the driving TFT DTr may be configured to receive a first power supply voltage Vdd. In the case where the driving TFT DTr is an N-type TFT, the first power supply voltage Vdd may be a high power supply voltage Vdd.

[0038] The light emitting current applied to the light emitting diode OD may be controlled according to a voltage applied to the gate electrode of the driving TFT DTr.

[0039] The light emitting diode OD may be configured as, for example, an organic light emitting diode whose light emitting material layer is made of an organic material. The light emitting diode OD emits light according to a light emitting current from the driving TFT DTr.

[0040] The light emitting diode OD may be configured such that a first electrode (eg, anode) thereof is connected to the source of the driving TFT DTr, and a second electrode (eg, cathode) thereof may be applied with a second power voltage Vss (eg, low power voltage Vss).

[0041] The storage capacitor Cst may be connected to the gate electrode of the driving TFT DTr and serve to maintain a voltage applied to the gate electrode of the driving TFT DTr until the next frame.

[0042] The storage capacitor Cst may be configured such that a first electrode thereof is connected to the gate electrode of the driving TFT DTr, and a second electrode thereof is connected to, for example, the drain electrode (or source electrode) of the driving TFT DTr.

[0043] In the present invention, in order to stably secure the channel length of the driving TFT DTr, the driving TFT DTr may be configured with two sub-driving TFTs DTr1 and DTr2 stacked in a direction perpendicular to the substrate.

[0044] For example, the driving TFT DTr may be configured to include a first sub driving TFT DTr1 located on a substrate and a second sub driving TFT DTr2 located on the first sub driving TFT DTr2. The first sub driving TFT DTr1 and the second sub driving TFT DTr2 may be connected to each other in series and share a gate. The first sub driving TFT DTr1 may be applied with a first power supply voltage Vdd at a drain thereof, and the second sub driving TFT DTr2 may be connected to the light emitting diode OD at a source thereof.

[0045] Since the driving TFT DTr is configured as a vertical double-layer stack structure, the length of the channel of the driving TFT DTr increased in the limited area of ​​the pixel region can be ensured as needed. Therefore, the degradation of driving characteristics, such as the decrease in the stability of the drain current and the increase in the off-current due to the degradation of the hot carrier reliability due to the short channel length, can be improved.

[0046] In the present invention, in addition to increasing the length of the channel by the vertical stacking structure, at least one sub-driving TFT can be configured such that its channel is formed to extend in two directions in a top view. Therefore, the required channel length can be satisfied with a minimum area.

[0047] In order to increase the length of the channel in a top view, the channel of at least one sub-TFT may be configured to have a bent structure. In other words, the semiconductor layer of at least one sub-TFT may be configured to have a bent structure.

[0048] The switching TFT STr may be configured to have a single TFT structure. For example, the switching TFT STr may be formed to have a structure that is the same as or similar to that of the first sub driving TFT DTr1 or the second sub driving TFT DTr2.

[0049] Alternatively, the switching TFT STr may be configured to have a dual TFT stack structure similar to the structure of the driving TFT DTr.

[0050] At least one of the TFTs formed in the scan driving circuit SDC may be configured to have a double TFT stack structure similar to the structure of the driving TFT DTr.

[0051] Embodiments of a vertical stack structure and a bent structure in a plan view of the driving TFT DTr with respect to a semiconductor layer will be described below.

[0052] Figure 3 is a view schematically showing a planar structure of a driving TFT in a pixel region according to a first embodiment of the present invention. Figure 4 is along Figure 3 The cross-sectional view is obtained along the line IV-IV', and Figure 5 is along Figure 3 The cross-sectional view is obtained along the V-V' line.

[0053] Reference Figures 3 to 5 , in the TFT substrate 10 , the driving TFT DTr may be configured to have a double-layer stacked structure in a direction perpendicular to the surface of the substrate 11 .

[0054] For example, the first sub drive TFT DTr1 as the lower drive TFT may be formed on the substrate 11 , and the second sub drive TFT DTr2 as the upper drive TFT may be formed on the first sub drive TFT DTr1 .

[0055] In the vertical stack structure, the gate electrode 45 may serve as a common gate electrode shared by both the first sub driving TFT DTr1 and the second sub driving TFT DTr2 .

[0056] The first sub driving TFT DTr1 and the second sub driving TFT DTr2 may be connected to each other in series.

[0057] The cross-sectional structures of the first sub-driving TFT DTr1 and the second sub-driving TFT DTr2 are shown in FIG. Figure 4 , the first sub driving TFT DTr1 may have a top gate structure, and the second sub driving TFT DTr2 may have a bottom gate structure.

[0058] In this regard, in each pixel region P, a first semiconductor layer 21 as a semiconductor layer of the first sub-driving TFT DTr1 may be formed on the substrate 11. The first semiconductor layer 21 may be made of polycrystalline silicon.

[0059] The buffer layer may be located under the first semiconductor layer and formed on the entire substrate 11 .

[0060] The first semiconductor layer 21 may include: a first channel portion CH1, which is a portion of the first semiconductor layer 21 corresponding to the gate 45 thereon (i.e., overlapping the gate 45); and a first source portion S1 and a first drain portion D1, which are located on both sides of the first channel portion CH1.

[0061] The first source portion S1 and the first drain portion D1 are portions highly doped with impurities (eg, N-type or P-type dopants). In the doping process of the first source portion S1 and the first drain portion D1, the gate 45 may be used as a doping mask.

[0062] A first gate insulating layer 31 as an insulating layer may be formed on the first semiconductor layer 21. The first gate insulating layer 31 may be formed on the entire substrate 11. The first gate insulating layer 31 may be made of an inorganic insulating material (eg, silicon oxide (SiO 2 ) or silicon nitride (SiNx).

[0063] A gate electrode 45 corresponding to the first channel portion CH1 may be formed on the first gate insulating layer 31. The gate electrode 45 may serve as a top gate electrode of the first sub driving TFT DTr1.

[0064] A second gate insulating layer 32 as an insulating layer may be formed on the gate 45. The second gate insulating layer 32 may be formed on the entire substrate 11. The second gate insulating layer 32 may be made of an inorganic insulating material (eg, silicon oxide (SiO 2 ) or silicon nitride (SiNx).

[0065] The second semiconductor layer 22, which is a semiconductor layer of the second sub driving TFT DTr2, may be formed on the second gate insulating layer 32. The second semiconductor layer 22 may be made of polysilicon.

[0066] The second semiconductor layer 22 may include: a second channel portion CH2, which is a portion of the second semiconductor layer 22 corresponding to the gate 45 thereunder (i.e., overlapping the gate 45); and a second source portion S2 and a second drain portion D2, which are located on both sides of the second channel portion CH2.

[0067] The second source portion S2 and the second drain portion D2 are portions highly doped with impurities. For example, the second source portion S2 and the second drain portion D2 may be doped with a dopant of the same type (N-type or P-type) as that of the first source portion S1 and the first drain portion D1. In the doping process of the second source portion S2 and the second drain portion D2, for example, the photoresist pattern may be used as a doping mask.

[0068] Since the gate electrode 45 is located under the second semiconductor layer 22 , the gate electrode may serve as a bottom gate of the second sub driving TFT DTr2 .

[0069] In addition, a passivation layer 50 as an insulating layer may be formed on the second semiconductor layer 22. The passivation layer 50 may be made of an inorganic insulating material or an organic insulating material. The passivation layer 50 may be formed to have a single layer or multi-layer structure.

[0070] Reference Figure 5 In each pixel region P, a drain electrode 71 and a source electrode 73 may be formed on the passivation layer 50 .

[0071] The drain electrode 71 may be connected to the first drain portion D1 of the first sub driving TFT DTr1 , and the source electrode 73 may be connected to the second source portion S2 of the second sub driving TFT DTr2 .

[0072] In this regard, since the first drain portion D1 of the first sub driving TFT DTr1 may substantially function as the drain portion of the driving TFT DTr, the drain electrode 71 may be formed to contact the first drain portion D1. Since the second source portion S2 of the second sub driving TFT DTr2 may substantially function as the source portion of the driving TFT DTr, the source electrode 73 may be formed to contact the second source portion S2.

[0073] To form contact between the first drain portion D1 and the drain electrode 71, the insulating layer therebetween (e.g., the passivation layer 50 and the first and second gate insulating layers 31 and 32) may have a first contact hole CT1 formed therein. Thus, the first drain portion D1 may contact the drain electrode 71 through the first contact hole CT1.

[0074] To form contact between the second source portion S2 and the source 73 , an insulating layer (eg, the passivation layer 50 ) therebetween may have a second contact hole CT2 formed therein. Thus, the second source portion S2 may contact the source 73 through the second contact hole CT2 .

[0075] In addition, the first sub drive TFT DTr1 and the second sub drive TFT DTr2 may be electrically connected to each other in series through the connection electrode 75 .

[0076] In this regard, the connection electrode 75 may be formed of the same metal material and in the same process as the drain electrode 71 and the source electrode 73 .

[0077] The connection electrode 75 may contact the first source portion S1 and the second drain portion D2 located below the connection electrode 75 through the third contact hole CT3 .

[0078] To this end, the third contact hole CT3 may be formed in the passivation layer 50 and the first and second gate insulating layers 31 and 32, and may also be formed in the second drain portion D2. In other words, the third contact hole CT3 may be formed to penetrate the second drain portion D2.

[0079] In this case, the connection electrode 75 may contact the inner surface of the second drain portion D2 (i.e., the inner surface exposed by the third contact hole CT3 (or surrounding or defining the third contact hole CT3)), and contact the top surface of the first source portion S1. Alternatively, the first source portion S1 may be formed similarly to the second drain portion D2 to have the third contact hole CT3 therein, in which case the connection electrode 75 may contact the inner surface of the first source portion S1 exposed by the third contact hole CT3.

[0080] The first source portion S1 and the second drain portion D2 overlapping and under the connection electrode 75 may be electrically connected by the connection electrode 75, and thus the first and second sub drive TFTs DTr1 and DTr2 (or the first and second semiconductor layers 21 and 22) may be connected in series.

[0081] In this way, by using the connection electrode 75 made of the metal material, a stable electrical connection may be formed between the first sub driving TFT DTr1 and the second sub driving TFT DTr2 .

[0082] In this regard, a method may be considered in which the second drain portion D2 is directly connected to the first source portion S1 through a contact hole without the connection electrode 75. However, in this case, the second drain portion D2 has a large resistance due to its material characteristics, and thus the connection resistance between the first sub driving TFT DTr1 and the second sub driving TFT DTr2 increases.

[0083] However, in this embodiment, since the connection electrode 75 made of a metal material is used, the connection resistance between the first sub driving TFT DTr1 and the second sub driving TFT DTr2 is reduced, and a stable electrical connection may be achieved.

[0084] As described above, the driving TFT DTr is configured in a vertical double-layer stack structure in which the first semiconductor layer 21 and the second semiconductor layer 22 are arranged so that the gate electrode 45 is located above the first semiconductor layer 21 and below the second semiconductor layer 22. Thus, double channel portions CH1 and CH2 overlapping each other in the vertical direction of the substrate 11 are formed, and therefore, the length of the channel can be increased by at least two times as compared with a single-layer stack structure of the related art using a single semiconductor.

[0085] In this embodiment, the first semiconductor layer 21 and the second semiconductor layer 22 may be formed to have a curved structure in a top view, and the first channel portion CH1 and the second channel portion CH2 thereof may have a curved structure in a top view. Therefore, the length of the channel may be ensured as much as possible in a limited area.

[0086] In this regard, reference Figure 3 In a top view, the first semiconductor layer 21 may include a first portion extending in a first direction (eg, an x ​​direction), and a second portion bent from the first portion and extending in a second direction (eg, a −y direction) different from the first direction.

[0087] As such, the first semiconductor layer 21 may be formed to have a bent structure in a plan view.

[0088] The bent structure may be similarly applied to the first channel portion CH1 of the first semiconductor layer 21. The first channel portion CH1 may include a first channel component CH1a extending in a first direction as an x ​​direction, and a second channel component CH1b bent from the first channel component CH1a and extending in a second direction as a -y direction.

[0089] Therefore, the first channel portion CH1 may include a first channel length L1 as a length of a channel in a first direction defined by the first channel component CH1a, and a second channel length L2 as a length of a channel in a second direction defined by the second channel component CH1b. Therefore, the first channel portion CH1 may have a channel length L1+L2.

[0090] The second semiconductor layer 22 may include a third portion extending in a first direction as an x-direction and overlapping with the first portion of the first semiconductor layer 21, and a fourth portion bent from the third portion and extending in a third direction different from the first and second directions (e.g., a y-direction (or +y-direction)).

[0091] In this way, the second semiconductor layer 22 may be formed to have a bent structure in a plan view.

[0092] The bent structure may be similarly applied to the second channel portion CH2 of the second semiconductor layer 22. The second channel portion CH2 may include a third channel portion CH2a extending in a first direction as an x-direction and overlapping the first channel portion CH1a, and a fourth channel portion CH2b bent from the third channel portion CH2a and extending in a third direction as a +y-direction.

[0093] The third channel component CH2a of the second channel portion CH2 may extend in a first direction which is the same direction as the first channel component CH1a of the first channel portion CH1 and may overlap the first channel component CH1a by the same length. Therefore, the third channel component CH2a may have substantially the same channel length as the first channel component CH1a, i.e., L1=L3.

[0094] Therefore, the second channel portion CH2 may include a third channel length L3 as the length of the channel in the first direction defined by the third channel component CH2a, and a fourth channel length L4 as the length of the channel in the third direction defined by the fourth channel component CH2b. Therefore, the second channel portion CH2 may have a channel length, L3+L4=L1+L4.

[0095] The first and second semiconductor layers 21 and 22 and the first and second channel portions CH1 and CH2 thereof may have a bent structure, and a bending direction of the first and second channel portions CH1 and CH2 may be different, eg, opposite to each other.

[0096] Therefore, the total channel length of the driving TFTDTr configured with the vertically stacked first sub-driving TFT DTr1 and the second sub-driving TFT DTr2 can be the sum of L1+L2 and L3(=L1)+L4 (L1+L2)+(L3+L4)=2L1+L2+L4, wherein L1+L2 is the channel length of the first channel portion CH1 located at the lower layer, and L3(=L1)+L4 is the channel length of the second channel portion CH2 located at the upper layer.

[0097] In this way, the first channel portion CH1 and the second channel portion CH2 are configured to be arranged in a vertical stack structure with the gate 45 therebetween and have a bent structure in a plane, and thus, the channel length relative to the occupied area can be maximized. Therefore, the channel length of the driving TFT DTr can be ensured while achieving the required driving characteristics with the minimum area, and the area availability of the pixel region P can be improved.

[0098] Therefore, even if the resolution increases, the driving TFT DTr ensuring stable driving characteristics can be effectively provided in the limited pixel area P.

[0099] In addition, since the first channel portion CH1 and the second channel portion CH2 are configured to bend and extend in different directions (for example, the -y direction and the +y direction, respectively), the channel lengths in different directions can be adjusted individually, so the channel length of the first channel portion CH1 and the channel length of the second channel portion CH2 can be freely adjusted as needed.

[0100] For example, the channel length of the first channel portion CH1 in the second direction as the -y direction and the channel length of the second channel portion CH2 in the third direction as the +y direction may be equal or different. In other words, the first and second sub drive TFTs DTr1 and DTr2 may be formed in a symmetrical or asymmetrical form.

[0101] The channel length of the first channel portion CH1 and the channel length of the second channel portion CH2 can be individually adjusted by bending the first channel portion CH1 and the second channel portion CH2 in different directions. Therefore, various driving characteristics required by the first sub driving TFT DTr1 and the second sub driving TFT DTr2, respectively, can be satisfied, and thus the driving TFT DTr suitable for the required characteristics can be effectively provided.

[0102] Figure 6 is a cross-sectional view schematically showing the structure of a driving TFT in a pixel region according to a second embodiment of the present invention.

[0103] Detailed description of components similar to those of the first embodiment may be omitted.

[0104] Reference Figure 6 , the driving TFT DTr of this embodiment may be an N-type TFT and use an LDD (Lightly Doped Drain) TFT.

[0105] In this regard, the first semiconductor layer 21 of the first sub-driving TFT DTr1 may include a first lightly doped drain (LDD) portion LDD1 between the first channel portion CH1 and the first source portion S1 and between the first channel portion CH1 and the first drain portion D1.

[0106] Similarly, the second semiconductor layer 22 of the second sub driving TFT DTr2 may include a second LDD portion LDD2 between the second channel portion CH2 and the second source portion S2 and between the second channel portion CH2 and the second drain portion D2.

[0107] By applying the LDD portions LDD1 and LDD2 to the driving TFT DTr having the vertical stack structure and the bent structure, the degradation of driving characteristics caused by the short channel length may be further improved.

[0108] Furthermore, in this embodiment, the size, ie, the length of the first LDD portion LDD1 and the second LDD portion LDD2 may be individually adjusted. For example, the first length LL1 of the first LDD portion LDD1 and the second length LL2 of the second LDD portion LDD2 may be equal or different.

[0109] In particular, in the case where the first channel portion CH1 and the second channel portion CH2 are bent in different directions (for example, in the -y direction and the +y direction, respectively), one end of the first channel portion CH1 and one end of the second channel portion CH2 are spaced apart from each other and separated from each other. In other words, the end of the first channel portion CH1 on the drain side and the end of the second channel portion CH2 on the source side are spaced apart from each other and separated from each other.

[0110] Therefore, the first LDD portion LDD1 at the drain side of the first channel portion CH1 is substantially unaffected by the doping process of the second semiconductor layer 22 over the first semiconductor layer 21. Therefore, the first length LL1 of the first LDD portion LDD1 and the second length LL2 of the second LDD portion LDD2 may be individually adjusted.

[0111] Therefore, optimal LDD portions respectively required for the first and second sub driving TFTs DTr1 and DTr2 may be formed, and thus the driving TFT DTr suitable for required characteristics may be effectively provided.

[0112] Figure 7 and Figure 8 1 and 2 are a plan view and a cross-sectional view schematically showing the structure of a driving TFT in a pixel area according to a third embodiment of the present invention, respectively.

[0113] Detailed description of components similar to those of the first and second embodiments may be omitted.

[0114] Reference Figure 7 and Figure 8 The driving TFT DTr of this embodiment may include an electrode pattern 60 which is located on the second sub driving TFT DTr2 and corresponds to and overlaps with the second channel portion CH2 of the second sub driving TFT DTr2.

[0115] For example, the first passivation layer 51 may be formed on the second semiconductor layer 22 , and the electrode pattern 60 may be formed on the first passivation layer 51 .

[0116] A second passivation layer 52 may be formed on the electrode pattern 60 , and a drain electrode 71 and a source electrode 73 may be formed on the second passivation layer 52 .

[0117] The electrode pattern 60 may be disposed to correspond to and overlap the second channel portion CH2 , and may be used as a doping mask in a doping process for the second source portion S2 and the second drain portion D2 of the second semiconductor layer 22 .

[0118] The electrode pattern 60 may serve to block light traveling from the outside toward the second channel portion CH2 over the electrode pattern 60. In addition, the electrode pattern 60 may overlap at least a portion of the first channel portion CH1.

[0119] The electrode pattern 60 may function as a back gate. For example, the electrode pattern 60 may receive a separate bias voltage from a power supply circuit, or may be electrically connected to the gate 45. Alternatively, the electrode pattern 60 may be electrically connected to the source 73. Alternatively, the electrode pattern 60 may be electrically connected to the drain 71, so that the electrode pattern 60 functions as a storage capacitor ( Figure 2 An electrode Cst) of the storage electrode (ie, the storage electrode facing the gate 45).

[0120] Fig. 9 is a plan view schematically showing the structure of a driving TFT in a pixel region according to a fourth embodiment of the present invention.

[0121] Detailed description of components similar to those of the first to third embodiments may be omitted.

[0122] Reference Fig. 9 In the driving TFT DTr of this embodiment, one of the first and second sub driving TFTs DTr1 and DTr2 may have a meander structure, and the other of the first and second sub driving TFTs DTr1 and DTr2 may have a non-meander structure, ie, a linear structure.

[0123] For the purpose of explanation, it is assumed that the first sub driving TFT DTr1 has a meander structure, and the second sub driving TFT DTr2 has a linear structure.

[0124] In this case, the second semiconductor layer 22 of the second sub driving TFT DTr2 may include a third component extending in the first direction as the x-direction and overlapping the first semiconductor layer 21 , and a fourth component continuously extending (or further extending) from the third component in the first direction.

[0125] Thus, the second channel portion CH2 of the second semiconductor layer 22 may be formed to have a linear structure. In this regard, the second channel portion CH2 may include a third channel component CH2a extending in the first direction as the x-direction and overlapping the first channel component CH1, and a fourth channel component CH2b extending from the third channel component CH2a in the first direction.

[0126] The third channel feature CH2a of the second channel portion CH2 may extend in the first direction which is the same direction as the first channel feature CH1a of the first channel portion CH1 and may overlap the first channel feature CH1a by the same length. Therefore, the third channel feature CH2a may have substantially the same channel length as the first channel feature CH1a.

[0127] The fourth channel part CH2b of the second channel portion CH2 continues to extend in the first direction different from the extending direction of the second channel part CH1b of the first channel portion CH1, and has a fourth channel length L4.

[0128] Therefore, the second channel portion CH2 may have a channel length in the first direction, L3+L4=L1+L4.

[0129] The first semiconductor layer 21 and the first channel portion CH1 thereof may have a bent structure in a plan view, and the second semiconductor layer 22 and the second channel portion CH2 thereof may have a linear structure in a plan view.

[0130] The bent and linear mixed structure of the fourth embodiment and the bent structure of the first embodiment may be appropriately selected according to the arrangement of elements of the pixel region P and the like.

[0131] Even in the case of the meander and line type mixed structure of the fourth embodiment, the channel length relative to the occupied area is increased. Therefore, the channel length of the driving TFT DTr that realizes the required driving characteristics with the minimum area can be ensured, and the area availability of the pixel region P can be improved.

[0132] Also, similar to the first embodiment, the first channel portion CH1 and the second channel portion CH2 may have channel parts extending in different directions (i.e., the second channel part CH1b and the fourth channel part CH2b), respectively, and the channel length of the first channel portion CH1 and the channel length of the second channel portion CH2 may be adjusted separately. Thus, various driving characteristics required of the first sub driving TFT DTr1 and the second sub driving TFT DTr2, respectively, may be satisfied, and thus the driving TFT DTr suitable for the required characteristics may be effectively provided.

[0133] According to the above-described embodiment, the driving TFT is configured to have a vertical double-layer stack structure with a shared gate, and at least one channel portion of the driving TFT has a bent structure.

[0134] Therefore, the channel length of the driving TFT relative to the occupied area can be increased. Therefore, the channel length of the driving TFT DTr that realizes the required driving characteristics with the minimum area can be ensured, and stable driving characteristics can be realized. In addition, the area availability of the pixel area can be improved.

[0135] In addition, the two vertically stacked channel portions have corresponding channel components extending in different directions, and their channel lengths can be adjusted separately. Thus, various driving characteristics required by the two sub-driving TFTs can be satisfied, and thus a driving TFT suitable for the required characteristics can be effectively provided.

[0136] It is obvious to those skilled in the art that various modifications and changes can be made in the present invention without departing from the spirit or scope of the present invention. Therefore, the present invention is intended to cover modifications and changes of the present invention that fall within the scope of the appended claims and their equivalents.

[0137] CROSS-REFERENCE TO RELATED APPLICATIONS

[0138] This application claims the benefit of priority to Korean Patent Application No. 10-2018-0109344 filed in Korea on September 13, 2018, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein.

Claims

1. A TFT substrate, comprising: A TFT is located on the substrate and includes a gate, a first semiconductor layer and a second semiconductor layer, The first semiconductor layer and the second semiconductor layer are vertically stacked, the gate is located between the first semiconductor layer and the second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are made of polysilicon. wherein the first semiconductor layer and the second semiconductor layer are electrically connected to each other in series and respectively include a first channel portion and a second channel portion, wherein at least one of the first channel portion and the second channel portion has a curved structure in a top view, wherein the first channel portion includes a first channel component extending along a first direction, and a second channel component extending along a second direction different from the first direction, wherein the second channel portion includes a third channel component extending in the first direction and overlapping the first channel component, and a fourth channel component extending in a direction different from the second direction, wherein the first channel component and the third channel component have the same channel length, and Wherein, the second channel component and the fourth channel component have different channel lengths.

2. The TFT substrate according to claim 1, wherein: The fourth channel member extends in a third direction different from the first direction and the second direction.

3. The TFT substrate according to claim 1, wherein: The fourth channel feature further extends from the third channel feature along the first direction.

4. The TFT substrate according to claim 1, further comprising: a first gate insulating layer, wherein the first gate insulating layer is located between the first semiconductor layer and the gate; a second gate insulating layer, the second gate insulating layer being located between the second semiconductor layer and the gate and on the first gate insulating layer; a passivation layer, the passivation layer being located on the second semiconductor layer; as well as a connecting electrode, the connecting electrode being located on the passivation layer, The connecting electrode contacts one of the source and drain portions of the second semiconductor layer and the other of the source and drain portions of the first semiconductor layer through contact holes in the passivation layer, the first gate insulating layer and the second gate insulating layer.

5. The TFT substrate according to claim 4, wherein: The one of the source portion and the drain portion of the second semiconductor layer is in contact with the connection electrode at an inner surface surrounding the contact hole.

6. The TFT substrate according to claim 1, wherein: The first semiconductor layer and the second semiconductor layer include a first lightly doped drain portion and a second lightly doped drain portion, respectively, and the first lightly doped drain portion and the second lightly doped drain portion have the same length or different lengths.

7. The TFT substrate according to claim 1, further comprising an electrode pattern, the electrode pattern being located on and corresponding to the second channel portion of the second semiconductor layer, the second semiconductor layer being located on the first semiconductor layer, and in, The electrode pattern is connected to a source electrode, a drain electrode, or the gate electrode of the TFT, or is applied with a bias voltage from a power supply circuit.

8. The TFT substrate according to claim 1, wherein: A channel length of the fourth channel feature is greater than a channel length of the first channel feature and a channel length of the third channel feature.

9. A display device, comprising: The TFT substrate according to any one of claims 1 to 8; as well as A first electrode is connected to a source of the TFT.

10. The display device according to claim 9, further comprising: A light emitting diode comprises the first electrode.

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