Small-size vertical pixel structure and image sensor

Abstract

The invention discloses a small-size vertical pixel structure and an image sensor. The small-size vertical pixel structure is manufactured based on a P-type silicon substrate, a transmission gate TG is located above a PD region, the PD region adopts an L-type structure, and the PD region is composed of a PDN and a DPDN; the transmission gate TG and the PDN region are separated by a PDP layer; the PDP, the PDN and the DPDN under the transmission gate TG are all subjected to pre-gate ion implantation; the PD region is formed by injecting N-type ions with different concentrations for multiple times, and the PDP layer is formed by injecting P-type ions with different concentrations; extra N-type ion implantation DPDN-NU is carried out on the DPDN area, non-uniform doping is carried out on the DPDN area, and a transverse electric field is formed. An L-shaped PD structure is adopted, a transverse electric field is formed, and electron transfer is accelerated; pDP layer injection is added, and the problem of charge leakage of a PD area and an FD node in a vertical pixel structure is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of CMOS image sensors, and in particular to a small-size vertical pixel structure and an image sensor. Background Art

[0002] CMOS image sensors are widely used in digital electronics, military defense, aerospace and other fields due to their low cost and high integration, and have taken a leading position in the market. Pixels are the core part of CMOS image sensors. With the development of CMOS image sensors, higher resolution is required on a smaller chip area, and the reduction of pixel size is an inevitable trend of development.

[0003] The vertical pixel structure can effectively reduce the pixel size, but it also brings about problems such as reduced quantum efficiency and charge leakage between the photodiode (PD) and the floating-diffusion node (FD), which has a certain impact on the performance of CMOS image sensors. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings and defects of the prior art and provide a small-size vertical pixel structure of 1μm-2μm and an image sensor. The small-size vertical pixel structure effectively reduces the pixel size, adopts an "L-type" PD structure, forms a lateral electric field, and accelerates electron transfer; removes the low-energy PDN (PD region N-type ion) injection of the pixel structure in the current technology, adds a PDP layer (PD region P-type ion) injection, and suppresses the problem of charge leakage in the PD region and FD node in the vertical pixel structure.

[0005] One object of the present invention is to provide a small-size vertical pixel structure, which is manufactured based on a P-type silicon substrate, wherein a transmission gate TG and a reset gate RST are composed of polysilicon; an oxide layer is provided between the transmission gate TG and the reset gate RST composed of the silicon substrate and polysilicon; two adjacent pixels are isolated by shallow trench isolation STI, a P well and a back deep trench isolation BDTI; the transmission gate TG is located above a PD region, the PD region adopts an L-type structure, and the PD region is composed of a PDN and a DPDN; the transmission gate TG and the PDN region are separated by a PDP layer; the PDP, PDN and DPDN under the transmission gate TG are all pre-gate ion implanted; the PD region is formed by multiple implantations of N-type ions of different concentrations, and the PDP layer is formed by implantations of P-type ions of different concentrations; an additional N-type ion implantation DPDN-NU is performed in the DPDN region, and the DPDN region is non-uniformly doped to form a lateral electric field.

[0006] Among them, the N-type ion implantations from top to bottom in the PD region are PDN1, PDN2, PDN3, and DPDN.

[0007] The ion concentration of N-type ions implanted in the PD region from top to bottom satisfies: PDN1>PDN2>PDN3>DPDN.

[0008] The DPDN area is larger than the PDN area, and its N-type ion implantation range is the entire pixel area.

[0009] The PDP layer has the function of clamping the maximum potential of the PD and preventing the penetration between the PD and the FD.

[0010] The sum of the concentrations of the additional N-type ion implanted DPDN-NU in the DPDN region and the N-type ion implanted DPDN in the DPDN region is less than PDN3.

[0011] Among them, the PDP layer injection range is the area between the STI area and the FD node to isolate the dark current on the device surface and the STI dark current, promote the depletion of the PD area, form a PPD structure, and avoid charge leakage between PD and FD when the transmission gate TG is not turned on.

[0012] Among them, the two P-type ion implantations from top to bottom of the PDP layer are PDP1 and PDP2.

[0013] Among them, the ion concentration of the two P-type ion implantations from top to bottom of the PDP layer meets the requirements of PDP1 <PDP2。

[0014] Another object of the present invention is to provide an image sensor comprising the small-size vertical pixel structure.

[0015] The pixel of the present invention adopts a vertical pixel structure, which effectively reduces the size of the pixel and enables the CMOS image sensor to achieve a higher resolution.

[0016] The pixel of the present invention adopts an "L-type" PD structure, and forms a lateral electric field by non-uniformly doping DPDN (deep PDN injection) to accelerate the transfer of electrons at the end of the "L-type" PD to the PD area.

[0017] The pixel of the present invention eliminates the low-energy PDN injection of the traditional pixel structure, injects P-type impurities in the corresponding area, effectively isolates the PD and FD areas, and suppresses the charge leakage problem of the PD and FD areas in the vertical pixel structure when the transfer gate TG is closed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of a small-size vertical pixel structure of the present invention.

[0019] Figure 2 It is a schematic diagram of the charge transfer path of the small-size vertical pixel structure of the present invention.

[0020] Figure 3 It is a control timing diagram of the small-size vertical pixel structure of the present invention. DETAILED DESCRIPTION

[0021] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0022] Figure 1 A schematic diagram of a small-size vertical pixel structure of the present invention is given.

[0023] See also Figure 1 As shown, the vertical structure pixel structure proposed in the present invention is based on a P-type silicon substrate (P-Sub), the transmission gate TG and the reset gate RST (Reset gate) are composed of polysilicon, an oxide layer is between the silicon substrate and the polysilicon, and adjacent pixels are isolated by shallow trench isolation (STI), P-well (P-Well), back-side deep trench isolation (BDTI) and other technologies.

[0024] Among them, the transmission gate TG is located above the PD area; the TG and PDN areas are separated by the PDP layer, which has the function of clamping the maximum potential of the PD and preventing punch-through between the PD and the FD; the PD area is composed of two parts, PDN and DPDN; the PDP, PDN and DPDN under the transmission gate TG are all pre-gate ion implanted.

[0025] Due to the small pixel size, multiple N-type ion implantations are used in the PD area, which can increase the depth of the depletion region while forming an electric potential gradient inside the PD that facilitates the flow of electrons from the PD to the channel under the gate, thereby promoting the movement of charges at the bottom of the PD to the top.

[0026] The N-type ion implantation in the PD region includes PDN1, PDN2, PDN3, and DPDN, and the ion concentrations thereof have the following relationship: PDN1>PDN2>PDN3>DPDN.

[0027] like Figure 1 As shown, the PD region of the pixel of the present invention adopts an L-shaped structure, which can improve the quantum efficiency of the pixel when back-illuminated. Among them, the DPDN region is larger than the PDN region, and the injection range is the entire pixel area. Due to the large ion injection range, the DPDN regions of adjacent pixels are likely to be connected together and affect the pixel performance. Therefore, the BDTI technology is used at the bottom of the PD to isolate it.

[0028] In some embodiments, the pixel of the present invention performs an additional N-type ion implantation (DPDNNon-uniformity, DPDN-NU) on the DPDN area to perform non-uniform doping on the DPDN area to form a lateral electric field, thereby accelerating the transfer of electrons from the end of the L-type PD to the inside of the PD.

[0029] Among them, in the embodiment of the present application, in order to ensure the longitudinal transfer of charges, the sum of the ion concentrations injected into DPDN-NU and DPDN should be less than PDN3.

[0030] In the embodiment of the present application, the injection range of the PDP layer is the area between the STI area and the FD (Floating-diffusion Node) node, which can effectively isolate the dark current on the device surface and the STI dark current, promote the depletion of the PD area, form a PPD structure, and effectively avoid the problem of charge leakage between PD and FD when the transmission gate TG is not turned on.

[0031] In the embodiment of the present application, the PDP uses two P-type ion implantations: PDP1 and PDP2, and the ion concentrations have the following relationship: PDP1 <PDP2。

[0032] Figure 2 It is a schematic diagram of the charge transfer path of the small-size vertical pixel structure of the present invention.

[0033] like Figure 2 As shown in the figure, when the transmission gate TG is closed, due to the higher ion concentration in the PDP2 region, a potential barrier is formed between the channel and PD, which blocks the electrons in the PD from flowing to the FD during exposure; after the charge transfer is completed, the channel electrons are blocked from flowing back to the PD. When the transmission gate TG is turned on, the concentration difference between PDP1 and PDP2 forms a potential gradient that facilitates the transfer of charges through the channel under the TG gate to the FD.

[0034] Figure 3 The control timing diagram of the pixel of the present invention is given, which is similar to the control principle of the traditional four-tube pixel. Figure 3 As shown, in the reset phase, the reset gate RST and the transmission gate TG are turned on to reset the PD region. Thereafter, the reset gate RST and the transmission gate TG are turned off to start exposure integration.

[0035] In the later stage of exposure, the readout stage begins, the row select gate SEL (Select) is turned on, and the source follower SF (Source follower) starts working; in the readout stage, the reset gate RST is turned on first to reset the FD node. After RST is turned off, the reset voltage is sampled; after the first sampling, the transmission gate TG is turned on, and its turn-on voltage is lower than the FD reset voltage, ensuring that the charge can flow smoothly to the FD node. At this time, the signal voltage is sampled.

[0036] The pixel of the embodiment of the present invention adopts a vertical pixel structure, which effectively reduces the size of the pixel and enables the CMOS image sensor to achieve a higher resolution.

[0037] The pixel of the embodiment of the present invention adopts an "L-type" PD structure, and forms a lateral electric field by non-uniformly doping DPDN (deep PDN injection) to accelerate the transfer of electrons at the end of the "L-type" PD to the PD area.

[0038] The pixel of the embodiment of the present invention eliminates the low-energy PDN injection of the traditional pixel structure, injects P-type impurities in the corresponding area, effectively isolates the PD and FD areas, and suppresses the charge leakage problem of the PD area and the FD area in the vertical pixel structure when the transfer gate TG (Transfergate) is closed.

[0039] Another object of an embodiment of the present invention is to provide an image sensor including the small-size vertical pixel structure.

[0040] The basic principles and main features of the present invention and the advantages of the present invention are shown and described above. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0041] Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is therefore intended that all changes falling within the meaning and range of equivalent elements of the claims are included in the present invention.

[0042] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. Small size vertical pixel structure, characterized in that: The transmission gate TG and reset gate RST are made of polysilicon based on a P-type silicon substrate. An oxide layer is formed between the transmission gate TG and reset gate RST formed of silicon substrate and polysilicon. Two adjacent pixels are isolated by shallow trench isolation STI, P well and back deep trench isolation BDTI. The transmission gate TG is located above the PD region, which adopts an L-shaped structure and consists of PDN and DPDN. The transmission gate TG and PDN regions are separated by a PDP layer. PDP, PDN and DPDN under the transmission gate TG are all pre-gate ion implanted. The PD region is formed by multiple implantations of N-type ions of different concentrations, and the PDP layer is formed by implantations of P-type ions of different concentrations. An additional N-type ion implantation DPDN-NU is performed in the DPDN region, and the DPDN region is non-uniformly doped to form a lateral electric field.

2. The small-size vertical pixel structure according to claim 1, characterized in that: The N-type ion implantation from top to bottom in the PD region is PDN1, PDN2, PDN3, and DPDN.

3. The small-size vertical pixel structure according to claim 2, characterized in that: The ion concentration of N-type ions implanted in the PD region from top to bottom satisfies: PDN1>PDN2>PDN3>DPDN.

4. The small-size vertical pixel structure according to claim 1, characterized in that: The DPDN area is larger than the PDN area, and its N-type ion implantation range is the entire pixel area.

5. The small-size vertical pixel structure according to claim 1, characterized in that: The PDP layer has the function of clamping the maximum potential of the PD and preventing punch-through between the PD and the FD.

6. The small-size vertical pixel structure according to claim 1, characterized in that: The sum of the additional N-type ion implantation DPDN-NU in the DPDN region and the N-type ion implantation DPDN in the DPDN region is less than PDN3.

7. The small-size vertical pixel structure according to claim 1, characterized in that: The PDP layer injection range is the area between the STI area and the FD node to isolate the device surface dark current and the STI dark current, promote the depletion of the PD area, form a PPD structure, and avoid charge leakage between the PD and FD when the transmission gate TG is not turned on.

8. The small-size vertical pixel structure according to claim 1, characterized in that: The PDP layer is implanted with P-type ions twice from top to bottom, namely PDP1 and PDP2.

9. The small-size vertical pixel structure according to claim 8, characterized in that: The ion concentration of the two P-type ion implantations from top to bottom of the PDP layer meets the requirements of PDP1 <PDP2。 10. An image sensor, characterized in that The invention comprises the small-size vertical pixel structure as described in any one of claims 1 to 9.

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