LED chip and manufacturing method thereof

Abstract

This application provides an LED chip and a method for manufacturing the same. The LED chip includes: a substrate; a first type semiconductor layer, an active layer, a second type semiconductor layer, a first passivation layer, a reflective layer, and a second passivation layer sequentially disposed on one side surface of the substrate along a first direction; the first direction is perpendicular to the substrate and points from the substrate to the active layer; the reflective layer has a plurality of arrayed grooves on the side near the first passivation layer, the opening of each groove facing the first passivation layer, and the groove wall of each groove is curved to shape and concentrate the light entering the groove and reflect it to the light-emitting surface; a first electrode electrically connected to the first type semiconductor layer; and a second electrode electrically connected to the second type semiconductor layer. This LED chip can reduce the incident angle of light on the light-emitting surface of the LED chip, thereby reducing the probability of total internal reflection and improving light extraction efficiency.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and more specifically, to an LED chip and its manufacturing method. Background Technology

[0002] Currently, light-emitting diodes (LEDs) based on the third-generation semiconductor material GaN are widely used in communications, lighting, and displays due to their advantages such as high efficiency, high brightness, long lifespan, and small size. However, because GaN has a relatively high refractive index (approximately 2.29), its critical angle for total internal reflection is small, which limits the light extraction efficiency (LEE) of LED chips and thus affects chip performance. Furthermore, as LED chip sizes continue to shrink, edge effects on the chip cross-section are increasing, further amplifying LEE losses. Therefore, improving LEE through LED chip structure design is crucial for enhancing chip performance.

[0003] Current LED chips often use PSS substrates (patterned substrates) to change the incident angle of light at the interface, thereby improving light extraction efficiency. However, on the one hand, PSS substrates themselves have high transmittance, and the proportion of scattered light is limited. On the other hand, the effect of this scattering structure is bidirectional, causing light that could have been output to be totally internally reflected at the material interface due to the change in the light path, further canceling out some of the light emission efficiency (LEE).

[0004] This case arose to overcome the limitation of light extraction efficiency in existing technologies. Summary of the Invention

[0005] In view of this, the present invention provides an LED chip that can improve light extraction efficiency and a method for manufacturing the same.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: An LED chip includes:

[0007] Substrate;

[0008] A first type semiconductor layer, an active layer, a second type semiconductor layer, a first passivation layer, a reflective layer, and a second passivation layer are sequentially arranged on one side surface of the substrate along a first direction; the first direction is perpendicular to the substrate and points from the substrate to the active layer; the reflective layer has a plurality of arrayed grooves on the side near the first passivation layer, the opening of each groove faces the first passivation layer, and the groove wall of each groove is curved to shape and concentrate the light entering the groove and reflect it to the light-emitting surface;

[0009] A first electrode electrically connected to the first type of semiconductor layer;

[0010] The second electrode is electrically connected to the second type of semiconductor layer.

[0011] Furthermore, the surface of the first passivation layer opposite to the active layer is provided with a plurality of arrayed first protrusions, each of the first protrusions protruding along the first direction;

[0012] The reflective layer contacts each of the first protrusions of the first passivation layer to form the groove.

[0013] Furthermore, the groove wall is a parabolic surface.

[0014] Furthermore, the surface of the first protrusion is formed by rotating a first line segment about its axis of symmetry;

[0015] The first line segment is selected from the line segment of the parabola including the vertex, and the axis of symmetry coincides with the axis of symmetry of the parabola.

[0016] Furthermore, it also includes an intermediate layer located on the substrate away from the surface of the active layer; the refractive index of the intermediate layer is less than the refractive index of the substrate and greater than the refractive index of air;

[0017] The intermediate layer has a plurality of arrayed second protrusions on its surface away from the active layer; the second protrusions protrude in a direction away from the first direction; after the emitted light enters the intermediate layer, the second protrusions cause the reflection direction of the emitted light that meets the reflection condition to be biased toward the focal point of the groove wall in the reflective layer, so as to reduce the incident angle when the emitted light reaches the intermediate layer for the second time and thus be output.

[0018] Furthermore, the surface of the second protrusion is formed by rotating the second line segment around the first axis;

[0019] The second line segment is selected from the off-axis segment of the parabola located on one side of the axis of symmetry; the first axis intersects the endpoint of the second line segment near the axis of symmetry and is parallel to the axis of symmetry.

[0020] Furthermore, in a projection plane parallel to the first direction, the endpoints of the projection contour lines of two adjacent grooves coincide.

[0021] Furthermore, in the projection plane parallel to the first direction, the endpoints of the projection contour lines of two adjacent second protrusions coincide.

[0022] Furthermore, the reflective layer is a metal reflector or a dielectric reflector.

[0023] Furthermore, when the reflective layer is a metal reflector, it can be one or more of a gold mirror, a silver mirror, an aluminum mirror, and a molybdenum mirror; when the reflective layer is a dielectric reflector, it can be a distributed Bragg mirror or a photonic crystal structure with a wide bandgap.

[0024] This invention also provides a method for manufacturing an LED chip, comprising the following steps:

[0025] Provide a substrate;

[0026] A first type semiconductor layer, an active layer, a second type semiconductor layer, a first passivation layer, a reflective layer, and a second passivation layer are sequentially grown along a first direction on one side of the substrate. The first direction is perpendicular to the substrate and extends from the substrate to the active layer. A plurality of arrayed grooves are formed on the side of the reflective layer near the first passivation layer. The opening of each groove faces the first passivation layer, and the groove wall of each groove is curved to shape and concentrate the light entering the groove and reflect it to the light-emitting surface.

[0027] Fabricate a first electrode that is electrically connected to the first type of semiconductor layer;

[0028] A second electrode is fabricated that is electrically connected to the second type of semiconductor layer.

[0029] Furthermore, the groove wall is a parabolic surface.

[0030] Furthermore, it also includes fabricating an intermediate layer on the surface of the substrate opposite to the active layer; the refractive index of the intermediate layer is less than the refractive index of the substrate and greater than the refractive index of air;

[0031] The intermediate layer has a plurality of arrayed second protrusions on its surface away from the active layer; the second protrusions protrude in a direction away from the first direction; after the emitted light enters the intermediate layer, the second protrusions cause the reflection direction of the emitted light that meets the reflection condition to be biased toward the focal point of the groove wall in the reflective layer, so as to reduce the incident angle when the emitted light reaches the intermediate layer for the second time and thus be output.

[0032] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0033] 1. An LED chip includes: a substrate; a first type semiconductor layer, an active layer, a second type semiconductor layer, a first passivation layer, a reflective layer, and a second passivation layer sequentially disposed on one side surface of the substrate along a first direction; the first direction is perpendicular to the substrate and points from the substrate to the active layer; the reflective layer has a plurality of arrayed grooves on the side near the first passivation layer, the opening of each groove facing the first passivation layer, and the groove wall of each groove is curved to shape and concentrate the light entering the groove and reflect it to the light-emitting surface; a first electrode electrically connected to the first type semiconductor layer; and a second electrode electrically connected to the second type semiconductor layer. Due to the above structural configuration, the LED chip of this application forms grooves on the reflective layer, and the groove walls can shape and concentrate the light entering the groove and reflect it to the light-emitting surface, reducing the incident angle of light at the light-emitting surface of the LED chip, thereby reducing the probability of total internal reflection and improving light extraction efficiency. The second passivation layer serves as a protective layer for the LED chip, increasing the reliability of the chip.

[0034] 2. The principle of light reflection from a parabola is as follows: Figure 2 As shown, when a beam of parallel light is incident on a parabolic surface, the reflected light from different positions will eventually converge at the same point, called the focal point. According to the principle of the reversibility of light paths, when a point light source is located at the focal point of the parabolic surface, the diverging light emitted by the point light source will become parallel light after reflection. Based on the Huygens-Fresnel principle, we can decompose the active layer into individual surface elements and consider each surface element as a point light source. The light emitted by the point light source enters the grooves of the reflective layer and is shaped and converged by the parabolic groove walls, reducing the incident angle of the light on the light-emitting surface of the LED chip, thereby reducing the probability of total internal reflection and improving light extraction efficiency.

[0035] 3. An intermediate layer is provided, and several arrayed second protrusions are arranged on the intermediate layer to improve light extraction efficiency. Simultaneously, to avoid the patterned arrangement on the intermediate layer causing light that could have been output to be totally internally reflected at the material interface due to changes in the optical path, thus canceling out some of the light emission (LEE), the inventors of this application designed the second protrusions so that the reflection direction of the emitted light that meets the reflection conditions is deflected towards the focal point of the parabolic groove wall in the reflective layer. This reduces the incident angle when the emitted light reaches the intermediate layer a second time, allowing it to be output and reducing the canceled-out LEE. Furthermore, due to the significant difference in refractive index between the substrate and air, the refractive index of the intermediate layer is between that of the substrate and air, reducing light backflow into the LED chip. Combined with the above structural design, this reduces the number of light reflections, thereby reducing light loss within the chip and improving light extraction efficiency.

[0036] 4. In the projection plane parallel to the first direction, the endpoints of the projection contour lines of two adjacent grooves coincide, that is, each groove is continuous and there is no gap in the middle, so that as many grooves as possible are formed on the reflective layer, the light shaping and focusing effect is better, and the light extraction efficiency of the LED chip can be improved.

[0037] 5. In the projection plane parallel to the first direction, the endpoints of the projection contour lines of two adjacent second protrusions coincide, that is, each second protrusion is continuous without any gaps in the middle, so that as many second protrusions as possible are formed on the intermediate layer, which can better improve the light extraction efficiency of the LED chip. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the structure of an embodiment of the LED chip of this application;

[0040] Figure 2 This is a schematic diagram illustrating the principle of parabolic reflection.

[0041] Figure 3 This is a schematic diagram illustrating the selection of the first and second line segments;

[0042] Figure 4 The projection outline of the first protrusion on a projection plane parallel to the first direction;

[0043] Figure 5 This is a partial schematic diagram of the first protrusion array on the surface of the first passivation layer;

[0044] Figure 6 The projection outline of the second protrusion on a projection plane parallel to the first direction;

[0045] Figure 7 This is a partial schematic diagram of the second protrusion array on the surface of the intermediate layer;

[0046] Figure 8 This is a schematic diagram of another embodiment of the LED chip in this application;

[0047] Figure 9-17 for Figure 8 The diagram shows the steps involved in manufacturing an LED chip.

[0048] Figure label:

[0049] Substrate 1; Type I semiconductor layer 2; Active layer 3; Type II semiconductor layer 4; First passivation layer 5; First protrusion 51; Reflective layer 6; Second passivation layer 7; Intermediate layer 8; Second protrusion 81; Current spreading layer 9; First electrode 10; Second electrode 20; First contact electrode 30; Second contact electrode 40; Parabola 50; Axis of symmetry 501; First line segment 502; Second line segment 503; First axis 60; Insulating channel 80; First direction D. Detailed Implementation

[0050] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0051] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0052] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0053] like Figure 1 As shown, this application provides an LED chip, which includes a substrate 1, a first type semiconductor layer 2, an active layer 3, a second type semiconductor layer 4, a first passivation layer 5, a reflective layer 6, and a second passivation layer 7 sequentially disposed on one side surface of the substrate 1 along a first direction D; the first direction D is perpendicular to the substrate 1 and points from the substrate 1 to the active layer 3; a first electrode 10 electrically connected to the first type semiconductor layer 2 and a second electrode 20 electrically connected to the second type semiconductor layer 4. The reflective layer 6 has a plurality of arrayed grooves on the side near the first passivation layer 5, the opening of each groove facing the first passivation layer 5, and the groove wall of each groove is curved to shape and concentrate the light entering the groove and reflect it to the light-emitting surface.

[0054] Due to the aforementioned structural configuration, the LED chip of this application has a groove formed on the reflective layer 6. The groove wall can shape and concentrate the light entering the groove before reflecting it to the light-emitting surface, thereby reducing the incident angle of light on the light-emitting surface of the LED chip and improving light extraction efficiency. The second passivation layer 7 serves as a protective layer for the LED chip, increasing the reliability of the chip.

[0055] In this embodiment, one of the first type semiconductor layer 2 and the second type semiconductor layer 4 is a P-type semiconductor layer, and the other is an N-type semiconductor layer. This application uses the example of the first type semiconductor layer 2 being an N-type semiconductor layer and the second type semiconductor layer 4 being a P-type semiconductor layer for illustration. The first type semiconductor layer 2 can be N-GaN, and the second type semiconductor layer 4 can be P-GaN.

[0056] The material of the first passivation layer 5 is preferably a material with a refractive index similar to that of GaN (approximately 2.29), which can reduce the refractive index difference between the first passivation layer 5 and the GaN layer and improve light transmittance. The first passivation layer 5 includes, but is not limited to, silicon nitride. Preferably, the silicon nitride first passivation layer is prepared by PECVD. The refractive index of silicon nitride prepared by PECVD is in the range of 1.8-2.5. During the preparation of the first passivation layer 5, the refractive index of silicon nitride can be controlled within the range of 2-2.2 by adjusting the process parameters to make the refractive index more similar to that of GaN. For example, the refractive index of silicon nitride can be controlled by adjusting the gas molar ratio in the reaction chamber and the radio frequency power parameters.

[0057] Substrate 1 includes, but is not limited to, sapphire substrate 1, preferably flat sapphire substrate 1, which can improve the quality of epitaxial layer during epitaxial layer growth, reduce epitaxial layer growth defects and uneven growth, thereby improving device reliability.

[0058] Among them, such as Figure 1 As shown, the LED chip in this application has grooves for etching a second type semiconductor layer 4 and an active layer 3 to form a mesa and an exposed portion of the first type semiconductor layer 2; it also has insulating channels 80 for etching the second type semiconductor layer 4, the active layer 3, and the exposed portion of the first type semiconductor layer 2 onto the substrate 1, and the insulating channels 80 are used to separate the individual chips. A first passivation layer 5 covers the exposed surfaces of the second type semiconductor layer 4, the active layer 3, and the first type semiconductor layer 2 of each chip in the LED chip. A reflective layer 6 covers the exposed surface of the first passivation layer 5, and a second passivation layer 7 covers the exposed surface of the reflective layer 6.

[0059] In a preferred embodiment, the surface of the first passivation layer 5 facing away from the active layer 3 is provided with a plurality of arrayed first protrusions 51, each of the first protrusions 51 protruding along the first direction D; the reflective layer 6 contacts each of the first protrusions 51 of the first passivation layer 5 to form a groove. Figure 5 This is a partial schematic diagram of the array of first protrusions 51 on the surface of the first passivation layer 5.

[0060] In a preferred embodiment, the groove wall is a parabolic surface. The principle of light reflection from a parabolic surface is as follows: Figure 2 As shown, when a beam of parallel light is incident on a parabolic surface, the reflected light from different positions will eventually converge at the same point, called the focal point. According to the principle of the reversibility of light paths, when a point light source is located at the focal point of the parabolic surface, the divergent light emitted by the point light source will become parallel light after reflection. According to the Huygens-Fresnel principle, we can decompose the active layer 3 into individual surface elements and regard each surface element as a point light source. After the light emitted by the point light source enters the groove of the reflective layer 6, it is shaped and converged by the parabolic groove wall, reducing the incident angle of the light on the light-emitting surface of the LED chip, thereby reducing the probability of total internal reflection and improving the light extraction efficiency.

[0061] In a preferred embodiment, such as Figure 3 As shown, the surface of the first protrusion 51 is formed by rotating a first line segment 502 about its axis of symmetry; the first line segment 502 is selected from the line segment of the parabola 50 including its vertex, and the axis of symmetry coincides with the axis of symmetry 501 of the parabola 50. This application exemplarily illustrates that the first line segment is... Figure 3 The line segment selected by the dashed box in section 502. Figure 4 The projection outline of the first protrusion 51 on a projection plane parallel to the first direction D is shown, and its projection outline is also the first line segment 502. In this application, the surface of the first protrusion 51 is rotated about its axis of symmetry by the first line segment 502 to form a parabolic surface, so that the groove wall of the groove is parabolic.

[0062] Preferably, such as Figure 1 As shown, the width A at the bottom of each first protrusion 51 ranges from 1μm to 4μm, including the endpoint values.

[0063] In a preferred embodiment, such as Figure 1 As shown, the LED chip also includes an intermediate layer 8 located on the substrate 1 away from the surface of the active layer 3. The refractive index of the intermediate layer 8 is less than that of the substrate 1 and greater than that of air. The surface of the intermediate layer 8 away from the active layer 3 is provided with a plurality of arrayed second protrusions 81. The second protrusions 81 protrude in a direction away from the first direction D. After the emitted light enters the intermediate layer 8, the second protrusions 81 cause the reflection direction of the emitted light that meets the reflection condition to be deflected towards the focal point of the groove wall in the reflective layer 6, thereby reducing the incident angle when the emitted light reaches the intermediate layer 8 for the second time and thus enabling output. The material of the intermediate layer 8 can be one of silicon oxide, aluminum oxide, a mixture of silicon and aluminum oxides, barium fluoride, magnesium fluoride, etc., but is not limited to these, as long as the material meets the above requirements.

[0064] An intermediate layer 8 is provided, and several arrayed second protrusions 81 are arranged on the intermediate layer 8 to improve light extraction efficiency. Simultaneously, to prevent the patterned arrangement on the intermediate layer 8 from causing light that could have been output to be totally internally reflected at the material interface due to changes in the optical path, thus canceling out some of the light emission (LEE), the inventors of this application designed the second protrusions 81 so that the reflection direction of the emitted light that meets the reflection conditions is deflected towards the focal point of the parabolic groove wall of the groove in the reflective layer 6. This reduces the incident angle when the emitted light reaches the intermediate layer 8 a second time, allowing it to be output and reducing the canceled-out LEE. Furthermore, due to the significant difference in refractive index between the substrate 1 and air, the refractive index of the intermediate layer 8 is between that of the substrate 1 and air, reducing light backflow into the LED chip. Combined with the above structural design, this reduces the number of light reflections, thereby reducing light loss within the chip and improving light extraction efficiency.

[0065] Preferably, such as Figure 3 As shown, the surface of the second protrusion 81 is formed by rotating the second line segment 503 about the first axis 60; the second line segment 503 is selected from the off-axis segment of the parabola 50 located on one side of the axis of symmetry 501, that is, the selected second line segment 503 does not intersect the axis of symmetry 501 of the parabola 50. This application exemplarily illustrates that the second line segment is... Figure 3 The line segment selected by the dashed box in section 503. For example... Figure 6 The projection outline of the second protrusion 81 on a projection plane parallel to the first direction D is shown, as follows. Figure 6 The first axis 60 shown intersects with the endpoint of the second line segment 503 near the axis of symmetry 501 and is parallel to the axis of symmetry 501. The first line segment 502 and the second line segment 503 can be selected from the same parabola 50 or from different parabolas 50, as long as the above-mentioned requirements are met. This application uses the example of the first line segment 502 and the second line segment 503 being selected from the same parabola 50 for illustration.

[0066] Preferably, such as Figure 1 As shown, the width B at the bottom of the second protrusion 81 ranges from 1μm to 4μm, including the endpoint values.

[0067] In a preferred embodiment, such as Figure 1 As shown, in the projection plane parallel to the first direction D, the endpoints of the projection contour lines of two adjacent grooves coincide. That is, the grooves are continuous without gaps, allowing for the formation of as many grooves as possible on the reflective layer 6, resulting in better light shaping and focusing, and thus improving the light extraction efficiency of the LED chip. In other words, as... Figure 5 As shown, during manufacturing, continuous first protrusions 51 are set to make the grooves on the reflective layer continuous.

[0068] In a preferred embodiment, such as Figure 1 , 7As shown, in the projection plane parallel to the first direction D, the endpoints of the projection contours of two adjacent second protrusions 81 coincide. That is, each second protrusion 81 is continuous without any gaps in between, so that as many second protrusions 81 as possible are formed on the intermediate layer 8, which can better improve the light extraction efficiency of the LED chip.

[0069] In a preferred embodiment, the reflective layer 6 is a metal mirror or a dielectric mirror. Preferably, when the reflective layer 6 is a metal mirror, it can be one or more of a gold mirror, a silver mirror, an aluminum mirror, and a molybdenum mirror; when the reflective layer 6 is a dielectric mirror, it can be a distributed Bragg mirror or a photonic crystal structure with a wide bandgap.

[0070] In a preferred embodiment, such as Figure 8 As shown, the LED chip also includes a current spreading layer 9 located below the first passivation layer 5 and covering the second type semiconductor layer 4 away from the surface of the active layer 3. The current spreading layer 9 includes, but is not limited to, I0.

[0071] In a preferred embodiment, such as Figure 1 , 8 As shown, the LED chip also includes a first contact electrode 30 and a second contact electrode 40. The first contact electrode 30 is located on the surface of the first type semiconductor layer 2 opposite to the active layer 3; the second contact electrode 40 is located on the surface of the second type semiconductor layer 4 opposite to the active layer 3 or on the surface of the current spreading layer 9 opposite to the active layer 3. The first electrode 10 is connected to the first contact electrode 30 through a via penetrating the first passivation layer 5, the reflective layer 6, and the second passivation layer 7; the second electrode 20 is connected to the second contact electrode 40 through a via penetrating the first passivation layer 5, the reflective layer 6, and the second passivation layer 7. It should be understood that the illustrations in this application are based on the example of a distributed Bragg reflector as the reflective layer. In other embodiments, when the reflective layer is a metal reflector, the first electrode 10 and the second electrode 20 should be insulated from the reflective layer 6.

[0072] This application also provides a method for manufacturing an LED chip, such as... Figure 8 As shown in Figure 17, it includes the following steps:

[0073] S01: A substrate 1 is provided. The substrate 1 includes, but is not limited to, a sapphire substrate 1, preferably a flat sapphire substrate 1.

[0074] S02: A first type semiconductor layer 2, an active layer 3, a second type semiconductor layer 4, a first passivation layer 5, a reflective layer 6, and a second passivation layer 7 are sequentially grown along a first direction D on one side of the substrate 1; the first direction D is perpendicular to the substrate 1 and points from the substrate 1 to the active layer 3. A plurality of arrayed grooves are formed on the side of the reflective layer 6 near the first passivation layer 5, with the opening of each groove facing the first passivation layer 5, and the groove walls of each groove being curved to shape and concentrate the light entering the groove before reflecting it to the light-emitting surface.

[0075] Preferably, a plurality of arrayed first protrusions 51 are formed on the surface of the first passivation layer 5 away from the active layer 3, and each first protrusion 51 protrudes along the first direction D; the reflective layer 6 contacts each of the first protrusions 51 of the first passivation layer 5 to form a groove.

[0076] Preferably, the groove wall is parabolic.

[0077] Preferably, the reflective layer 6 is a metal mirror or a dielectric mirror. When the reflective layer 6 is a metal mirror, it can be one or more of a combination of a gold mirror, a silver mirror, an aluminum mirror, and a molybdenum mirror; when the reflective layer 6 is a dielectric mirror, it can be a distributed Bragg mirror or a photonic crystal structure with a wide bandgap.

[0078] Preferably, a current spreading layer 9 is provided below the first passivation layer 5, and the current spreading layer 9 covers the surface of the second type semiconductor layer 4 away from the active layer 3.

[0079] Alternatively, a first contact electrode 30 is provided on the first type semiconductor layer 2, and a second contact electrode 40 is provided on the current spreading layer 9.

[0080] S03: Fabricate a first electrode 10 that is electrically connected to the first type of semiconductor layer 2.

[0081] S04: Fabricate a second electrode 20 that is electrically connected to the second type semiconductor layer 4.

[0082] In a preferred embodiment, the method for manufacturing the LED chip further includes:

[0083] S05: An intermediate layer 8 is fabricated on the surface of the substrate 1 opposite to the active layer 3. The refractive index of the intermediate layer 8 is less than that of the substrate 1 and greater than that of air. The surface of the intermediate layer 8 opposite to the active layer 3 is provided with a plurality of arrayed second protrusions 81. The second protrusions 81 protrude in a direction opposite to the first direction D. After the emitted light enters the intermediate layer 8, the second protrusions 81 cause the reflection direction of the emitted light that meets the reflection condition to be deflected toward the focal point of the groove wall in the reflective layer 6, so as to reduce the incident angle when the emitted light reaches the intermediate layer 8 for the second time and thus output the light.

[0084] Taking an LED chip that also includes a current spreading layer 9, a first contact electrode 30, and a second contact electrode 40 as an example, step S02 specifically includes:

[0085] S021: As Figure 9 As shown, a first-type semiconductor layer 2, an active layer 3, and a second-type semiconductor layer 4 are grown on a substrate 1.

[0086] S022: Photoresist is spin-coated onto the surface of the second type semiconductor layer 4. After exposure and development, a MESA pattern is prepared. Then, inductively coupled plasma etching (ICP) is used to etch the areas of the epitaxial layer surface not covered by photoresist, exposing the first type semiconductor layer 2. The etching depth is 5000-25000 angstroms. The etching gases used are chlorine (Cl2), boron trichloride (BCl3), and argon (Ar). After etching, the remaining photoresist is removed. Figure 10 As shown, a trench is etched to expose the first type semiconductor layer 2.

[0087] S023: As Figure 11 As shown, a layer of photoresist is spin-coated onto the exposed surface of the epitaxial layer. After exposure and development, dry etching is performed using an ICP machine until the substrate 1 is exposed, forming an insulating channel 80 (ISO) to separate the individual chips. The etching depth is 40,000-60,000 angstroms, including the endpoint values. Chlorine (Cl2), boron trichloride (BCl3), and argon (Ar) are selected as the etching gases. After etching, the remaining photoresist is removed.

[0088] S024: As Figure 12 As shown, a current spreading layer material is sputtered onto the surface of the second type semiconductor layer 4 using plasma magnetron sputtering; then, photoresist is spin-coated, and after exposure and development, a current spreading layer 9 pattern is prepared; excess current spreading layer material is removed by wet etching with an etchant to complete the preparation of the current spreading layer 9, and excess photoresist is removed after preparation. The current spreading layer 9 includes, but is not limited to, ITO.

[0089] S025: As Figure 13 As shown, a layer of photoresist is prepared by spin coating, and the patterns of the first contact electrode 30 and the second contact electrode 40 are prepared by exposure and development. The first contact electrode 30 and the second contact electrode 40 are deposited by electron beam evaporation. The deposited material will uniformly cover the entire surface. The excess deposited material is removed by electrostatic film peeling, leaving only the first contact electrode 30 and the second contact electrode 40. Then, a photoresist removal process is performed to remove the residual photoresist.

[0090] S026: As Figure 14As shown, a first passivation layer 5 with a thickness of 10,000-14,000 angstroms, including endpoint values, is prepared using enhanced plasma chemical vapor deposition (PECVD). The first passivation layer 5 can be silicon nitride, and the refractive index of silicon nitride is controlled between 2 and 2.2 by adjusting the gas molar ratio in the reaction chamber and the RF power parameters. Next, a photoresist layer is prepared by spin coating and partially removed by soft baking to form a shaped photoresist layer. Then, a hard template (silicon or sapphire) for fabricating the first protrusion array 51 is used to transfer the morphology on the template to the photoresist using nanoimprint lithography, and the photoresist is cured by baking. Finally, the photoresist morphology is transferred to the first passivation layer 5 by ICP dry etching, forming an array of first protrusions 51 on it. The etching gases selected are carbon tetrafluoride (CF4), trifluoromethane (CHF3), argon (Ar), and oxygen (O2). High vertical etching selectivity is achieved by adjusting the ratio of CHF3 and Ar gases, and a suitable etching selectivity ratio is achieved by adjusting the ratio of O2, so that the photoresist morphology can be completely transferred to the first passivation layer 5.

[0091] Preferably, such as Figure 3 , 4 As shown in Figure 5, the surface of the first protrusion 51 is formed by rotating the first line segment 502 about its axis of symmetry; the first line segment 502 is selected from the line segment of the parabola 50 including the vertex, and the axis of symmetry coincides with the axis of symmetry 501 of the parabola 50.

[0092] S027: As Figure 15 As shown, a reflective layer 6 is deposited on the first passivation layer 5 using reactive plasma deposition (RPT) or electron beam thermal evaporation. Taking a distributed Bragg reflector as an example, the reflective layer 6 is formed by alternating layers of high-refractive-index Ti3O5 and low-refractive-index SiO2, each layer approximately 1000 angstroms thick, with 39 alternating layers deposited to form the distributed Bragg reflector. Finally, a curved reflective surface with grooves is formed on the surface of the reflective layer 6 facing the active layer 3. Similarly, metal reflectors such as gold, silver, and aluminum reflectors can be prepared using thermal evaporation. Subsequently, a second passivation layer with a thickness of 3000-3500 angstroms, including the endpoint values, is deposited using PECVD as a core protection layer to increase core reliability. The number of alternating layers and the thickness of each layer in the distributed Bragg reflector are merely illustrative descriptions and can be adjusted according to actual needs.

[0093] Preferably, in a projection plane parallel to the first direction D, the endpoints of the projection contours of two adjacent grooves coincide.

[0094] Step S03 specifically involves etching the first passivation layer 5, the reflective layer 6, and the second passivation layer 7 to create a through hole exposing the first contact electrode 30, and then creating the first electrode 10 within the through hole.

[0095] Step S04 specifically involves etching the first passivation layer 5, the reflective layer 6, and the second passivation layer 7 to create a through hole exposing the second contact electrode 40, and then fabricating the second electrode 20 within the through hole.

[0096] Among them, such as Figure 16 , 17 As shown, steps S03 and S04 can also be performed simultaneously. Specifically, a layer of photoresist is spin-coated onto the surface of the second passivation layer 7, and after exposure and development, a through-hole pattern is prepared. Dry etching is performed on the first passivation layer 5, the reflective layer 6, and the second passivation layer 7 using ICP to etch through-holes exposing the first contact electrode 30 and the second contact electrode 40, respectively. The photoresist is then removed using a photoresist stripping process. Afterward, photoresist is spin-coated onto the surface again, and the first electrode 10 and the second electrode 20 are patterned after exposure and development. A metal layer is then prepared by electron beam evaporation, and excess metal is removed using a stripping method to form the first electrode 10 and the second electrode 20.

[0097] Step S05 specifically includes: thinning and smoothing the side of substrate 1 away from the active layer 3 through grinding and polishing processes. Then, an intermediate layer material is deposited on the surface of substrate 1 away from the active layer 3, followed by spin-coating of a photoresist layer. The second bump 81 array pattern is then prepared by exposure and development. Finally, each second bump 81 is prepared using ICP dry etching, forming a pattern as shown... Figure 8 The intermediate layer 8 is shown. The etching gases used are carbon tetrafluoride (CF4), trifluoromethane (CHF3), and argon (Ar). Residual photoresist is then removed via a photoresist stripping process.

[0098] Preferably, the surface of the second protrusion 81 is formed by rotating the second line segment 503 around the first axis 60; the second line segment 503 is selected from the off-axis segment of the parabola 50 located on one side of the axis of symmetry 501; the first axis 60 intersects the endpoint of the second line segment 503 near the axis of symmetry 501 and is parallel to the axis of symmetry 501.

[0099] Preferably, in a projection plane parallel to the first direction D, the endpoints of the projection contour lines of two adjacent second protrusions 81 coincide.

[0100] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0101] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0102] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED chip, characterized in that, include: Substrate; A first type semiconductor layer, an active layer, a second type semiconductor layer, a first passivation layer, a reflective layer, and a second passivation layer are disposed on one side surface of the substrate and arranged sequentially along a first direction; the first direction is perpendicular to the substrate and points from the substrate to the active layer; The reflective layer has a plurality of arrayed grooves on the side near the first passivation layer. The opening of each groove faces the first passivation layer, and the groove wall of each groove is curved to shape and concentrate the light entering the groove and reflect it to the light-emitting surface. An intermediate layer located on the substrate away from the surface of the active layer; The refractive index of the intermediate layer is less than that of the substrate, but greater than that of air; The intermediate layer has a plurality of arrayed second protrusions on its surface opposite to the active layer; The second protrusion protrudes in a direction away from the first direction; after the emitted light enters the intermediate layer, the second protrusion causes the reflection direction of the emitted light that meets the reflection condition to be biased toward the focal point of the groove wall in the reflective layer, so as to reduce the incident angle when the emitted light reaches the intermediate layer for the second time and thus output it. A first electrode electrically connected to the first type of semiconductor layer; The second electrode is electrically connected to the second type of semiconductor layer.

2. The LED chip as described in claim 1, characterized in that, The surface of the first passivation layer opposite to the active layer is provided with a plurality of arrayed first protrusions, each of which protrudes along the first direction. The reflective layer contacts each of the first protrusions of the first passivation layer to form the groove.

3. The LED chip as described in claim 1, characterized in that, The groove wall is parabolic.

4. An LED chip as described in claim 2, characterized in that, The surface of the first protrusion is formed by rotating a first line segment about its axis of symmetry. The first line segment is selected from the line segment of the parabola including the vertex, and the axis of symmetry coincides with the axis of symmetry of the parabola.

5. An LED chip as described in claim 1, characterized in that, The surface of the second protrusion is formed by rotating the second line segment around the first axis; The second line segment is selected from the off-axis segment of the parabola located on one side of the axis of symmetry; the first axis intersects the endpoint of the second line segment near the axis of symmetry and is parallel to the axis of symmetry.

6. An LED chip as described in claim 1, characterized in that, In a projection plane parallel to the first direction, the endpoints of the projection contour lines of two adjacent grooves coincide.

7. An LED chip as described in claim 1, characterized in that, In a projection plane parallel to the first direction, the endpoints of the projection contour lines of two adjacent second protrusions coincide.

8. An LED chip as described in claim 1, characterized in that, The reflective layer is a metal reflector or a dielectric reflector.

9. An LED chip as described in claim 8, characterized in that, When the reflective layer is a metal reflector, it can be one or a combination of gold, silver, aluminum, and molybdenum mirrors; when the reflective layer is a dielectric reflector, it can be a distributed Bragg reflector or a photonic crystal structure with a wide bandgap.

10. A method for manufacturing an LED chip, characterized in that, Includes the following steps: Provide a substrate; A first type semiconductor layer, an active layer, a second type semiconductor layer, a first passivation layer, a reflective layer, and a second passivation layer are sequentially grown along a first direction on one side of the substrate; the first direction is perpendicular to the substrate and points from the substrate to the active layer; a plurality of arrayed grooves are formed on the side of the reflective layer near the first passivation layer, the opening of each groove faces the first passivation layer, and the groove wall of each groove is curved, so as to shape and concentrate the light entering the groove and reflect it to the light-emitting surface; An intermediate layer is fabricated on the substrate away from the surface of the active layer; the refractive index of the intermediate layer is less than that of the substrate and greater than that of air; The intermediate layer has a plurality of arrayed second protrusions on its surface opposite to the active layer; The second protrusion protrudes in a direction away from the first direction; after the emitted light enters the intermediate layer, the second protrusion causes the reflection direction of the emitted light that meets the reflection condition to be biased toward the focal point of the groove wall in the reflective layer, so as to reduce the incident angle when the emitted light reaches the intermediate layer for the second time and thus output it. Fabricate a first electrode that is electrically connected to the first type of semiconductor layer; A second electrode is fabricated that is electrically connected to the second type of semiconductor layer.

11. The method for manufacturing an LED chip as described in claim 10, characterized in that, The groove wall is parabolic.

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