Tantalum doped ruthenium layers for interconnects

Abstract

Methods of forming interconnects and electronic devices are described. A method of forming an interconnect includes forming a tantalum nitride layer on a substrate; forming a ruthenium layer on the tantalum nitride layer; and exposing the tantalum nitride layer and the ruthenium layer to a plasma comprising a mixture of hydrogen (H2) and argon (Ar) to form a tantalum-doped ruthenium layer thereon. An apparatus for performing the method is also described.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to methods of forming barrier layers. In particular, embodiments of the present disclosure relate to methods of forming tantalum-doped ruthenium layers for interconnects. Background Art

[0002] The miniaturization of semiconductor circuit elements has reached the point where feature sizes of 20 nm or less are being manufactured on a commercial scale. As critical dimensions continue to decrease, new challenges arise for process steps such as filling the gaps between circuit elements. As the width between elements continues to shrink, the gaps between them typically become taller and narrower, making the gaps more difficult to fill and making contacts more difficult to make robust.

[0003] Ruthenium-doped tantalum nitride is being investigated as a copper barrier material for smaller node applications. However, integrating ruthenium-doped tantalum nitride into small features can result in copper / ruthenium corrosion (due to, for example, electromigration of copper in close proximity to the ruthenium), thereby destroying the connection.

[0004] Ruthenium (Ru) doped tantalum nitride (TaN) typically contains a high concentration of carbon (C) and is not effectively or easily removed by in-situ H2 / Ar plasma during atomic layer deposition (ALD) tantalum nitride formation. Studies on tantalum doped ruthenium layers have shown that the copper (Cu) diffusion activation energy is greater than that of the ruthenium doped tantalum layer.

[0005] Accordingly, there is a need for methods of forming tantalum-doped ruthenium layers for interconnects. Summary of the invention

[0006] One or more embodiments of the present disclosure are directed to a method of forming an interconnect. The method includes forming a tantalum nitride layer on a substrate; forming a ruthenium layer on the tantalum nitride layer; and exposing the tantalum nitride layer and the ruthenium layer to a plasma containing a mixture of hydrogen (H2) and argon (Ar) to form a tantalum-doped ruthenium layer thereon.

[0007] Additional embodiments of the present disclosure relate to other methods of forming interconnects. In some embodiments, the method of forming an interconnect comprises forming at least one conformal tantalum nitride layer and at least one ruthenium layer on a substrate having a surface having a structure formed in the surface. The structure extends a certain distance into the substrate and has sidewalls and a bottom. The bottom comprises a conductive material and the sidewalls comprise a low-k dielectric material, the low-k dielectric material comprising one or more of fluorine-doped silicon oxide, organosilicate glass, or porous silicon dioxide. At least one ruthenium layer is formed on at least one conformal tantalum nitride layer. In some embodiments, the method of forming an interconnect further comprises exposing the conformal tantalum nitride layer and the ruthenium layer to a plasma comprising a mixture of hydrogen (H2) and argon (Ar) to form a tantalum-doped ruthenium layer, the tantalum-doped ruthenium layer comprising greater than or equal to 80 at.% ruthenium.

[0008] Additional embodiments of the present disclosure relate to electronic devices. The electronic devices described herein include a substrate having a surface having a structure formed in the surface. The structure extends a certain distance into the substrate and has sidewalls and a bottom. The bottom comprises a conductive material and the sidewalls comprise a dielectric material. The electronic device further comprises a tantalum-doped ruthenium layer in the structure. The tantalum-doped ruthenium layer comprises greater than or equal to 80 at. % ruthenium. The electronic device further comprises a metal fill in the structure on the tantalum-doped ruthenium layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Therefore, in order that the manner in which the above-mentioned features of the present disclosure can be understood in detail, the present disclosure briefly summarized above may be described in more detail by reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of the scope, as the present disclosure may admit to other equally effective embodiments.

[0010] Figure 1 A schematic diagram showing a substrate according to one or more embodiments of the present disclosure;

[0011] Figure 2 A flowchart illustrating a method according to one or more embodiments of the present disclosure;

[0012] FIG. 3A to FIG. 3D The diagram is executed Figure 2 A schematic diagram of an electronic device during the method;

[0013] Figure 4A and Figure 4B Schematic diagram of one or more embodiments of the present disclosure Figure 3B an expanded view of region 4;

[0014] Figure 5 A schematic diagram illustrating a cluster tool according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of explanation or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0016] As used in this specification and the appended claims, the term "substrate" refers to a surface, or portion of a surface, on which a process acts. Those skilled in the art will also understand that reference to a substrate may also refer to only a portion of a substrate, unless the context clearly indicates otherwise. In addition, reference to deposited on a substrate may mean both a bare substrate and a substrate having one or more films or features deposited or formed on the substrate.

[0017] As used herein, "substrate" refers to any substrate or a material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces (on which treatment may be performed) include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials, such as metals, metal nitrides, metal alloys and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure and / or bake the substrate surface. In addition to the film treatment directly on the surface of the substrate itself, in the present disclosure, any film treatment step disclosed may also be performed on an underlayer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include such an underlayer as indicated by the context. Thus, for example, where a film / layer or a portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0018] The substrate surface may have one or more features formed in the substrate surface, one or more layers formed on the substrate surface, and combinations of the above items. The shape of the feature can be any suitable shape, including but not limited to peaks, grooves, and cylindrical vias. As used in this regard, the term "feature" refers to any intentional surface irregularity. Suitable examples of features include but are not limited to grooves with a top, two sidewalls, and a bottom, a peak with a top and two sidewalls extending upward from the surface, and a via with a sidewall extending downward from a surface with a bottom. In some embodiments, the bottom of the via comprises an open bottom defined or defined by an underlying material (e.g., a dielectric material), which may also define two sidewalls, or the underlying material at the bottom may be a conductor such as a metal (e.g., copper), which may be the same or different from the sidewall material.

[0019] The term “on” indicates that there is direct contact between elements. The term “directly on” indicates that there is direct contact between elements without intervening elements.

[0020] Embodiments of the present disclosure advantageously provide a tantalum-doped ruthenium layer that acts as a better copper (Cu) barrier for advanced nodes and can be used in more challenging structures as a combined barrier liner in logic devices. In advanced copper (Cu) interconnects, reducing the copper (Cu) barrier thickness has attracted attention because it requires accommodating smaller structures. However, the inherent barrier properties related to the activation energy of copper (Cu) diffusion limit the thickness that can act as an effective barrier. Embodiments of the present disclosure demonstrate that doping Ta into Ru can reduce the surface distance of the tantalum-doped ruthenium layer from the surface of the tantalum-doped ruthenium layer compared to a tantalum nitride (TaN) barrier layer. The activation energy of copper (Cu) diffusion at a distance of 1.50 eV increases to greater than 3.0 eV or greater than 4.0 eV.

[0021] While not wishing to be bound by theory, it is believed that the total thickness of the previously disclosed barrier or liner layers (eg, tantalum nitride) is greater than or equal to The total thickness can be used as an effective copper (Cu) barrier / liner. Embodiments of the present disclosure demonstrate that tantalum-doped ruthenium layers exhibit improved intrinsic barrier properties in bulk structures and are expected to reduce the barrier thickness to less than or equal to This allows for improved copper (Cu) interconnect structures.

[0022] Embodiments of the present disclosure show that the surface of the tantalum-doped ruthenium layer is A tantalum-doped ruthenium layer containing approximately 20 at. % tantalum may increase the activation energy for copper (Cu) diffusion by greater than or equal to 1 eV compared to the copper (Cu) diffusion activation energy of a 20% ruthenium-doped tantalum layer at a distance of .

[0023] Embodiments of the present disclosure are described by the accompanying drawings, which illustrate electronic devices and processes for forming interconnections according to one or more embodiments of the present disclosure. The processes shown are merely illustrative of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0024] Figure 1 Schematic diagram of a structure that may be used in accordance with one or more embodiments. Figure 1 The substrate 10 illustrated in FIG. 1 includes a material 15 (e.g., a dielectric) having a structure 20 formed in a surface 18 of the material 15. The structure 20 has a top 22, a bottom 26, and sides 24, 25. In the illustrated embodiment, the structure 20 is defined by the material 15 on the bottom 26 and the sides 24, 25. In some embodiments, the bottom 26 of the structure 20 is defined by a different material (not shown) than the sides 24, 25. For example, in some embodiments, the bottom 26 of the structure comprises a conductive material and the sides 24, 25 comprise a dielectric. In some embodiments, the bottom 26 of the structure 20 comprises a dielectric and the sides 24, 25 comprise a conductive material. In some embodiments, the bottom and sides are different materials, and both the bottom and sides are either dielectric or conductive materials.

[0025] The width W of structure 20 is defined as the distance between sides 24, 25. Those skilled in the art will recognize that the structures shown are exemplary and that typical structures may not have squared corners. The width of such a structure is measured as the average distance between the side walls measured parallel to the surface of the structure. The depth D of the structure is defined as the distance from the top 22 to the bottom 26 of the structure 20. The aspect ratio of structure 20 is defined as the depth D of the structure: the width W. In some embodiments, the aspect ratio is greater than or equal to 5:1, 10:1, 15:1, 20:1, or 25:1.

[0026] In some embodiments, material 15 comprises a dielectric. Suitable dielectrics include, but are not limited to, silicon oxide (SiO), silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), aluminum nitride (AlN), aluminum oxide (AlO), or a high-k dielectric material. In some embodiments, the material comprises a hardmask material (e.g., carbon (C)). As used in this specification and the appended claims, unless otherwise specified by a subscript, a chemical formula represents an element identity and is not intended to imply any particular stoichiometric ratio. For example, a titanium nitride (TiN) film can have any suitable combination of titanium and nitrogen atoms and is not limited to a unity relationship.

[0027] Some embodiments of the method include independently forming a tantalum nitride layer and a ruthenium layer by an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process. One or more embodiments of the method include sequentially forming a tantalum nitride layer and a ruthenium layer by an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process.

[0028] In some embodiments, physical vapor deposition (PVD) processing utilizing high density plasma and a biasable susceptor further improves one or more of barrier properties, carbon, and / or ruthenium content without damaging the low-k dielectric.

[0029] Figure 2 An embodiment of a method 100 of forming an interconnect (eg, a copper interconnect) in accordance with one or more embodiments of the present disclosure is illustrated. Figures 3A to 3D Graphic usage Figure 2 The electronic device 120 is processed by the method 100. Those skilled in the art will recognize that the illustrated embodiments are merely exemplary embodiments and that the present disclosure is not limited to the illustrated processes and / or illustrated embodiments.

[0030] Method 100 includes forming a tantalum nitride layer on a substrate (operation 102); forming a ruthenium layer on the tantalum nitride layer (operation 104); and exposing the tantalum nitride layer and the ruthenium layer to a plasma comprising a mixture of hydrogen (H2) and argon (Ar) to form a tantalum-doped ruthenium layer thereon (operation 106). In some embodiments, when the substrate includes a surface having a structure formed in the surface, method 100 optionally includes filling the structure with a metal filling material (operation 108).

[0031] Figure 3A A substrate 125 is shown having a first material 130 and a second material 132 forming a structure 135. The structure 135 is shown to be defined on sidewalls 137 by a surface 131 of the first material 130 and on a bottom 136 by a top surface 133 of the second material 132. In some embodiments, as Figure 3A As shown in FIG. 1 , a structure 135 in the first material 130 has a bottom 136 and at least one sidewall 137. In some embodiments, the structure 135 is a circular via having one cylindrical sidewall 137. In some embodiments, the structure 135 is a trench having two or more sidewalls 137.

[0032] The substrate 125 (and any layers formed thereon) is exposed to one or more operations of the method 100 to form a tantalum-doped ruthenium layer 150, such as Figure 3C The present disclosure describes the accompanying drawings and is related to a tantalum-doped ruthenium layer 150 . Figure 4A and Figure 4B 1. An embodiment of the present disclosure is shown in FIG. Figure 3B Expanded view of area 4 in .

[0033] The first material 130 can be any suitable material or combination of materials. In some embodiments, the first material 130 comprises a dielectric. Suitable dielectrics include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics (e.g., porous or carbon-doped SiO2 with a k value of less than about 5). x ). In some embodiments, the low-k dielectric comprises one or more of fluorine-doped silicon oxide, organosilicate glass, or porous silicon dioxide. In other embodiments, the dielectric layer is a multilayer structure. For example, in one or more embodiments, the dielectric layer comprises a stack of an oxide layer and a nitride layer.

[0034] The second material 132 can be any suitable material or combination of materials. In some embodiments, the second material 132 includes a conductive material. Suitable conductive materials include, but are not limited to, copper (Cu) or tungsten (W).

[0035] In some embodiments, the

[0036] Figure 3B A tantalum nitride (TaN) layer 142 is shown formed on the first material 130. In some embodiments, the tantalum nitride layer 142 is a conformal layer. As used in this manner, a "conformal layer" has a thickness that does not vary by more than 0.5%, 1%, 5%, 10%, or 15% relative to an average thickness. In some embodiments, the tantalum nitride layer 142 has a ruthenium (Ru) layer 144 deposited / formed on the tantalum nitride layer 142. In one or more embodiments, the ruthenium layer 144 is a conformal layer.

[0037] In some embodiments, the tantalum nitride layer 142 has a thickness of Egypt within the range of Egypt In some embodiments, the ruthenium layer 144 has a thickness of to within the range of to within the range of to within the range.

[0038] In some embodiments, the tantalum nitride layer 142 and the ruthenium layer 144 include a lamination of multiple layers. Figure 2 , Figure 3B and Figure 4B In the embodiment shown in , the tantalum nitride layer 142 and the ruthenium layer 144 are part of a stack of alternating tantalum nitride layers and ruthenium layers. In some embodiments, forming the doped tantalum nitride layer includes forming the stack of tantalum nitride layers and ruthenium layers by atomic layer deposition (ALD).

[0039] In some embodiments, the tantalum nitride layer 142 is formed to a first layer thickness T1 (eg, Figure 4A In an exemplary embodiment, the tantalum nitride layer 142 is formed by atomic layer deposition (ALD) to to In some embodiments, the first layer thickness is about

[0040] In some embodiments, atomic layer deposition of tantalum nitride (TaN) comprises sequential exposure of a tantalum precursor and a nitrogen reactant. The tantalum precursor may be any suitable tantalum species, including but not limited to penta(dimethylamino)tantalum (PDMAT), and the nitrogen reactant comprises ammonia (NH3). One skilled in the art will recognize that the reaction with PDMAT and NH3 represents only one possible ALD reaction and should not be considered to limit the scope of the present disclosure.

[0041] The temperature during the formation of the tantalum nitride layer 142 and / or the ruthenium layer 144 can be any suitable temperature, depending on, for example, the active species used. In some embodiments, the substrate is maintained at a temperature in the range of 150° C. to 350° C., including in the range of 175° C. to 325° C., or in the range of 200° C. to 300° C., or in the range of 225° C. to 275° C.

[0042] The pressure during the formation of the tantalum nitride layer 142 and / or the ruthenium layer 144 can be any suitable pressure, depending on, for example, the active species used. In some embodiments, the substrate is maintained at a pressure in the range of 0.5 Torr to 30 Torr, including in the range of 1 Torr to 25 Torr, or in the range of 5 Torr to 20 Torr, or in the range of 10 Torr to 15 Torr.

[0043] In some embodiments, the ruthenium layer 144 formed by operation 104 includes metallic ruthenium. In some embodiments, the ruthenium layer 144 consists essentially of metallic ruthenium. As used in this manner, the term "consisting essentially of" means that the specified layer (e.g., the ruthenium layer 144) is composed of greater than or equal to 95%, 98%, 99%, or 99.5% of the stated substance (e.g., ruthenium) on an atomic basis.

[0044] In some embodiments, the ruthenium layer 144 has a thickness T R (See Figure 5 A) to within the scope of to within the range of to within the range of to within the range of to within the range of to within the range.

[0045] In some embodiments, the ruthenium layer 144 is amorphous. In some embodiments, the ruthenium layer 144 is substantially amorphous. As used in this manner, the term "substantially amorphous" means that greater than 90%, 95%, or 98% of the volume of the ruthenium layer 144 is amorphous. In some embodiments, the ruthenium layer 144 has a nanocrystallite structure.

[0046] In some embodiments, the ruthenium layer 144 is formed while maintaining the substrate at the same process temperature as during the formation of the tantalum nitride layer 142 .

[0047] In some embodiments, the total thickness T of the tantalum nitride layer 142 and the ruthenium layer 144 is F (See Figure 5 A) to within the scope of to within the range of to within the range of to within the range of to within the range of to within the range of to within the range.

[0048] In some embodiments, Figure 4B As shown in FIG. 1 , the tantalum nitride layer 142 and the ruthenium layer 144 maintain a laminate structure appearance. Figure 4B The illustrated embodiment shows a stacked structure appearance including a single pair of two tantalum nitride layers 142 and two ruthenium layers 144, but the stacked structure appearance is not limited to a single pair of two tantalum nitride layers 142 and two ruthenium layers 144. The adjoining edges of the individual layers may be blurred together while maintaining the stacked structure appearance.

[0049] refer to Figure 3C , at operation 106, the tantalum nitride layer 142 and the ruthenium layer 144 are exposed to a plasma containing a mixture of hydrogen (H2) and argon (Ar) to produce a tantalum-doped ruthenium layer 150. As used herein, the step of exposing the tantalum nitride layer 142 and the ruthenium layer 144 to a plasma containing a mixture of hydrogen (H2) and argon (Ar) at operation 106 to produce the tantalum-doped ruthenium layer 150 may be referred to as a “plasma exposure process 106”.

[0050] Embodiments of the present disclosure advantageously provide a tantalum-doped ruthenium layer (eg, tantalum-doped ruthenium layer 150 ) having a copper (Cu) diffusion activation energy greater than that of a 20% ruthenium-doped tantalum layer.

[0051] Further embodiments of the present disclosure advantageously provide a tantalum-doped ruthenium layer at a distance from the surface of the tantalum-doped ruthenium layer. A tantalum-doped ruthenium layer (eg, tantalum-doped ruthenium layer 150 ) having a copper (Cu) diffusion activation energy greater than 4.0 eV at a distance of .

[0052] The thickness of individual layers may be affected by plasma exposure to varying degrees. In some embodiments, the plasma exposure process 106 does not change or substantially change the thickness of other layers (e.g., the tantalum nitride layer 142 and the ruthenium layer 144). As used in this manner, if the thickness variation is less than ±5% of the pre-plasma thickness, the thickness is substantially unchanged.

[0053] In some embodiments, the thickness of the tantalum-doped ruthenium layer 150 is equal to the total thickness T of the tantalum nitride layer 142 and the ruthenium layer 144. F (See Figure 5 A) In some embodiments, the thickness of the tantalum-doped ruthenium layer 150 is to within the scope of to within the range of to within the range of to within the range of to within the range of to within the range of to within the range.

[0054] In some embodiments, the concentration of the dopant (e.g., tantalum) in the tantalum-doped ruthenium layer 150 is in the range of 3 at % to 70 at % tantalum, including in the range of 5 at % to 65 at % tantalum, or in the range of 10 at. % to 60 at. % tantalum, or in the range of 15 at. % to 55 at. % tantalum, or in the range of 20 at. % to 50 at. % tantalum, or in the range of 25 at. % to 45 at. % tantalum, or in the range of 30 at. % to 40 at. % tantalum.

[0055] In some embodiments, the tantalum-doped ruthenium layer 150 is a conformal film formed on the sidewalls 137 and the bottom 136 of the structure 135 .

[0056] Refer to Figure 2 In the method 100, in some embodiments, at operation 108, a metal film 160 is deposited on the tantalum-doped ruthenium layer 150 to fill the structure, such as Figure 3D In some embodiments, the metal film 160 is a metal contact. In some embodiments, the metal film 160 includes or consists essentially of one or more of copper (Cu), cobalt (Co), tungsten (W), or copper doped with one or more of manganese (Mn), tungsten (W), or aluminum (Al).

[0057] The metal film 160 may be deposited by any suitable technique known to a skilled artisan. In some embodiments, the metal film 160 is deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD).

[0058] Various hardware arrangements may be used to implement method 100. In some embodiments, forming a tantalum nitride layer, forming a ruthenium layer, and exposing the tantalum nitride layer and the ruthenium layer to a plasma containing a mixture of hydrogen (H2) and argon (Ar) to form a tantalum-doped ruthenium layer occur in the same process chamber. In some embodiments, forming a tantalum nitride layer, forming a ruthenium layer, and exposing the tantalum nitride layer and the ruthenium layer to a plasma containing a mixture of hydrogen (H2) and argon (Ar) to form a tantalum-doped ruthenium layer occur in separate process chambers.

[0059] Some or all of the processes and methods of the present disclosure may also be implemented in hardware. As such, the processes may be implemented as software and executed using a computer system, implemented as hardware (e.g., an application specific integrated circuit or other type of hardware implementation), or implemented as a combination of software and hardware. When executed by a processor, the software routines convert a general purpose computer into a special purpose computer (controller) that controls chamber operations so that the processes are performed.

[0060] Additional embodiments of the present disclosure relate to processing tools for forming the described memory devices and methods, such as Figure 5 The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are positioned within the central transfer station 921, 931 and are configured to move robot blades and wafers to each of the multiple sides.

[0061] The cluster tool 900 includes a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916 and 918, also referred to as process stations, connected to a central transfer station. Each processing chamber provides a separate processing area isolated from an adjacent process station. The processing chamber can be any suitable chamber, including but not limited to a pre-cleaning chamber, a buffer chamber, a transfer space, a wafer orienter / degassing chamber, a cryogenic cooling chamber, a deposition chamber, an annealing chamber, an etching chamber, a selective etching chamber, and the like. The specific arrangement of the process chambers and components may vary depending on the cluster tool and should not be considered to limit the scope of the present disclosure.

[0062] exist Figure 5 In the embodiment shown in FIG, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. Although the loading chamber 954 is shown on the left side and the unloading chamber 956 is shown on the right side, those skilled in the art will understand that this is representative of only one possible configuration.

[0063] The size and shape of the loading chamber 954 and the unloading chamber 956 may vary depending, for example, on the substrates being processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette with a plurality of wafers positioned therein.

[0064] The robot 952 is within the factory interface 950 and can move between the loading chamber 954 and the unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 to a load lock chamber 960 through the factory interface 950. The robot 952 can also transfer wafers from a load lock chamber 962 to a cassette in the unloading chamber 956 through the factory interface 950. As will be appreciated by those skilled in the art, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960, and a second robot that transfers wafers between the load lock chamber 962 and the unloading chamber 956.

[0065] The cluster tool 900 shown has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 through the load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921, and the first transfer chamber 921 has at least one robot 925 positioned in the first transfer chamber 921. The robot 925 is also referred to as a robot wafer transfer mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960, 962, the process chambers 902, 904, 916, 918 and the buffer chambers 922, 924. The robot 925 of some embodiments is a multi-arm robot capable of independently moving more than one wafer at a time. In some embodiments, the first transfer chamber 921 contains more than one robot wafer transfer mechanism. The robot 925 in the first transfer chamber 921 is configured to move the wafer between chambers around the first transfer chamber 921. Individual wafers are carried on a wafer transfer blade located at the distal end of the first robot mechanism.

[0066] After processing the wafer in the first section 920, the wafer may be transferred to the second section 930 by a pass-through chamber. For example, the chambers 922, 924 may be one-way or two-way pass-through chambers. Pass-through chambers 922, 924 may be used, for example, to cryogenically cool the wafer prior to processing in the second section 930, or to allow for cooling or post-processing of the wafer prior to moving back to the first section 920.

[0067] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component that can control the processing chambers and the robot. For example, the system controller 990 may be a computer including a central processing unit (CPU), memory, suitable circuits, and storage.

[0068] Accordingly, one or more embodiments of the present disclosure relate to a cluster tool comprising one or more process chambers surrounding a central transfer station. One or more process chambers of some embodiments are configured to form a tantalum nitride layer on a substrate; to form a ruthenium layer on the tantalum nitride layer; and to expose the tantalum nitride layer and the ruthenium layer to a plasma comprising a mixture of hydrogen (H2) and argon (Ar) to form a tantalum-doped ruthenium layer thereon. At least one controller is connected to the one or more process chambers and the central transfer station. At least one controller of some embodiments has one or more configurations selected from the following items: a configuration for forming a tantalum nitride layer on a substrate; a configuration for forming a ruthenium layer on the tantalum nitride layer; a configuration for exposing the tantalum nitride layer and the ruthenium layer to a plasma comprising a mixture of hydrogen (H2) and argon (Ar) to form a tantalum-doped ruthenium layer thereon; and a configuration for moving a substrate between one or more process chambers and the central transfer station.

[0069] The process can typically be stored as a software routine in the memory of the system controller 990, which, when executed by the processor, causes the process chamber to perform the process of the present disclosure. The software routine can also be stored and / or executed by a second processor (not shown) away from the hardware controlled by the processor. Some or all of the methods of the present disclosure can also be performed in hardware. As such, the process can be implemented as software and executed using a computer system, implemented as hardware (e.g., an application specific integrated circuit or other type of hardware implementation), or implemented as a combination of software and hardware. When executed by the processor, the software routine converts a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chamber so that the process is performed.

[0070] Additional embodiments of the present disclosure are directed to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to: deposit a tantalum nitride film on a substrate; deposit a ruthenium-containing film on the substrate; anneal the substrate; and expose the substrate to a neon plasma.

[0071] One or more embodiments relate to a non-transitory computer-readable medium comprising instructions that, when executed by a controller of a processing chamber, cause the processing chamber to: form a tantalum nitride layer on a substrate; form a ruthenium layer on the tantalum nitride layer; and expose the tantalum nitride layer and the ruthenium layer to a plasma comprising a mixture of hydrogen (H2) and argon (Ar) to form a tantalum-doped ruthenium layer thereon.

[0072] For ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and similar terms may be used herein to describe the relationship of one element or feature to another element or feature, as shown in the figures. It will be understood that in addition to the orientation depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as being "below" or "beneath" other elements or features will be oriented as "above" other elements or features. Therefore, the exemplary term "below" can cover both orientations above and below. The device can be oriented in other ways (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0073] References throughout the specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Thus, phrases such as "in one or more embodiments," "certain embodiments," "in an embodiment," or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, in one or more embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0074] Although the present invention has been described with reference to specific embodiments, it will be appreciated by those skilled in the art that the described embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure may include modifications and variations within the scope of the appended claims and the equivalents of the claims.

Claims

1. A method for forming an interconnection, the method comprising the following steps: forming a tantalum nitride layer on a substrate; forming a ruthenium layer on the tantalum nitride layer; and The tantalum nitride layer and the ruthenium layer are exposed to plasma including a mixture of hydrogen (H2) and argon (Ar) to form a tantalum-doped ruthenium layer thereon.

2. The method of claim 1, wherein the tantalum-doped ruthenium layer contains tantalum in a range from 3 at. % to 70 at. %.

3. The method of claim 1, wherein the tantalum-doped ruthenium layer contains greater than or equal to 60 at. % ruthenium.

4. The method of claim 1, wherein the tantalum nitride layer has a thickness of to and the ruthenium layer has a thickness in the range of to within the range. 5 . The method of claim 1 , wherein each of the tantalum nitride layer and the ruthenium layer is independently formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD). 6 . The method of claim 5 , wherein each of the tantalum nitride layer and the ruthenium layer is independently formed by atomic layer deposition (ALD) at a temperature in a range of 200° C. to 300° C. and a pressure in a range of 0.5 Torr to 30 Torr.

7. The method of claim 1, wherein the tantalum-doped ruthenium layer has a thickness less than or equal to 8. The method of claim 7, wherein the thickness is less than or equal to 9. The method of claim 7, wherein the tantalum-doped ruthenium layer has a copper (Cu) diffusion activation energy greater than 20% of the copper diffusion activation energy of the ruthenium-doped tantalum layer.

10. The method of claim 7, wherein the tantalum-doped ruthenium layer is at a distance from the surface of the tantalum-doped ruthenium layer. The copper (Cu) diffusion activation energy is greater than 4.0 eV at a distance of .

11. The method of claim 1 further comprising the step of depositing a metal contact on the tantalum-doped ruthenium layer.

12. The method of claim 11, wherein the metal contact comprises one or more of: copper, cobalt, tungsten, or copper doped with one or more of manganese, tungsten, or aluminum.

13. The method of claim 1, wherein the substrate has a surface with a structure formed in the surface, the structure extending a distance into the substrate and having sidewalls and a bottom, the bottom comprising a conductive material.

14. The method of claim 13 wherein the sidewalls of the structure comprise a low-k dielectric material.

15. The method of claim 14, wherein the tantalum-doped ruthenium layer is a conformal film formed on the sidewalls and bottom of the structure.

16. The method of claim 1, wherein the tantalum nitride layer and the ruthenium layer are part of a stack of alternating tantalum nitride and ruthenium layers.

17. A method of forming an interconnect, the method comprising the steps of: forming at least one conformal tantalum nitride layer and at least one ruthenium layer on a substrate having a surface, the surface having a structure formed in the surface, the structure extending a distance into the substrate and having sidewalls and a bottom, the bottom comprising a conductive material, the sidewalls comprising a low-k dielectric material, the low-k dielectric material comprising one or more of fluorine-doped silicon oxide, organosilicate glass, or porous silicon dioxide, the at least one ruthenium layer being formed on the at least one conformal tantalum nitride layer; and The conformal tantalum nitride layer and the ruthenium layer are exposed to a plasma comprising a mixture of hydrogen (H2) and argon (Ar) to form a tantalum-doped ruthenium layer comprising greater than or equal to 80 at. % ruthenium.

18. The method of claim 17, wherein the tantalum-doped ruthenium layer has a thickness less than or equal to 19. An electronic device comprising: a substrate having a surface with a structure formed in the surface, the structure extending a distance into the substrate and having sidewalls and a bottom, the bottom comprising a conductive material and the sidewalls comprising a dielectric material; a tantalum-doped ruthenium layer, wherein the tantalum-doped ruthenium layer comprises greater than or equal to 80 at. % ruthenium in the structure; and A metal filling is provided, wherein the metal is filled in the structure on the tantalum-doped ruthenium layer.

20. The electronic device of claim 19, wherein the tantalum-doped ruthenium layer has a thickness less than Thickness.

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