Data processing method and data processing device

Abstract

The embodiment of the present application provides a data processing method and a data processing device, which adopts FEC coding and combines PCS technology to meet longer transmission distances. Specifically, PCS processing is performed on a first bit set of k bits to obtain a second bit set, where k is an integer greater than 1. FEC coding is performed on the second bit set and a third bit set of k bits other than the first bit set to obtain a fourth bit set. The fourth bit set includes m0 first bit subsets, each first bit subset includes F0 bits, m0 is an integer greater than 1, and F0 is an even number greater than 1. The fourth bit set is subjected to a first interleaving process to obtain a fifth bit set. The fifth bit set includes m0 second bit subsets, each second bit subset includes F0 bits, F0 / 2 bits of each second bit subset come from the second bit set, and the other F0 / 2 bits of each second bit subset come from the third bit set and / or FEC-coded check bits.

Claims

1. A data processing method, characterized in that: include: Performing probabilistic constellation shaping (PCS) processing on a first bit set of k bits to obtain a second bit set, where k is an integer greater than 1; performing forward error correction (FEC) encoding on the second bit set and a third bit set of the k bits excluding the first bit set to obtain a fourth bit set, where the fourth bit set includes m0 first bit subsets, each of the first bit subsets includes F0 bits, where m0 is an integer greater than 1, and F0 is an even number greater than 1; Performing a first interleaving process on the fourth bit set obtains a fifth bit set, the fifth bit set including m0 second bit subsets, each second bit subset including F0 bits, F0 / 2 bits in each second bit subset coming from the second bit set, and another F0 / 2 bits in each second bit subset coming from the third bit set and / or the FEC encoded check bits.

2. The method according to claim 1, characterized in that The fifth bit set includes m0×F0 bits, and each of the second bit subsets includes consecutive F0 bits.

3. The method according to claim 1, characterized in that Each of the second bit subsets is presented as a square matrix.

4. The method according to any one of claims 1 to 3, characterized in that The F0 bits in each of the second bit subsets are distributed as F1 rows and F1 columns, F1 / 2 bits of the F1 bits in each row of the second bit subset come from the second bit set, the second bit set includes m0×F0 / 2 bits, and the other F1 / 2 bits of the F1 bits in each row of the second bit subset come from the third bit set and / or the check bits of the FEC code.

5. The method according to claim 4, characterized in that F0=256, F1=16.

6. The method according to claim 4, characterized in that F0=256, F1=16, the second bit subset has the i2th row and the The bits of the column are from the second bit set, 0≤i2<16, 0≤j2<8; Alternatively, the bit in the i2th row and the (j2×2-i2%2+1)th column in the second bit subset is from the second bit set, 0≤i2<16, 0≤j2<8; in, means rounding a down to the nearest integer, and b%c means taking the modulus of b to c.

7. The method according to claim 4, characterized in that F0=256, F1=16, and the bits in the second bit subset satisfy one or more of the following: The bits in row 0 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 1 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 2 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in row 3 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; The bits in row 4 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 5 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 6 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in row 7 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; The bits in row 8 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 9 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 10 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in row 11 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; The bits in row 12 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 13 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 14 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in the 15th row and the 1st, 2nd, 5th, 6th, 9th, 10th, 13th and 14th columns in the second bit subset are from the second bit set.

8. The method according to any one of claims 1 to 3, characterized in that F0=256, m1 of the first bit subsets in the fourth bit set, a total of m1×256 bits, come from the second bit set, and m0=m1×2.

9. The method according to any one of claims 1 to 3, characterized in that F0=256, the m0×256 bits in the fourth bit set are distributed as 32 rows and m0×8 columns, the m0×256 bits in the fifth bit set are distributed as 32 rows and m0×8 columns, the m0×8 bits in the r1-th row in the fifth bit set come from the m0×8 bits in the r0-th row in the fourth bit set, where 0≤r0<32, 0≤r1<32.

10. The method according to any one of claims 1 to 3, characterized in that Performing FEC encoding on the second bit set and a third bit set of the k bits excluding the first bit set to obtain a fourth bit set includes: Performing pre-coding interleaving processing on the second bit set and the third bit set to obtain a sixth bit set, where the number of bits in the sixth bit set is equal to the sum of the number of bits in the second bit set and the number of bits in the third bit set, the sixth bit set including m3 third bit subsets, the m3 third bit subsets being distributed in 2 rows and m4 columns, where m3=2×m4, m3 is an integer greater than 1 and less than m0, each third bit subset in some of the third bit subsets including F0 bits, and each third bit subset in another part of the third bit subsets including F2 bits, where F2 is an even number greater than 1 and less than F0; Perform FEC encoding on the sixth bit set to obtain the fourth bit set.

11. The method according to claim 10, characterized in that m3=14, m4=7, F0=256, F2=240, each third bit subset of columns 0 to 5 includes 16 rows and 16 columns of bits, each third bit subset of column 6 includes 16 rows and 15 columns of bits, F0 / 2 bits in each third bit subset of columns 0 to 4 come from the second bit set, and another F0 / 2 bits in each third bit subset of columns 0 to 4 come from the third bit set, 9 bits in each row of each third bit subset of column 5 come from the second bit set, and another 7 bits in each row of each third bit subset of column 5 come from the third bit set, and F2 bits in each third bit subset of column 6 come from the second bit set.

12. The method according to claim 9, characterized in that r0＝r1。 13. The method according to any one of claims 1 to 3, characterized in that m0=12 or 16.

14. The method according to any one of claims 1 to 3, characterized in that After performing interleaving processing on the fourth bit set to obtain a fifth bit set, the method further includes: Performing a second interleaving process on every two first bit streams among the L first bit streams to obtain a total of L / 2 second bit streams, each of the first bit streams including a plurality of the fifth bit sets, where L is an even number greater than 0; Performing symbol mapping and polarization division on the L / 2 second bit streams to obtain a dual-polarization symbol stream, wherein the symbol mapping and the polarization division map t bits into one dual-polarization symbol, where t is an integer greater than 0; Digital signal processing (DSP) is performed on the dual-polarization symbol stream to form a frame.

15. The method according to claim 14, characterized in that The amplitude bits in the dual-polarization symbol are from the second bit set.

16. The method according to claim 15, characterized in that t=8, the dual-polarization symbol is a dual-polarization DP-16QAM symbol.

17. The method according to claim 16, characterized in that Performing DSP framing on the dual-polarization symbol stream includes: Every 172032 dual-polarization DP-16QAM symbols are framed to obtain a DSP superframe, where the superframe contains 175104 dual-polarization symbols.

18. The method according to any one of claims 1 to 3, characterized in that The number of bits in the first bit set is an integer multiple of 2, 4, 8, or 16, the second bit set includes 2048 bits, the third bit set includes 1504 bits, and the fourth bit set includes 4096 bits.

19. A data processing method, characterized in that: include: Acquire first data from a data frame, where the first data includes r rows and q columns of bits, where r is an integer greater than 0, and q is an integer greater than 0; Performing a cyclic redundancy check (CRC) on the first data and / or inserting padding bits to obtain second data, wherein the second data includes d CRC parity bits and / or d PAD Filling bits, d CRC is an integer greater than or equal to 0, d PAD is an integer greater than or equal to 0; The second data is scrambled to obtain third data, the number of bits of the third data is d scr =r×q+d CP , d CP =d CRC +d PAD ; Get k bits of the third data, where k is an integer greater than 1, d scr is an integer multiple of k; Performing probabilistic constellation shaping (PCS) processing on a first bit set of the k bits to obtain a second bit set; Forward error correction (FEC) encoding is performed on the second bit set and a third bit set of the k bits excluding the first bit set to obtain a fourth bit set.

20. The method according to claim 19, characterized in that The fourth bit set includes m0 first bit subsets, each of the first bit subsets includes F0 bits, m0 is an integer greater than 1, and F0 is an even number greater than 1. FEC encoding is performed on the second bit set and a third bit set of the k bits excluding the first bit set to obtain a fourth bit set, including: Performing pre-coding interleaving processing on the second bit set and the third bit set to obtain a sixth bit set, where the number of bits in the sixth bit set is equal to the sum of the number of bits in the second bit set and the number of bits in the third bit set, the sixth bit set including m3 third bit subsets, the m3 third bit subsets being distributed in 2 rows and m4 columns, where m3=2×m4, m3 is an integer greater than 1 and less than m0, each third bit subset in some of the third bit subsets including F0 bits, and each third bit subset in another part of the third bit subsets including F2 bits, where F2 is an even number greater than 1 and less than F0; Perform FEC encoding on the sixth bit set to obtain the fourth bit set.

21. The method according to claim 19 or 20, characterized in that The number of bits in the first bit set is an integer multiple of 2, 4, 8, or 16, the second bit set includes 2048 bits, the third bit set includes 1504 bits, and the fourth bit set includes 4096 bits.

22. The method according to claim 19 or 20, characterized in that d scr It is an integer multiple of 4×k, q=10280.

23. The method according to claim 19 or 20, characterized in that r=79,d CP =328,k=3224; Or, r = 83, d CP =32, k=3386; Or, r = 83, d CP =536, k=3388; Or, r = 87, d CP =72, k=2662; Or, r = 87, d CP =744, k=2664; Or, r = 87, d CP =3432, k=2672; Or, r = 104, d CP =704, k=3184; Or, r = 104, d CP =3392, k=3192; Or, r = 105, d CP =504, k=3214; Or, r = 105, d CP =1176, k=3216; Or, r = 109, d CP =40, k=2668; Or, r = 109, d CP =880, k=2670; Or, r = 110, d CP =176, k=3366; Or, r = 110, d CP =848, k=3368; Or, r = 110, d CP =3536, k=3376; Or, r = 111, d CP =648, k=3398; Or, r = 131, d CP =8, k=2672; Or, r = 131, d CP =1016, k=2674; Or, r = 131, d CP =680, k=3208; Or, r = 132, d CP =480, k=3232; Or, r = 132, d CP =1320, k=3234; Or, r = 137, d CP =320, k=3354; Or, r = 137, d CP =1160, k=3356; Or, r = 138, d CP =120, k=3378; Or, r = 138, d CP =960, k=3380; Or, r = 152, d CP =344, k=2658; Or, r = 152, d CP =1520, k=2660; Or, r = 153, d CP =648, k=2676; Or, r = 157, d CP =856, k=3204; Or, r = 158, d CP =656, k=3224; Or, r = 165, d CP =264, k=3366; Or, r = 165, d CP =1272, k=3368; Or, r = 166, d CP =64, k=3386; Or, r = 166, d CP =1072, k=3388; Or, r = 174, d CP =144, k=2662; Or, r = 174, d CP =1488, k=2664; Or, r = 175, d CP =616, k=2678; Or, r = 183, d CP =360, k=3200; Or, r = 183, d CP =1536, k=3202; Or, r = 184, d CP =664, k=3218; Or, r = 184, d CP =1840, k=3220; Or, r = 185, d CP =968, k=3236; Or, r = 192, d CP =744, k=3358; Or, r = 192, d CP =1920, k=3360; Or, r = 193, d CP =1048, k=3376; Or, r = 194, d CP =176, k=3392; Or, r = 194, d CP =1352, k=3394; Or, r = 196, d CP =616, k=2666; Or, r = 209, d CP =536, k=3198; Or, r = 209, d CP =1880, k=3200; Or, r = 210, d CP =1008, k=3214; Or, r = 211, d CP =136, k=3228; Or, r = 211, d CP =1480, k=3230; Or, r = 217, d CP =280, k=2656; Or, r = 217, d CP =1960, k=2658; Or, r = 218, d CP =80, k=2668; Or, r = 218, d CP =1760, k=2670; Or, r = 219, d CP =1224, k=3352; Or, r = 220, d CP =352, k=3366; Or, r = 220, d CP =1696, k=3368; Or, r = 221, d CP =824, k=3382; Or, r = 221, d CP =2168, k=3384; Or, r = 222, d CP =1296, k=3398; Or, r = 235, d CP =376, k=3196; Or, r = 235, d CP =1888, k=3198; Or, r = 236, d CP =680, k=3210; Or, r = 236, d CP =2192, k=3212; Or, r = 237, d CP =984, k=3224; Or, r = 238, d CP =1288, k=3238; Or, r = 239, d CP =920, k=2660; Or, r = 240, d CP =1728, k=2672; Or, r = 247, d CP =1000, k=3360; Or, r = 247, d CP =2512, k=3362; Or, r = 248, d CP =1304, k=3374; Or, r = 249, d CP =96, k=3386; Or, r = 249, d CP =1608, k=3388; Or, r = 250, d CP =400, k=3400; Or, r = 250, d CP =1912, k=3402; Or, r = 261, d CP =216, k=2662; Or, r = 261, d CP =2232, k=2664; Or, r = 261, d CP =1560, k=3196; Or, r = 262, d CP =16, k=2672; Or, r = 262, d CP =2032, k=2674; Or, r = 262, d CP =1360, k=3208; Or, r = 263, d CP =1160, k=3220; Or, r = 264, d CP =960, k=3232; Or, r = 264, d CP =2640, k=3234; Or, r = 274, d CP =640, k=3354; Or, r = 274, d CP =2320, k=3356; Or, r = 275, d CP =440, k=3366; Or, r = 275, d CP =2120, k=3368; Or, r = 276, d CP =240, k=3378; Or, r = 276, d CP =1920, k=3380; Or, r = 277, d CP =40, k=3390; Or, r = 277, d CP =1720, k=3392; Or, r = 283, d CP =2032, k=2666; Or, r = 284, d CP =488, k=2674; Or, r = 284, d CP =2672, k=2676; Or, r = 287, d CP =896, k=3194; Or, r = 287, d CP =2744, k=3196; Or, r = 288, d CP =1704, k=3206; Or, r = 289, d CP =664, k=3216; Or, r = 289, d CP =2512, k=3218; Or, r = 290, d CP =1472, k=3228; Or, r = 291, d CP =432, k=3238; Or, r = 291, d CP =2280, k=3240; Or, r = 302, d CP =80, k=3360; Or, r = 302, d CP =1928, k=3362; Or, r = 303, d CP =888, k=3372; Or, r = 303, d CP =2736, k=3374; Or, r = 304, d CP =688, k=2658; Or, r = 304, d CP =3040, k=2660; Or, r = 304, d CP =1696, k=3384; Or, r = 305, d CP =2168, k=2668; Or, r = 305, d CP =656, k=3394; Or, r = 305, d CP =2504, k=3396; Or, r = 306, d CP =1296, k=2676; Or, r = 313, d CP =1912, k=3194; Or, r = 314, d CP =1712, k=3204; Or, r = 315, d CP =1512, k=3214; Or, r = 316, d CP =1312, k=3224; Or, r = 317, d CP =1112, k=3234; Or, r = 317, d CP =3128, k=3236; Or, r = 326, d CP =320, k=2660; Or, r = 326, d CP =2840, k=2662; Or, r = 327, d CP =120, k=2668; Or, r = 327, d CP =2640, k=2670; Or, r = 328, d CP =2440, k=2678; Or, r = 329, d CP =728, k=3356; Or, r = 329, d CP =2744, k=3358; Or, r = 330, d CP =528, k=3366; Or, r = 330, d CP =2544, k=3368; Or, r = 331, d CP =328, k=3376; Or, r = 331, d CP =2344, k=3378; Or, r = 332, d CP =128, k=3386; Or, r = 332, d CP =2144, k=3388; Or, r = 333, d CP =1944, k=3398; Or, r = 339, d CP =744, k=3192; Or, r = 339, d CP =2928, k=3194; Or, r = 340, d CP =1384, k=3202; Or, r = 341, d CP =2024, k=3212; Or, r = 342, d CP =480, k=3220; Or, r = 342, d CP =2664, k=3222; Or, r = 343, d CP =1120, k=3230; Or, r = 343, d CP =3304, k=3232; Or, r = 344, d CP =1760, k=3240; Or, r = 348, d CP =288, k=2662; Or, r = 348, d CP =2976, k=2664; Or, r = 349, d CP =760, k=2670; Or, r = 349, d CP =3448, k=2672; Or, r = 350, d CP =1232, k=2678; Or, r = 356, d CP =704, k=3352; Or, r = 356, d CP =2888, k=3354; Or, r = 357, d CP =1344, k=3362; Or, r = 357, d CP =3528, k=3364; Or, r = 358, d CP =1984, k=3372; Or, r = 359, d CP =440, k=3380; Or, r = 359, d CP =2624, k=3382; Or, r = 360, d CP =1080, k=3390; Or, r = 360, d CP =3264, k=3392; Or, r = 361, d CP =1720, k=3400; Or, r = 365, d CP =1592, k=3192; Or, r = 366, d CP =720, k=3200; Or, r = 366, d CP =3072, k=3202; Or, r = 367, d CP =2200, k=3210; Or, r = 368, d CP =1328, k=3218; Or, r = 368, d CP =3680, k=3220; Or, r = 369, d CP =2304, k=2658; Or, r = 369, d CP =456, k=3226; Or, r = 369, d CP =2808, k=3228; Or, r = 370, d CP =592, k=2664; Or, r = 370, d CP =3448, k=2666; Or, r = 370, d CP =1936, k=3236; Or, r = 371, d CP =1736, k=2672; Or, r = 384, d CP =1488, k=3358; Or, r = 384, d CP =3840, k=3360; Or, r = 385, d CP =616, k=3366; Or, r = 385, d CP =2968, k=3368; Or, r = 386, d CP =2096, k=3376; Or, r = 387, d CP =1224, k=3384; Or, r = 387, d CP =3576, k=3386; Or, r = 388, d CP =352, k=3392; Or, r = 388, d CP =2704, k=3394; Or, r = 389, d CP =1832, k=3402; Or, r = 391, d CP =2440, k=2660; Or, r = 392, d CP =1232, k=2666; Or, r = 392, d CP =2240, k=3200; Or, r = 393, d CP =24, k=2672; Or, r = 393, d CP =3048, k=2674; Or, r = 393, d CP =2040, k=3208; Or, r = 394, d CP =1840, k=3216; Or, r = 395, d CP =1640, k=3224; Or, r = 396, d CP =1440, k=3232; Or, r = 396, d CP =3960, k=3234; Or, r = 397, d CP =1240, k=3240; Or, r = 397, d CP =3760, k=3242; Or, r = 411, d CP =960, k=3354; Or, r = 411, d CP =3480, k=3356; Or, r = 412, d CP =760, k=3362; Or, r = 412, d CP =3280, k=3364; Or, r = 413, d CP =2912, k=2662; Or, r = 413, d CP =560, k=3370; Or, r = 413, d CP =3080, k=3372; Or, r = 414, d CP =2208, k=2668; Or, r = 414, d CP =360, k=3378; Or, r = 414, d CP =2880, k=3380; Or, r = 415, d CP =1504, k=2674; Or, r = 415, d CP =160, k=3386; Or, r = 415, d CP =2680, k=3388; Or, r = 416, d CP =2480, k=3396; Or, r = 418, d CP =1072, k=3198; Or, r = 418, d CP =3760, k=3200; Or, r = 419, d CP =1544, k=3206; Or, r = 419, d CP =4232, k=3208; Or, r = 420, d CP =2016, k=3214; Or, r = 421, d CP =2488, k=3222; Or, r = 422, d CP =272, k=3228; Or, r = 422, d CP =2960, k=3230; Or, r = 423, d CP =744, k=3236; Or, r = 423, d CP =3432, k=3238; Or, r = 434, d CP =560, k=2656; Or, r = 434, d CP =3920, k=2658; Or, r = 435, d CP =360, k=2662; Or, r = 435, d CP =3720, k=2664; Or, r = 436, d CP =160, k=2668; Or, r = 436, d CP =3520, k=2670; Or, r = 437, d CP =3320, k=2676; Or, r = 438, d CP =2448, k=3352; Or, r = 439, d CP =232, k=3358; Or, r = 439, d CP =2920, k=3360; Or, r = 440, d CP =704, k=3366; Or, r = 440, d CP =3392, k=3368; Or, r = 441, d CP =1176, k=3374; Or, r = 441, d CP =3864, k=3376; Or, r = 442, d CP =1648, k=3382; Or, r = 442, d CP =4336, k=3384; Or, r = 443, d CP =2120, k=3390; Or, r = 444, d CP =2424, k=3198; Or, r = 444, d CP =2592, k=3398; Or, r = 445, d CP =712, k=3204; Or, r = 445, d CP =3568, k=3206; Or, r = 446, d CP =1856, k=3212; Or, r = 447, d CP =144, k=3218; Or, r = 447, d CP =3000, k=3220; Or, r = 448, d CP =1288, k=3226; Or, r = 448, d CP =4144, k=3228; Or, r = 449, d CP =2432, k=3234; Or, r = 456, d CP =1032, k=2658; Or, r = 456, d CP =4560, k=2660; Or, r = 457, d CP =1336, k=2664; Or, r = 458, d CP =1640, k=2670; Or, r = 459, d CP =1944, k=2676; Or, r = 466, d CP =1888, k=3356; Or, r = 466, d CP =4744, k=3358; Or, r = 467, d CP =176, k=3362; Or, r = 467, d CP =3032, k=3364; Or, r = 468, d CP =1320, k=3370; Or, r = 468, d CP =4176, k=3372; Or, r = 469, d CP =2464, k=3378; Or, r = 470, d CP =752, k=3196; Or, r = 470, d CP =3776, k=3198; Or, r = 470, d CP =752, k=3384; Or, r = 470, d CP =3608, k=3386; Or, r = 471, d CP =2568, k=3204; Or, r = 471, d CP =1896, k=3392; Or, r = 471, d CP =4752, k=3394; Or, r = 472, d CP =1360, k=3210; Or, r = 472, d CP =4384, k=3212; Or, r = 472, d CP =184, k=3398; Or, r = 472, d CP =3040, k=3400; Or, r = 473, d CP =152, k=3216; Or, r = 473, d CP =3176, k=3218; Or, r = 474, d CP =1968, k=3224; Or, r = 475, d CP =760, k=3230; Or, r = 475, d CP =3784, k=3232; Or, r = 476, d CP =2576, k=3238; Or, r = 478, d CP =1840, k=2660; Or, r = 479, d CP =2648, k=2666; Or, r = 480, d CP =3456, k=2672; Or, r = 481, d CP =568, k=2676; Or, r = 481, d CP =4264, k=2678; Or, r = 493, d CP =184, k=3352; Or, r = 493, d CP =3208, k=3354; Or, r = 494, d CP =2000, k=3360; Or, r = 494, d CP =5024, k=3362; Or, r = 495, d CP =792, k=3366; Or, r = 495, d CP =3816, k=3368; Or, r = 496, d CP =1936, k=3196; Or, r = 496, d CP =2608, k=3374; Or, r = 497, d CP =1232, k=3202; Or, r = 497, d CP =4424, k=3204; Or, r = 497, d CP =1400, k=3380; Or, r = 497, d CP =4424, k=3382; Or, r = 498, d CP =528, k=3208; Or, r = 498, d CP =3720, k=3210; Or, r = 498, d CP =192, k=3386; Or, r = 498, d CP =3216, k=3388; Or, r = 499, d CP =1672, k=2656; Or, r = 499, d CP =3016, k=3216; Or, r = 499, d CP =2008, k=3394; Or, r = 499, d CP =5032, k=3396; Or, r = 500, d CP =2984, k=2662; Or, r = 500, d CP =2312, k=3222; Or, r = 500, d CP =800, k=3400; Or, r = 500, d CP =3824, k=3402; Or, r = 501, d CP =432, k=2666; Or, r = 501, d CP =4296, k=2668; Or, r = 501, d CP =1608, k=3228; Or, r = 501, d CP =4800, k=3230; Or, r = 502, d CP =1744, k=2672; Or, r = 502, d CP =904, k=3234; Or, r = 502, d CP =4096, k=3236; Or, r = 503, d CP =3056, k=2678.

24. The method according to claim 19 or 20, characterized in that d scr =336×k。 25. The method according to claim 19 or 20, characterized in that Performing CRC on the first data includes: Perform CRC-32 check on a total of r×q / p bits in each r / p rows of the first data to add a check bit with a length of 32 bits, d CRC =32×p, r is divisible by p, and p is an integer greater than 1; or, For the first r in the first data F0 ×(p-1) rows of each r F0 Rows total q×r F0 The CRC-32 check is performed on the first data to add a check bit with a length of 32 bits, and the last r F1 Rows total q×r F1 bits to perform CRC-32 check to add a check bit with a length of 32 bits, where d CRC =32×p, r cannot be divided by p, p is an integer greater than 1, r F0 ×(p-1)+r F1 =r, integer r F0 Greater than integer r F1 .

26. The method according to claim 19 or 20, characterized in that q＝2056。 27. The method according to claim 26, characterized in that Performing CRC on the first data includes: For the first r in the first data F0 ×(p-1) rows of each r F0 Rows total q×r F0 The CRC-32 check is performed on the first data to add a check bit with a length of 32 bits, and the last r F1 Rows total q×r F1 bits to perform CRC-32 check to add a check bit with a length of 32 bits, where d CRC =32×p, r cannot be divided by p, p is an integer greater than 1, r F0 ×(p-1)+r F1 =r, integer r F0 Greater than integer r F1 .

28. The method according to claim 26, characterized in that r＝435。 29. The method according to claim 28, characterized in that p=22, r F0 =20, r F1 =15, performing CRC on the first data includes: A CRC-32 check is performed on each of the first 420 lines, totaling 41,120 bits, in the first data to add a check bit with a length of 32 bits, and a CRC-32 check is performed on the last 15 lines, totaling 30,840 bits, in the first data to add a check bit with a length of 32 bits.

30. The method according to claim 28, wherein d CP =3432, k=2672, or, d CP =744, k=2664.

31. The method according to claim 26, wherein r=546,d CP =1008,k=3344; Or, r = 546, d CP =3696, k=3352; Or, r = 547, d CP =1640, k=3352; Or, r = 547, d CP =4328, k=3360; Or, r = 548, d CP =2272, k=3360; Or, r = 548, d CP =4960, k=3368; Or, r = 549, d CP =216, k=3360; Or, r = 549, d CP =2904, k=3368; Or, r = 549, d CP =5592, k=3376; Or, r = 550, d CP =848, k=3368; Or, r = 550, d CP =3536, k=3376; Or, r = 551, d CP =1480, k=3376; Or, r = 551, d CP =4168, k=3384; Or, r = 552, d CP =2112, k=3384; Or, r = 552, d CP =4800, k=3392; Or, r = 553, d CP =56, k=3384; Or, r = 553, d CP =2744, k=3392; Or, r = 553, d CP =5432, k=3400; Or, r = 554, d CP =688, k=3392; Or, r = 554, d CP =3376, k=3400; Or, r = 555, d CP =1320, k=3400; Or, r = 555, d CP =4008, k=3408; Or, r = 556, d CP =1952, k=3408; Or, r = 556, d CP =4640, k=3416; Or, r = 557, d CP =2584, k=3416; Or, r = 557, d CP =5272, k=3424; Or, r = 558, d CP =528, k=3416; Or, r = 558, d CP =3216, k=3424; Or, r = 559, d CP =1160, k=3424; Or, r = 559, d CP =3848, k=3432; Or, r = 560, d CP =1792, k=3432; Or, r = 560, d CP =4480, k=3440; Or, r = 561, d CP =2424, k=3440; Or, r = 561, d CP =5112, k=3448; Or, r = 562, d CP =368, k=3440; Or, r = 562, d CP =3056, k=3448; Or, r = 562, d CP =5744, k=3456.

32. The method according to claim 26, wherein r=520,d CP =704, k=3184; or, r=520, d CP =3392, k=3192; Or, r = 520, d CP =6080, k=3200; Or, r = 521, d CP =1336, k=3192; Or, r = 521, d CP =4024, k=3200; Or, r = 522, d CP =1968, k=3200; Or, r = 522, d CP =4656, k=3208; Or, r = 523, d CP =2600, k=3208; Or, r = 523, d CP =5288, k=3216; Or, r = 524, d CP =544, k=3208; Or, r = 524, d CP =3232, k=3216; Or, r = 525, d CP =1176, k=3216; Or, r = 525, d CP =3864, k=3224; Or, r = 526, d CP =1808, k=3224; Or, r = 526, d CP =4496, k=3232; Or, r = 527, d CP =2440, k=3232; Or, r = 527, d CP =5128, k=3240; Or, r = 528, d CP =384, k=3232; Or, r = 528, d CP =3072, k=3240; Or, r = 528, d CP =5760, k=3248; Or, r = 529, d CP =1016, k=3240; Or, r = 529, d CP =3704, k=3248; Or, r = 530, d CP =1648, k=3248; Or, r = 530, d CP =4336, k=3256; Or, r = 531, d CP =2280, k=3256; Or, r = 531, d CP =4968, k=3264; Or, r = 532, d CP =2912, k=3264; Or, r = 532, d CP =224, k=3256; Or, r = 533, d CP =856, k=3264; Or, r = 533, d CP =3544, k=3272; Or, r = 534, d CP =1488, k=3272; Or, r = 534, d CP =4176, k=3280; Or, r = 535, d CP =2120, k=3280; Or, r = 535, d CP =4808, k=3288.

33. The method according to claim 19 or 20, characterized in that The fourth bit set includes m0 first bit subsets, where m0 is an integer greater than 1. After performing the FEC encoding on the second bit set and the third bit set to obtain the fourth bit set, the method further includes: Performing a first interleaving process on the fourth bit set to obtain a fifth bit set, the fifth bit set including m0 second bit subsets, each second bit subset including 256 bits, 128 bits in each second bit subset coming from the second bit set, and the other 128 bits in each second bit subset coming from the third bit set and / or the FEC encoded check bits.

34. The method according to claim 33, wherein Each of the second bit subsets includes 256 consecutive bits.

35. The method according to claim 33, wherein Each of the second bit subsets is presented as a square matrix.

36. The method according to claim 33, wherein The 256 bits of the second bit subset are distributed into 16 rows and 16 columns, and the bits in the second bit subset satisfy one or more of the following: The bits in row 0 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 1 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 2 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in row 3 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; The bits in row 4 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 5 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 6 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in row 7 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; The bits in row 8 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 9 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 10 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in row 11 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; The bits in row 12 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 13 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 14 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in the 15th row and the 1st, 2nd, 5th, 6th, 9th, 10th, 13th and 14th columns in the second bit subset are from the second bit set.

37. The method according to claim 33, wherein The m0×256 bits in the fourth bit set are distributed as 32 rows and m0×8 columns, the m0×256 bits in the fifth bit set are distributed as 32 rows and m0×8 columns, the m0×8 bits in the r1th row in the fifth bit set come from the m0×8 bits in the r0th row in the fourth bit set, where 0≤r0<32, 0≤r1<32.

38. The method according to claim 37, wherein r0＝r1。 39. The method according to claim 19 or 20, characterized in that The fourth bit set includes m0 first bit subsets, where m0=12 or 16.

40. The method according to claim 33, wherein After performing the first interleaving process on the fourth bit set to obtain a fifth bit set, the method further includes: Performing a second interleaving process on every two first bit streams among the L first bit streams to obtain a total of L / 2 second bit streams, each of the first bit streams including a plurality of the fifth bit sets, where L is an even number greater than 0; Performing symbol mapping and polarization division on the L / 2 second bit streams to obtain a dual-polarization symbol stream, wherein the symbol mapping and the polarization division map t bits into one dual-polarization symbol, where t is an integer greater than 0; Digital signal processing (DSP) is performed on the dual-polarization symbol stream to form a frame.

41. The method according to claim 40, wherein The amplitude bits in the dual-polarization symbol are from the second bit set.

42. The method according to claim 41, wherein t=8, the dual-polarization symbol is a dual-polarization DP-16QAM symbol.

43. The method according to claim 42, wherein Performing DSP framing on the dual-polarization symbol stream includes: Every 172032 dual-polarization DP-16QAM symbols are framed to obtain a DSP superframe, where the superframe contains 175104 dual-polarization symbols.

44. The method according to claim 43, wherein Obtaining the first data from the data frame includes: Get F from the data frame Frame The first data to get F Frame ×r×q bits, F Frame is an integer greater than 0; d scr ×F Frame =336×k×F DSP ; Among them, F DSP Indicates the number of DSP superframes, F DSP A DSP superframe consists of F Frame The first data is processed and F DSP An integer greater than 0.

45. The method according to claim 44, wherein F DSP >1, the F DSP A plurality of consecutive symbols in the first DSP superframe in the DSP superframe is a first identifier, and the F DSP A plurality of consecutive symbols in each DSP superframe in the DSP superframes except the first DSP superframe are the second identifiers.

46. ​​A data processing method, characterized in that: include: Performing a first probabilistic constellation shaping (PCS) process on a first bit set in the first group of k bits to obtain a second bit set, where the second bit set includes m0×128 bits, where k is an integer greater than 1, and m0 is an integer greater than 1; performing a first forward error correction (FEC) encoding on the second bit set and a third bit set excluding the first bit set in the first group of k bits to obtain a fourth bit set, where the fourth bit set includes m0 first bit square matrices, each of which includes 256 bits distributed in 16 rows and 16 columns; performing a second PCS process on a fifth bit set in the second group of k bits to obtain a sixth bit set; performing a second FEC encoding on the sixth bit set and a seventh bit set excluding the fifth bit set in the second group of k bits to obtain an eighth bit set, where the eighth bit set includes m0 second bit square matrices, each of which includes 256 bits distributed in 16 rows and 16 columns; Inputting the 21 fourth bit sets and the 21 eighth bit sets into an interleaving buffer, wherein the interleaving buffer includes 84×m1 cache units distributed as 84 rows and m1 columns, where m0=m1×2, and each cache unit is used to cache 16 rows and 16 columns, totaling 256 bits. 42×m1 first bit matrices are input into the even rows of the interleaving buffer, and 42×m1 second bit matrices are input into the odd rows of the interleaving buffer. The interleaving buffer includes a first cache subset and a second cache subset, the first cache subset includes 42×m1 cache units, and the second cache subset includes 42×m1 cache units. The bits input into the first cache subset come from the second bit set and the sixth bit set, and the bits input into the second cache subset come from the third bit set, the seventh bit set, parity bits of the first FEC code, and parity bits of the second FEC code. Symbol mapping and polarization division are performed on every 8 bits in the interleaved buffer to obtain a dual-polarization DP-16QAM symbol, where 2 amplitude bits of the 4 bits corresponding to the 16QAM symbol of the DP-16QAM symbol in the target polarization direction come from a column in the first cache unit of the first cache subset, and 2 sign bits of the 4 bits corresponding to the 16QAM symbol of the DP-16QAM symbol in the target polarization direction come from a column in the second cache unit of the second cache subset.

47. The method according to claim 46, wherein Four of the eight bits come from a column of a first cache unit in the first cache subset, and the other four of the eight bits come from a column of a second cache unit in the second cache subset.

48. The method according to claim 46 or 47, characterized in that The m0 first bit matrixes are distributed into 2 rows and m1 columns, wherein the first bit matrix in the 0th row and the m2th column and the first bit matrix in the 1st row and the m2th column are from the second bit set, and the m0 second bit matrixes are distributed into 2 rows and m1 columns, wherein the second bit matrix in the 0th row and the m2th column and the second bit matrix in the 1st row and the m2th column are from the sixth bit set, 0≤m2<m1 / 2.

49. The method according to claim 48, characterized in that m0=16, the first cache subset includes 336 cache units in columns 0, 1, 2, and 3 of the interleaved cache, and the second cache subset includes 336 cache units in columns 4, 5, 6, and 7 of the interleaved cache. Alternatively, m0=12, the first cache subset includes a total of 252 cache units in columns 0, 1, and 2 of the interleaved cache, and the second cache subset includes a total of 252 cache units in columns 3, 4, and 5 of the interleaved cache.

50. The method according to claim 46 or 47, characterized in that m0=16,m1=8; The m0 first bit squares are distributed into 2 rows and m1 columns, and the first bit square at row 0 and column 0, the first bit square at row 0 and column 1, the first bit square at row 0 and column 4, the first bit square at row 0 and column 5, the first bit square at row 1 and column 0, the first bit square at row 1 and column 1, the first bit square at row 1 and column 4, and the first bit square at row 1 and column 5 are from the second bit set; The m0 second bit matrixes are distributed into 2 rows and m1 columns, and the second bit matrix in row 0 and column 0, the second bit matrix in row 0 and column 1, the second bit matrix in row 0 and column 4, the second bit matrix in row 0 and column 5, the second bit matrix in row 1 and column 0, the second bit matrix in row 1 and column 1, the second bit matrix in row 1 and column 4, and the second bit matrix in row 1 and column 5 are from the sixth bit set.

51. The method according to claim 50, characterized in that The first cache subset includes 336 cache units in columns 0, 1, 4, and 5 of the interleaved cache, and the second cache subset includes 336 cache units in columns 2, 3, 6, and 7 of the interleaved cache.

52. A data processing device, characterized in that: include: Probabilistic constellation shaping PCS unit, forward error correction FEC encoding unit and first interleaving processing unit; The PCS unit is configured to: perform PCS processing on a first bit set of k bits to obtain a second bit set, where k is an integer greater than 1; The FEC unit is configured to: perform FEC encoding on the second bit set and a third bit set of the k bits excluding the first bit set to obtain a fourth bit set, where the fourth bit set includes m0 first bit subsets, each of the first bit subsets includes F0 bits, where m0 is an integer greater than 1, and F0 is an even number greater than 1; The first interleaving processing unit is used to: perform a first interleaving process on the fourth bit set to obtain a fifth bit set, where the fifth bit set includes m0 second bit subsets, each second bit subset includes F0 bits, F0 / 2 bits in each second bit subset come from the second bit set, and the other F0 / 2 bits in each second bit subset come from the third bit set and / or the FEC encoded check bits.

53. The data processing device according to claim 52, characterized in that The fifth bit set includes m0×F0 bits, and each of the second bit subsets includes consecutive F0 bits.

54. The data processing device according to claim 52, characterized in that Each of the second bit subsets is presented as a square matrix.

55. The data processing device according to any one of claims 52 to 54, characterized in that The F0 bits in each of the second bit subsets are distributed as F1 rows and F1 columns, F1 / 2 bits of the F1 bits in each row of the second bit subset come from the second bit set, the second bit set includes m0×F0 / 2 bits, and the other F1 / 2 bits of the F1 bits in each row of the second bit subset come from the third bit set and / or the check bits of the FEC code.

56. The data processing device according to claim 55, characterized in that F0=256, F1=16.

57. The data processing device according to claim 55, characterized in that F0=256, F1=16, the second bit subset has the i2th row and the The bits of the column are from the second bit set, 0≤i2<16, 0≤j2<8; Alternatively, the bit in the i2th row and the (j2×2-i2%2+1)th column in the second bit subset is from the second bit set, 0≤i2<16, 0≤j2<8; in, means rounding a down to the nearest integer, and b%c means taking the modulus of b to c.

58. The data processing device according to claim 55, characterized in that F0=256, F1=16, and the bits in the second bit subset satisfy one or more of the following: The bits in row 0 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 1 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 2 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in row 3 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; The bits in row 4 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 5 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 6 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in row 7 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; The bits in row 8 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 9 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 10 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in row 11 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; The bits in row 12 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 13 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 14 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in the 15th row and the 1st, 2nd, 5th, 6th, 9th, 10th, 13th and 14th columns in the second bit subset are from the second bit set.

59. The data processing device according to any one of claims 52 to 54, characterized in that F0=256, m1 of the first bit subsets in the fourth bit set, a total of m1×256 bits, come from the second bit set, and m0=m1×2.

60. The data processing device according to any one of claims 52 to 54, characterized in that F0=256, the m0×256 bits in the fourth bit set are distributed as 32 rows and m0×8 columns, the m0×256 bits in the fifth bit set are distributed as 32 rows and m0×8 columns, the m0×8 bits in the r1-th row in the fifth bit set come from the m0×8 bits in the r0-th row in the fourth bit set, where 0≤r0<32, 0≤r1<32.

61. The data processing device according to any one of claims 52 to 54, characterized in that The data processing device further includes a pre-coding interleaving unit; The pre-coding interleaving unit is configured to: perform pre-coding interleaving on the second bit set and the third bit set to obtain a sixth bit set, where the number of bits in the sixth bit set is equal to the sum of the number of bits in the second bit set and the number of bits in the third bit set, the sixth bit set includes m3 third bit subsets, the m3 third bit subsets are distributed in 2 rows and m4 columns, m3=2×m4, m3 is an integer greater than 1 and less than m0, each third bit subset in a part of the third bit subsets includes F0 bits, and each third bit subset in another part of the third bit subsets includes F2 bits, where F2 is an even number greater than 1 and less than F0; The FEC unit is configured to perform FEC encoding on the sixth bit set to obtain the fourth bit set.

62. The data processing device according to claim 61, characterized in that m3=14, m4=7, F0=256, F2=240, each third bit subset of columns 0 to 5 includes 16 rows and 16 columns of bits, each third bit subset of column 6 includes 16 rows and 15 columns of bits, F0 / 2 bits in each third bit subset of columns 0 to 4 come from the second bit set, and another F0 / 2 bits in each third bit subset of columns 0 to 4 come from the third bit set, 9 bits in each row of each third bit subset of column 5 come from the second bit set, and another 7 bits in each row of each third bit subset of column 5 come from the third bit set, and F2 bits in each third bit subset of column 6 come from the second bit set.

63. The data processing device according to claim 60, characterized in that r0＝r1。 64. The data processing device according to any one of claims 52 to 54, characterized in that: m0=12 or 16.

65. The data processing device according to any one of claims 52 to 54, characterized in that The data processing device further includes a second interleaving processing unit, a symbol mapping unit, a polarization division unit and a digital signal processing (DSP) framing unit; The second interleaving processing unit is configured to perform a second interleaving process on every two first bit streams in the L first bit streams to obtain a total of L / 2 second bit streams, each of the first bit streams including a plurality of the fifth bit sets, where L is an even number greater than 0; The symbol mapping unit and the polarization division unit are used to perform symbol mapping and polarization division on L / 2 second bit streams to obtain a dual-polarization symbol stream, wherein the symbol mapping and the polarization division map t bits into one dual-polarization symbol, where t is an integer greater than 0; The DSP framing unit is configured to perform DSP framing on the dual-polarization symbol stream.

66. The data processing device according to claim 65, characterized in that The amplitude bits in the dual-polarization symbol are from the second bit set.

67. The data processing device according to claim 66, characterized in that t=8, the dual-polarization symbol is a dual-polarization DP-16QAM symbol.

68. The data processing device according to claim 67, characterized in that The DSP framing unit is specifically configured to perform framing processing on every 172032 dual-polarization DP-16QAM symbols to obtain a DSP superframe, where the superframe contains 175104 dual-polarization symbols.

69. The data processing device according to any one of claims 52 to 54, characterized in that The number of bits in the first bit set is an integer multiple of 2, 4, 8, or 16, the second bit set includes 2048 bits, the third bit set includes 1504 bits, and the fourth bit set includes 4096 bits.

70. A data processing device, characterized in that: include: A first processing unit, a second processing unit, a scrambling unit, a third processing unit, a probabilistic constellation shaping PCS unit and a forward error correction FEC encoding unit; The first processing unit is configured to: obtain first data from a data frame, where the first data includes r rows and q columns of bits, where r is an integer greater than 0, and q is an integer greater than 0; The second processing unit is used to: perform a cyclic redundancy check CRC on the first data and / or insert padding bits to obtain second data, wherein the second data includes d CRC parity bits and / or d PAD Filling bits, d CRC is an integer greater than or equal to 0, d PAD is an integer greater than or equal to 0; The scrambling unit is used to scramble the second data to obtain third data, the number of bits of the third data is d scr =r×q+d CP , d CP =d CRC +d PAD ; The third processing unit is used to obtain k bits of the third data, where k is an integer greater than 1, and d scr is an integer multiple of k; The PCS unit is configured to: perform PCS processing on a first bit set of k bits to obtain a second bit set; The FEC unit is configured to perform FEC encoding on the second bit set and a third bit set of the k bits excluding the first bit set to obtain a fourth bit set.

71. The data processing device according to claim 70, characterized in that The fourth bit set includes m0 first bit subsets, each of the first bit subsets includes F0 bits, m0 is an integer greater than 1, and F0 is an even number greater than 1. The data processing apparatus further includes a pre-coding interleaving unit, the pre-coding interleaving unit being configured to: Performing pre-coding interleaving processing on the second bit set and the third bit set to obtain a sixth bit set, where the number of bits in the sixth bit set is equal to the sum of the number of bits in the second bit set and the number of bits in the third bit set, the sixth bit set including m3 third bit subsets, the m3 third bit subsets being distributed in 2 rows and m4 columns, where m3=2×m4, m3 is an integer greater than 1 and less than m0, each third bit subset in some of the third bit subsets including F0 bits, and each third bit subset in another part of the third bit subsets including F2 bits, where F2 is an even number greater than 1 and less than F0; The FEC unit is configured to perform FEC encoding on the sixth bit set to obtain the fourth bit set.

72. The data processing device according to claim 70 or 71, characterized in that The number of bits in the first bit set is an integer multiple of 2, 4, 8, or 16, the second bit set includes 2048 bits, the third bit set includes 1504 bits, and the fourth bit set includes 4096 bits.

73. The data processing device according to claim 70 or 71, characterized in that d scr It is an integer multiple of 4×k, q=10280.

74. The data processing device according to claim 70 or 71, characterized in that r=79,d CP =328,k=3224; Or, r = 83, d CP =32, k=3386; Or, r = 83, d CP =536, k=3388; Or, r = 87, d CP =72, k=2662; Or, r = 87, d CP =744, k=2664; Or, r = 87, d CP =3432, k=2672; Or, r = 104, d CP =704, k=3184; Or, r = 104, d CP =3392, k=3192; Or, r = 105, d CP =504, k=3214; Or, r = 105, d CP =1176, k=3216; Or, r = 109, d CP =40, k=2668; Or, r = 109, d CP =880, k=2670; Or, r = 110, d CP =176, k=3366; Or, r = 110, d CP =848, k=3368; Or, r = 110, d CP =3536, k=3376; Or, r = 111, d CP =648, k=3398; Or, r = 131, d CP =8, k=2672; Or, r = 131, d CP =1016, k=2674; Or, r = 131, d CP =680, k=3208; Or, r = 132, d CP =480, k=3232; Or, r = 132, d CP =1320, k=3234; Or, r = 137, d CP =320, k=3354; Or, r = 137, d CP =1160, k=3356; Or, r = 138, d CP =120, k=3378; Or, r = 138, d CP =960, k=3380; Or, r = 152, d CP =344, k=2658; Or, r = 152, d CP =1520, k=2660; Or, r = 153, d CP =648, k=2676; Or, r = 157, d CP =856, k=3204; Or, r = 158, d CP =656, k=3224; Or, r = 165, d CP =264, k=3366; Or, r = 165, d CP =1272, k=3368; Or, r = 166, d CP =64, k=3386; Or, r = 166, d CP =1072, k=3388; Or, r = 174, d CP =144, k=2662; Or, r = 174, d CP =1488, k=2664; Or, r = 175, d CP =616, k=2678; Or, r = 183, d CP =360, k=3200; Or, r = 183, d CP =1536, k=3202; Or, r = 184, d CP =664, k=3218; Or, r = 184, d CP =1840, k=3220; Or, r = 185, d CP =968, k=3236; Or, r = 192, d CP =744, k=3358; Or, r = 192, d CP =1920, k=3360; Or, r = 193, d CP =1048, k=3376; Or, r = 194, d CP =176, k=3392; Or, r = 194, d CP =1352, k=3394; Or, r = 196, d CP =616, k=2666; Or, r = 209, d CP =536, k=3198; Or, r = 209, d CP =1880, k=3200; Or, r = 210, d CP =1008, k=3214; Or, r = 211, d CP =136, k=3228; Or, r = 211, d CP =1480, k=3230; Or, r = 217, d CP =280, k=2656; Or, r = 217, d CP =1960, k=2658; Or, r = 218, d CP =80, k=2668; Or, r = 218, d CP =1760, k=2670; Or, r = 219, d CP =1224, k=3352; Or, r = 220, d CP =352, k=3366; Or, r = 220, d CP =1696, k=3368; Or, r = 221, d CP =824, k=3382; Or, r = 221, d CP =2168, k=3384; Or, r = 222, d CP =1296, k=3398; Or, r = 235, d CP =376, k=3196; Or, r = 235, d CP =1888, k=3198; Or, r = 236, d CP =680, k=3210; Or, r = 236, d CP =2192, k=3212; Or, r = 237, d CP =984, k=3224; Or, r = 238, d CP =1288, k=3238; Or, r = 239, d CP =920, k=2660; Or, r = 240, d CP =1728, k=2672; Or, r = 247, d CP =1000, k=3360; Or, r = 247, d CP =2512, k=3362; Or, r = 248, d CP =1304, k=3374; Or, r = 249, d CP =96, k=3386; Or, r = 249, d CP =1608, k=3388; Or, r = 250, d CP =400, k=3400; Or, r = 250, d CP =1912, k=3402; Or, r = 261, d CP =216, k=2662; Or, r = 261, d CP =2232, k=2664; Or, r = 261, d CP =1560, k=3196; Or, r = 262, d CP =16, k=2672; Or, r = 262, d CP =2032, k=2674; Or, r = 262, d CP =1360, k=3208; Or, r = 263, d CP =1160, k=3220; Or, r = 264, d CP =960, k=3232; Or, r = 264, d CP =2640, k=3234; Or, r = 274, d CP =640, k=3354; Or, r = 274, d CP =2320, k=3356; Or, r = 275, d CP =440, k=3366; Or, r = 275, d CP =2120, k=3368; Or, r = 276, d CP =240, k=3378; Or, r = 276, d CP =1920, k=3380; Or, r = 277, d CP =40, k=3390; Or, r = 277, d CP =1720, k=3392; Or, r = 283, d CP =2032, k=2666; Or, r = 284, d CP =488, k=2674; Or, r = 284, d CP =2672, k=2676; Or, r = 287, d CP =896, k=3194; Or, r = 287, d CP =2744, k=3196; Or, r = 288, d CP =1704, k=3206; Or, r = 289, d CP =664, k=3216; Or, r = 289, d CP =2512, k=3218; Or, r = 290, d CP =1472, k=3228; Or, r = 291, d CP =432, k=3238; Or, r = 291, d CP =2280, k=3240; Or, r = 302, d CP =80, k=3360; Or, r = 302, d CP =1928, k=3362; Or, r = 303, d CP =888, k=3372; Or, r = 303, d CP =2736, k=3374; Or, r = 304, d CP =688, k=2658; Or, r = 304, d CP =3040, k=2660; Or, r = 304, d CP =1696, k=3384; Or, r = 305, d CP =2168, k=2668; Or, r = 305, d CP =656, k=3394; Or, r = 305, d CP =2504, k=3396; Or, r = 306, d CP =1296, k=2676; Or, r = 313, d CP =1912, k=3194; Or, r = 314, d CP =1712, k=3204; Or, r = 315, d CP =1512, k=3214; Or, r = 316, d CP =1312, k=3224; Or, r = 317, d CP =1112, k=3234; Or, r = 317, d CP =3128, k=3236; Or, r = 326, d CP =320, k=2660; Or, r = 326, d CP =2840, k=2662; Or, r = 327, d CP =120, k=2668; Or, r = 327, d CP =2640, k=2670; Or, r = 328, d CP =2440, k=2678; Or, r = 329, d CP =728, k=3356; Or, r = 329, d CP =2744, k=3358; Or, r = 330, d CP =528, k=3366; Or, r = 330, d CP =2544, k=3368; Or, r = 331, d CP =328, k=3376; Or, r = 331, d CP =2344, k=3378; Or, r = 332, d CP =128, k=3386; Or, r = 332, d CP =2144, k=3388; Or, r = 333, d CP =1944, k=3398; Or, r = 339, d CP =744, k=3192; Or, r = 339, d CP =2928, k=3194; Or, r = 340, d CP =1384, k=3202; Or, r = 341, d CP =2024, k=3212; Or, r = 342, d CP =480, k=3220; Or, r = 342, d CP =2664, k=3222; Or, r = 343, d CP =1120, k=3230; Or, r = 343, d CP =3304, k=3232; Or, r = 344, d CP =1760, k=3240; Or, r = 348, d CP =288, k=2662; Or, r = 348, d CP =2976, k=2664; Or, r = 349, d CP =760, k=2670; Or, r = 349, d CP =3448, k=2672; Or, r = 350, d CP =1232, k=2678; Or, r = 356, d CP =704, k=3352; Or, r = 356, d CP =2888, k=3354; Or, r = 357, d CP =1344, k=3362; Or, r = 357, d CP =3528, k=3364; Or, r = 358, d CP =1984, k=3372; Or, r = 359, d CP =440, k=3380; Or, r = 359, d CP =2624, k=3382; Or, r = 360, d CP =1080, k=3390; Or, r = 360, d CP =3264, k=3392; Or, r = 361, d CP =1720, k=3400; Or, r = 365, d CP =1592, k=3192; Or, r = 366, d CP =720, k=3200; Or, r = 366, d CP =3072, k=3202; Or, r = 367, d CP =2200, k=3210; Or, r = 368, d CP =1328, k=3218; Or, r = 368, d CP =3680, k=3220; Or, r = 369, d CP =2304, k=2658; Or, r = 369, d CP =456, k=3226; Or, r = 369, d CP =2808, k=3228; Or, r = 370, d CP =592, k=2664; Or, r = 370, d CP =3448, k=2666; Or, r = 370, d CP =1936, k=3236; Or, r = 371, d CP =1736, k=2672; Or, r = 384, d CP =1488, k=3358; Or, r = 384, d CP =3840, k=3360; Or, r = 385, d CP =616, k=3366; Or, r = 385, d CP =2968, k=3368; Or, r = 386, d CP =2096, k=3376; Or, r = 387, d CP =1224, k=3384; Or, r = 387, d CP =3576, k=3386; Or, r = 388, d CP =352, k=3392; Or, r = 388, d CP =2704, k=3394; Or, r = 389, d CP =1832, k=3402; Or, r = 391, d CP =2440, k=2660; Or, r = 392, d CP =1232, k=2666; Or, r = 392, d CP =2240, k=3200; Or, r = 393, d CP =24, k=2672; Or, r = 393, d CP =3048, k=2674; Or, r = 393, d CP =2040, k=3208; Or, r = 394, d CP =1840, k=3216; Or, r = 395, d CP =1640, k=3224; Or, r = 396, d CP =1440, k=3232; Or, r = 396, d CP =3960, k=3234; Or, r = 397, d CP =1240, k=3240; Or, r = 397, d CP =3760, k=3242; Or, r = 411, d CP =960, k=3354; Or, r = 411, d CP =3480, k=3356; Or, r = 412, d CP =760, k=3362; Or, r = 412, d CP =3280, k=3364; Or, r = 413, d CP =2912, k=2662; Or, r = 413, d CP =560, k=3370; Or, r = 413, d CP =3080, k=3372; Or, r = 414, d CP =2208, k=2668; Or, r = 414, d CP =360, k=3378; Or, r = 414, d CP =2880, k=3380; Or, r = 415, d CP =1504, k=2674; Or, r = 415, d CP =160, k=3386; Or, r = 415, d CP =2680, k=3388; Or, r = 416, d CP =2480, k=3396; Or, r = 418, d CP =1072, k=3198; Or, r = 418, d CP =3760, k=3200; Or, r = 419, d CP =1544, k=3206; Or, r = 419, d CP =4232, k=3208; Or, r = 420, d CP =2016, k=3214; Or, r = 421, d CP =2488, k=3222; Or, r = 422, d CP =272, k=3228; Or, r = 422, d CP =2960, k=3230; Or, r = 423, d CP =744, k=3236; Or, r = 423, d CP =3432, k=3238; Or, r = 434, d CP =560, k=2656; Or, r = 434, d CP =3920, k=2658; Or, r = 435, d CP =360, k=2662; Or, r = 435, d CP =3720, k=2664; Or, r = 436, d CP =160, k=2668; Or, r = 436, d CP =3520, k=2670; Or, r = 437, d CP =3320, k=2676; Or, r = 438, d CP =2448, k=3352; Or, r = 439, d CP =232, k=3358; Or, r = 439, d CP =2920, k=3360; Or, r = 440, d CP =704, k=3366; Or, r = 440, d CP =3392, k=3368; Or, r = 441, d CP =1176, k=3374; Or, r = 441, d CP =3864, k=3376; Or, r = 442, d CP =1648, k=3382; Or, r = 442, d CP =4336, k=3384; Or, r = 443, d CP =2120, k=3390; Or, r = 444, d CP =2424, k=3198; Or, r = 444, d CP =2592, k=3398; Or, r = 445, d CP =712, k=3204; Or, r = 445, d CP =3568, k=3206; Or, r = 446, d CP =1856, k=3212; Or, r = 447, d CP =144, k=3218; Or, r = 447, d CP =3000, k=3220; Or, r = 448, d CP =1288, k=3226; Or, r = 448, d CP =4144, k=3228; Or, r = 449, d CP =2432, k=3234; Or, r = 456, d CP =1032, k=2658; Or, r = 456, d CP =4560, k=2660; Or, r = 457, d CP =1336, k=2664; Or, r = 458, d CP =1640, k=2670; Or, r = 459, d CP =1944, k=2676; Or, r = 466, d CP =1888, k=3356; Or, r = 466, d CP =4744, k=3358; Or, r = 467, d CP =176, k=3362; Or, r = 467, d CP =3032, k=3364; Or, r = 468, d CP =1320, k=3370; Or, r = 468, d CP =4176, k=3372; Or, r = 469, d CP =2464, k=3378; Or, r = 470, d CP =752, k=3196; Or, r = 470, d CP =3776, k=3198; Or, r = 470, d CP =752, k=3384; Or, r = 470, d CP =3608, k=3386; Or, r = 471, d CP =2568, k=3204; Or, r = 471, d CP =1896, k=3392; Or, r = 471, d CP =4752, k=3394; Or, r = 472, d CP =1360, k=3210; Or, r = 472, d CP =4384, k=3212; Or, r = 472, d CP =184, k=3398; Or, r = 472, d CP =3040, k=3400; Or, r = 473, d CP =152, k=3216; Or, r = 473, d CP =3176, k=3218; Or, r = 474, d CP =1968, k=3224; Or, r = 475, d CP =760, k=3230; Or, r = 475, d CP =3784, k=3232; Or, r = 476, d CP =2576, k=3238; Or, r = 478, d CP =1840, k=2660; Or, r = 479, d CP =2648, k=2666; Or, r = 480, d CP =3456, k=2672; Or, r = 481, d CP =568, k=2676; Or, r = 481, d CP =4264, k=2678; Or, r = 493, d CP =184, k=3352; Or, r = 493, d CP =3208, k=3354; Or, r = 494, d CP =2000, k=3360; Or, r = 494, d CP =5024, k=3362; Or, r = 495, d CP =792, k=3366; Or, r = 495, d CP =3816, k=3368; Or, r = 496, d CP =1936, k=3196; Or, r = 496, d CP =2608, k=3374; Or, r = 497, d CP =1232, k=3202; Or, r = 497, d CP =4424, k=3204; Or, r = 497, d CP =1400, k=3380; Or, r = 497, d CP =4424, k=3382; Or, r = 498, d CP =528, k=3208; Or, r = 498, d CP =3720, k=3210; Or, r = 498, d CP =192, k=3386; Or, r = 498, d CP =3216, k=3388; Or, r = 499, d CP =1672, k=2656; Or, r = 499, d CP =3016, k=3216; Or, r = 499, d CP =2008, k=3394; Or, r = 499, d CP =5032, k=3396; Or, r = 500, d CP =2984, k=2662; Or, r = 500, d CP =2312, k=3222; Or, r = 500, d CP =800, k=3400; Or, r = 500, d CP =3824, k=3402; Or, r = 501, d CP =432, k=2666; Or, r = 501, d CP =4296, k=2668; Or, r = 501, d CP =1608, k=3228; Or, r = 501, d CP =4800, k=3230; Or, r = 502, d CP =1744, k=2672; Or, r = 502, d CP =904, k=3234; Or, r = 502, d CP =4096, k=3236; Or, r = 503, d CP =3056, k=2678.

75. The data processing device according to claim 70 or 71, characterized in that d scr =336×k。 76. The data processing device according to claim 70 or 71, characterized in that The second data processing unit is specifically configured to: Perform CRC-32 check on a total of r×q / p bits in each r / p rows of the first data to add a check bit with a length of 32 bits, d CRC =32×p, r is divisible by p, and p is an integer greater than 1; or, For the first r in the first data F0 ×(p-1) rows of each r F0 Rows total q×r F0 The CRC-32 check is performed on the first data to add a check bit with a length of 32 bits, and the last r F1 Rows total q×r F1 bits to perform CRC-32 check to add a check bit with a length of 32 bits, where d CRC =32×p, r cannot be divided by p, p is an integer greater than 1, r F0 ×(p-1)+r F1 =r, integer r F0 Greater than integer r F1 .

77. The data processing device according to claim 70 or 71, characterized in that q＝2056。 78. The data processing device according to claim 77, characterized in that The second data processing unit is specifically configured to: For the first r in the first data F0 ×(p-1) rows of each r F0 Rows total q×r F0 The CRC-32 check is performed on the first data to add a check bit with a length of 32 bits, and the last r F1 Rows total q×r F1 bits to perform CRC-32 check to add a check bit with a length of 32 bits, where d CRC =32×p, r cannot be divided by p, p is an integer greater than 1, r F0 ×(p-1)+r F1 =r, integer r F0 Greater than integer r F1 .

79. The data processing device according to claim 77, characterized in that r＝435。 80. The data processing device according to claim 79, characterized in that p=22, r F0 =20, r F1 =15, the second data processing unit is specifically configured to: A CRC-32 check is performed on each of the first 420 lines, totaling 41,120 bits, in the first data to add a check bit with a length of 32 bits, and a CRC-32 check is performed on the last 15 lines, totaling 30,840 bits, in the first data to add a check bit with a length of 32 bits.

81. The data processing device according to claim 79, characterized in that d CP =3432, k=2672, or, d CP =744, k=2664.

82. The data processing device according to claim 77, characterized in that r=546,d CP =1008,k=3344; Or, r = 546, d CP =3696, k=3352; Or, r = 547, d CP =1640, k=3352; Or, r = 547, d CP =4328, k=3360; Or, r = 548, d CP =2272, k=3360; Or, r = 548, d CP =4960, k=3368; Or, r = 549, d CP =216, k=3360; Or, r = 549, d CP =2904, k=3368; Or, r = 549, d CP =5592, k=3376; Or, r = 550, d CP =848, k=3368; Or, r = 550, d CP =3536, k=3376; Or, r = 551, d CP =1480, k=3376; Or, r = 551, d CP =4168, k=3384; Or, r = 552, d CP =2112, k=3384; Or, r = 552, d CP =4800, k=3392; Or, r = 553, d CP =56, k=3384; Or, r = 553, d CP =2744, k=3392; Or, r = 553, d CP =5432, k=3400; Or, r = 554, d CP =688, k=3392; Or, r = 554, d CP =3376, k=3400; Or, r = 555, d CP =1320, k=3400; Or, r = 555, d CP =4008, k=3408; Or, r = 556, d CP =1952, k=3408; Or, r = 556, d CP =4640, k=3416; Or, r = 557, d CP =2584, k=3416; Or, r = 557, d CP =5272, k=3424; Or, r = 558, d CP =528, k=3416; Or, r = 558, d CP =3216, k=3424; Or, r = 559, d CP =1160, k=3424; Or, r = 559, d CP =3848, k=3432; Or, r = 560, d CP =1792, k=3432; Or, r = 560, d CP =4480, k=3440; Or, r = 561, d CP =2424, k=3440; Or, r = 561, d CP =5112, k=3448; Or, r = 562, d CP =368, k=3440; Or, r = 562, d CP =3056, k=3448; Or, r = 562, d CP =5744, k=3456.

83. The data processing device according to claim 77, characterized in that r=520,d CP =704, k=3184; or, r=520, d CP =3392, k=3192; Or, r = 520, d CP =6080, k=3200; Or, r = 521, d CP =1336, k=3192; Or, r = 521, d CP =4024, k=3200; Or, r = 522, d CP =1968, k=3200; Or, r = 522, d CP =4656, k=3208; Or, r = 523, d CP =2600, k=3208; Or, r = 523, d CP =5288, k=3216; Or, r = 524, d CP =544, k=3208; Or, r = 524, d CP =3232, k=3216; Or, r = 525, d CP =1176, k=3216; Or, r = 525, d CP =3864, k=3224; Or, r = 526, d CP =1808, k=3224; Or, r = 526, d CP =4496, k=3232; Or, r = 527, d CP =2440, k=3232; Or, r = 527, d CP =5128, k=3240; Or, r = 528, d CP =384, k=3232; Or, r = 528, d CP =3072, k=3240; Or, r = 528, d CP =5760, k=3248; Or, r = 529, d CP =1016, k=3240; Or, r = 529, d CP =3704, k=3248; Or, r = 530, d CP =1648, k=3248; Or, r = 530, d CP =4336, k=3256; Or, r = 531, d CP =2280, k=3256; Or, r = 531, d CP =4968, k=3264; Or, r = 532, d CP =2912, k=3264; Or, r = 532, d CP =224, k=3256; Or, r = 533, d CP =856, k=3264; Or, r = 533, d CP =3544, k=3272; Or, r = 534, d CP =1488, k=3272; Or, r = 534, d CP =4176, k=3280; Or, r = 535, d CP =2120, k=3280; Or, r = 535, d CP =4808, k=3288.

84. The data processing device according to claim 70 or 71, characterized in that The fourth bit set includes m0 first bit subsets, where m0 is an integer greater than 1, and the data processing device further includes a first interleaving unit; The first interleaving unit is used to: perform a first interleaving process on the fourth bit set to obtain a fifth bit set, where the fifth bit set includes m0 second bit subsets, each second bit subset includes 256 bits, 128 bits in each second bit subset come from the second bit set, and the other 128 bits in each second bit subset come from the third bit set and / or the FEC encoded check bits.

85. The data processing device according to claim 84, characterized in that Each of the second bit subsets includes 256 consecutive bits.

86. The data processing device according to claim 84, characterized in that Each of the second bit subsets is presented as a square matrix.

87. The data processing device according to claim 84, characterized in that The 256 bits of the second bit subset are distributed into 16 rows and 16 columns, and the bits in the second bit subset satisfy one or more of the following: The bits in row 0 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 1 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 2 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in row 3 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; The bits in row 4 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 5 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 6 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in row 7 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; The bits in row 8 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 9 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 10 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in row 11 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; The bits in row 12 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; The bits in row 13 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; The bits in row 14 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; The bits in the 15th row and the 1st, 2nd, 5th, 6th, 9th, 10th, 13th and 14th columns in the second bit subset are from the second bit set.

88. The data processing device according to claim 84, characterized in that The m0×256 bits in the fourth bit set are distributed as 32 rows and m0×8 columns, the m0×256 bits in the fifth bit set are distributed as 32 rows and m0×8 columns, the m0×8 bits in the r1th row in the fifth bit set come from the m0×8 bits in the r0th row in the fourth bit set, where 0≤r0<32, 0≤r1<32.

89. The data processing device according to claim 88, characterized in that r0＝r1。 90. The data processing device according to claim 70 or 71, characterized in that The fourth bit set includes m0 first bit subsets, where m0=12 or 16.

91. The data processing device according to claim 84, characterized in that The data processing device further comprises a second interleaving unit, a symbol mapping unit, a polarization division unit and a digital signal processing (DSP) framing unit; The second interleaving unit is configured to perform a second interleaving process on every two first bit streams in the L first bit streams to obtain a total of L / 2 second bit streams, each of the first bit streams including a plurality of the fifth bit sets, where L is an even number greater than 0; The symbol mapping unit and the polarization division unit are used to perform symbol mapping and polarization division on L / 2 second bit streams to obtain a dual-polarization symbol stream, wherein the symbol mapping and the polarization division map t bits into one dual-polarization symbol, where t is an integer greater than 0; The DSP framing unit is configured to perform DSP framing on the dual-polarization symbol stream.

92. The data processing device according to claim 91, characterized in that The amplitude bits in the dual-polarization symbol are from the second bit set.

93. The data processing device according to claim 92, characterized in that t=8, the dual-polarization symbol is a dual-polarization DP-16QAM symbol.

94. The data processing device according to claim 93, characterized in that The DSP framing unit is specifically configured to perform framing processing on every 172032 dual-polarization DP-16QAM symbols to obtain a DSP superframe, where the superframe contains 175104 dual-polarization symbols.

95. The data processing device according to claim 94, characterized in that The first processing unit is specifically configured to: obtain F from the data frame Frame The first data to get F Frame ×r×q bits, F Frame is an integer greater than 0; d scr ×F Frame =336×k×F DSP ; Among them, F DSP Indicates the number of DSP superframes, F DSP A DSP superframe consists of F Frame The first data is processed and F DSP An integer greater than 0.

96. The data processing device according to claim 95, characterized in that F DSP >1, the F DSP A plurality of consecutive symbols in the first DSP superframe in the DSP superframe is a first identifier, and the F DSP A plurality of consecutive symbols in each DSP superframe in the DSP superframes except the first DSP superframe are the second identifiers.

97. A data processing device, characterized in that: include: A first probabilistic constellation shaping PCS unit, a first forward error correction FEC encoding unit, a second PCS unit, a second FEC unit, an interleaving processing unit, a symbol mapping unit, and a polarization division unit; The first PCS unit is configured to: perform a first PCS process on a first bit set in the first group of k bits to obtain a second bit set, where the second bit set includes m0×128 bits, where k is an integer greater than 1, and m0 is an integer greater than 1; The first FEC encoding unit is configured to perform a first forward error correction (FEC) encoding on the second bit set and a third bit set in the first group of k bits excluding the first bit set to obtain a fourth bit set, where the fourth bit set includes m0 first bit square matrices, each of which includes 256 bits distributed in 16 rows and 16 columns. The second PCS unit is configured to: perform a second PCS process on a fifth bit set in the second group of k bits to obtain a sixth bit set; The second FEC encoding unit is configured to perform a second FEC encoding on the sixth bit set and a seventh bit set excluding the fifth bit set in the second group of k bits to obtain an eighth bit set, where the eighth bit set includes m0 second bit square matrices, each of which includes 256 bits distributed in 16 rows and 16 columns. The interleaving processing unit is configured to: input the 21 fourth bit sets and the 21 eighth bit sets into an interleaving buffer, wherein the interleaving buffer includes 84×m1 cache units distributed as 84 rows and m1 columns, where m0=m1×2, and each cache unit is used to cache 16 rows and 16 columns, totaling 256 bits. 42×m1 first bit matrices are input into even rows of the interleaving buffer, and 42×m1 second bit matrices are input into odd rows of the interleaving buffer. The interleaving buffer includes a first cache subset and a second cache subset, the first cache subset includes 42×m1 cache units, and the second cache subset includes 42×m1 cache units. The bits input into the first cache subset come from the second bit set and the sixth bit set, and the bits input into the second cache subset come from the third bit set, the seventh bit set, parity bits of the first FEC code, and parity bits of the second FEC code. The symbol mapping unit and the polarization division unit are used to perform symbol mapping and polarization division on every 8 bits in the interleaved buffer to obtain a dual-polarization DP-16QAM symbol, wherein 2 amplitude bits of the 4 bits corresponding to the 16QAM symbol of the DP-16QAM symbol in the target polarization direction come from a column of the first cache unit of the first cache subset, and 2 symbol bits of the 4 bits corresponding to the 16QAM symbol of the DP-16QAM symbol in the target polarization direction come from a column of the second cache unit of the second cache subset.

98. The data processing device according to claim 97, characterized in that Four of the eight bits come from a column of a first cache unit in the first cache subset, and the other four of the eight bits come from a column of a second cache unit in the second cache subset.

99. The data processing device according to claim 97 or 98, characterized in that The m0 first bit matrixes are distributed into 2 rows and m1 columns, wherein the first bit matrix in the 0th row and the m2th column and the first bit matrix in the 1st row and the m2th column are from the second bit set, and the m0 second bit matrixes are distributed into 2 rows and m1 columns, wherein the second bit matrix in the 0th row and the m2th column and the second bit matrix in the 1st row and the m2th column are from the sixth bit set, 0≤m2<m1 / 2.

100. The data processing device according to claim 99, characterized in that m0=16, the first cache subset includes 336 cache units in columns 0, 1, 2, and 3 of the interleaved cache, and the second cache subset includes 336 cache units in columns 4, 5, 6, and 7 of the interleaved cache. Alternatively, m0=12, the first cache subset includes a total of 252 cache units in columns 0, 1, and 2 of the interleaved cache, and the second cache subset includes a total of 252 cache units in columns 3, 4, and 5 of the interleaved cache.

101. The data processing device according to claim 97 or 98, characterized in that: m0=16,m1=8; The m0 first bit squares are distributed into 2 rows and m1 columns, and the first bit square at row 0 and column 0, the first bit square at row 0 and column 1, the first bit square at row 0 and column 4, the first bit square at row 0 and column 5, the first bit square at row 1 and column 0, the first bit square at row 1 and column 1, the first bit square at row 1 and column 4, and the first bit square at row 1 and column 5 are from the second bit set; The m0 second bit matrixes are distributed into 2 rows and m1 columns, and the second bit matrix in row 0 and column 0, the second bit matrix in row 0 and column 1, the second bit matrix in row 0 and column 4, the second bit matrix in row 0 and column 5, the second bit matrix in row 1 and column 0, the second bit matrix in row 1 and column 1, the second bit matrix in row 1 and column 4, and the second bit matrix in row 1 and column 5 are from the sixth bit set.

102. The data processing device according to claim 101, characterized in that The first cache subset includes 336 cache units in columns 0, 1, 4, and 5 of the interleaved cache, and the second cache subset includes 336 cache units in columns 2, 3, 6, and 7 of the interleaved cache.

103. A data processing device, characterized in that: include: A processor and a transceiver, the processor is used to execute the method as described in any one of claims 1 to 51, and the transceiver is used to perform data transmission and reception operations.

104. A communication system, characterized in that include: A data processing device at the sending end and a data processing device at the receiving end, wherein the data processing device at the sending end is used to execute the method according to any one of claims 1 to 51, and the data processing device at the sending end is used to send a data stream to the data processing device at the receiving end.

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