Current measuring device of power semiconductor device test circuit and measuring method thereof

Abstract

The invention provides a current measuring device of a power semiconductor device test circuit and a measuring method thereof. The current measuring device comprises a multi-layer circuit board and a plurality of chip resistors, the multi-layer circuit board at least comprises a first circuit board and a second circuit board which are oppositely arranged, the multi-layer circuit board is provided with a plurality of first through holes penetrating through the multi-layer circuit board, and the at least two chip resistors are connected in parallel. Each chip resistor is embedded into each first through hole of the multilayer circuit board, each chip resistor comprises a first detection end and a second detection end which are oppositely arranged, and the current direction of the wire of the circuit to be detected connected to the first detection end is at least partially opposite to the current direction of the wire of the circuit to be detected connected to the second detection end; the first detection end and the second detection end are both used for being externally connected with a voltage measuring device. It is possible to provide a current measuring device with high bandwidth and low insertion inductance.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor device test circuits, and in particular to a current measuring device and a measuring method for a power semiconductor device test circuit. Background Art

[0002] The current measurement in the power semiconductor device test circuit requires a higher bandwidth and a smaller insertion inductance. However, the current measurement method using a coaxial current meter or a Rogowski coil in the related art cannot meet the requirements of high bandwidth and low insertion inductance. Summary of the invention

[0003] In view of the shortcomings of the related art, the present application proposes a current measuring device for a power semiconductor device test circuit, so as to solve the problems of low bandwidth and large insertion inductance of the current measuring device in the related art.

[0004] An embodiment of the present application provides a current measuring device for a power semiconductor device test circuit, the current measuring device comprising a multilayer circuit board and a plurality of chip resistors, wherein the multilayer circuit board comprises at least a first circuit board and a second circuit board arranged opposite to each other, the multilayer circuit board being provided with a plurality of first through holes penetrating the multilayer circuit board, the opening direction of the first through holes being parallel to the direction of the first circuit board pointing to the second circuit board. At least two of the chip resistors are connected in parallel, and each of the chip resistors is respectively embedded in each of the first through holes of the multilayer circuit board. Each of the chip resistors includes a first detection end and a second detection end that are relatively arranged. The first detection end is exposed at one end of the first through hole and is electrically connected to the circuit to be tested in the multilayer circuit board. The second detection end is exposed at the other end of the first through hole and is electrically connected to the circuit to be tested in the multilayer circuit board. The surface of the first circuit board facing the second circuit board is the inner surface. The orthographic projection of the wiring of the circuit to be tested connected to the first detection end on the inner surface is at least partially overlapped with the orthographic projection of the wiring of the circuit to be tested connected to the second detection end on the inner surface. The current direction of the wiring of the circuit to be tested connected to the first detection end is at least partially opposite to the current direction of the wiring of the circuit to be tested connected to the second detection end. Both the first detection end and the second detection end are used for an external voltage measuring device.

[0005] In one embodiment, the cross-sectional area of ​​the chip resistor on the inner surface is less than or equal to the cross-sectional area of ​​the first through hole on the inner surface, and the length of the chip resistor along the opening direction is less than or equal to the distance between a side of the first circuit board facing away from the second circuit board and a side of the second circuit board facing away from the first circuit board.

[0006] In one embodiment, the plurality of chip resistors include a first chip resistor group and a second chip resistor group that are spaced apart from each other, the first chip resistor group includes a plurality of first chip resistors, the second chip resistor group includes a plurality of second chip resistors, and each of the first chip resistors is connected in parallel with each of the second chip resistors in a one-to-one correspondence.

[0007] In one embodiment, the first detection end of the first chip resistor is electrically connected to the first detection end of the second chip resistor and is commonly electrically connected to a first electrical connection line, and the first electrical connection line is connected to the circuit to be tested in the multi-layer circuit board; the second detection end of the first chip resistor is electrically connected to the second detection end of the second chip resistor and is commonly electrically connected to a second electrical connection line, and the second electrical connection line is connected to the circuit to be tested in the multi-layer circuit board.

[0008] In one embodiment, the multilayer circuit board also includes a third circuit board and a fourth circuit board sequentially stacked on the first circuit board; the third circuit board and the fourth circuit board are located between the first circuit board and the second circuit board; the multilayer circuit board is also provided with a plurality of second through holes penetrating the multilayer circuit board, the opening direction of the second through holes is parallel to the direction of the first circuit board pointing to the second circuit board, the plurality of second through holes include a first sub-through hole group and a second sub-through hole group, the first sub-through hole group includes a plurality of first sub-through holes, the second sub-through hole group includes a plurality of second sub-through holes, the first electrical connection line sequentially passes through the first sub-through holes from the end connected to the first detection end to be electrically connected to at least part of the circuit to be tested located in the first circuit board; the second electrical connection line sequentially passes through the second sub-through holes from the end connected to the second detection end to be electrically connected to at least part of the circuit to be tested located in the second circuit board; wherein,

[0009] The third circuit board is connected to the second sub-through holes in the second sub-through hole group and is electrically connected to the second electrical connection line;

[0010] And / or, the fourth circuit board is communicated with the first sub-through hole in the first sub-through hole group and is electrically connected to the first electrical connection line.

[0011] In one embodiment, the direction of the current flowing through the wiring of at least part of the circuit to be tested located on the third circuit board is opposite to the direction of the current flowing through the wiring of at least part of the circuit to be tested located on the first circuit board; the direction of the current flowing through the wiring of at least part of the circuit to be tested located on the fourth circuit board is opposite to the direction of the current flowing through the wiring of at least part of the circuit to be tested located on the second circuit board.

[0012] In one embodiment, the first chip resistor group is arranged adjacent to the first sub-through hole group, the second chip resistor group is arranged on a side of the first sub-through hole group away from the first chip resistor group, and the second sub-through hole group is arranged on a side of the first chip resistor group away from the first through hole group.

[0013] In one embodiment, the direction of current flowing through any chip resistor in the first chip resistor group is the same as the direction of current flowing through any chip resistor in the second chip resistor group; the direction of current flowing through the first electrical connection line in any first sub-through hole group within the first sub-through hole group is opposite to the direction of current flowing through any chip resistor in the first chip resistor group, and the direction of current flowing through the second electrical connection line in any second sub-through hole group within the second sub-through hole group is opposite to the direction of current flowing through any chip resistor in the second chip resistor group.

[0014] In one embodiment, the direction of the current flowing through the first chip resistor group and the direction of the current flowing through the second chip resistor group are both in the direction from the first circuit board to the second circuit board; the direction of the current flowing through the first electrical connection line in any first sub-through hole located in the first sub-through hole group and the direction of the current flowing through the second electrical connection line in any second sub-through hole located in the second sub-through hole group are both in the direction from the second circuit board to the first circuit board.

[0015] In one embodiment, the direction of the current flowing through the first chip resistor group and the direction of the current flowing through the second chip resistor group are both in the direction from the second circuit board to the first circuit board; the direction of the current flowing through the first electrical connection line in any first sub-through hole located in the first sub-through hole group and the direction of the current flowing through the second electrical connection line in any second sub-through hole located in the second sub-through hole group are both in the direction from the first circuit board to the second circuit board.

[0016] In one embodiment, each first sub-through hole of the first sub-through hole group has a first opening end and a second opening end that are oppositely arranged, the first opening end is arranged on the second circuit board, and the second opening end is arranged on the first circuit board, and the end of the first electrical connection line close to the first detection end passes through the first opening end and the second opening end in sequence to be electrically connected to at least a portion of the circuit to be tested located in the first circuit board; each second sub-through hole of the second sub-through hole group has a third opening end and a fourth opening end that are oppositely arranged; the third opening end is arranged on the first circuit board, and the fourth opening end is arranged on the second circuit board, and the second electrical connection line passes through the third opening end and the fourth opening end in sequence to be electrically connected to at least a portion of the circuit to be tested located on the second circuit board.

[0017] This embodiment further provides a current measurement method for a power semiconductor device test circuit. Based on the above-mentioned current measurement device, the current measurement method includes:

[0018] When the circuit to be tested is powered on, a voltage signal between the first detection terminal and the second detection terminal is collected, and a current to be tested of the power semiconductor device test circuit is determined according to the voltage signal.

[0019] The beneficial effects of this application include:

[0020] In this embodiment, multiple patch resistors are embedded in a multilayer circuit board, and the multiple patch resistors are connected in parallel and in series to the circuit to be tested. By measuring the voltage signal between the first detection end and the second detection end of the patch resistor, the current of the circuit to be tested can be measured by conversion. When the patch resistors are connected in parallel, the current will be shunted in the parallel patch resistors, so the current intensity in each single resistor is relatively small, and the magnetic field intensity generated by the resistor is weak, and the resulting stray inductance effect will also be relatively weakened. In addition, when the patch resistors are connected in parallel, the current will be shunted between the patch resistors, and each patch resistor will bear a part of the current, so the total current that the entire circuit can carry can be increased, that is, the circuit current capacity is improved. Furthermore, compared with the method of directly soldering the chip resistors on the surface of the circuit board, the current direction of the wiring of the circuit to be tested connected to the first detection end is at least partially opposite to the current direction of the wiring of the circuit to be tested connected to the second detection end. According to Ampere's law, the current loop connected to the first detection end and the current loop connected to the second detection end can generate magnetic fields in opposite directions. These magnetic fields in opposite directions will cancel each other out, resulting in a weakening of the magnetic field strength in the area between the two current loops. Since stray inductance exists due to the magnetic field effect generated by the current, this weakening of the magnetic field strength will reduce the stray inductance. On the other hand, such a design of the wiring can shorten the physical length of the current loop to a certain extent, thereby reducing the stray inductance; since the chip resistor has a high-frequency bandwidth, it can provide accurate resistance values ​​within the high-frequency range, and the application range is less limited. Furthermore, compared with coaxial shunts and Rogowski coils, chip resistors are cheaper, so costs can also be reduced.

[0021] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0023] Figure 1Shown is a structural schematic diagram of a current measurement structure of a power semiconductor device test circuit in the related art;

[0024] Figure 2 Shown is a structural schematic diagram of a current measurement structure of a power semiconductor device test circuit in the related art;

[0025] Figure 3 Shown is a top view of a current measuring device of a power semiconductor device test circuit provided by an exemplary embodiment of the present application;

[0026] Figure 4 Shown Figure 3 The schematic cross-sectional structure diagram of the current measuring device shown along the section line AA;

[0027] Figure 5 Shown is a top view of a current measuring device of a power semiconductor device test circuit provided by an exemplary embodiment of the present application;

[0028] Figure 6 Shown Figure 5 A schematic cross-sectional structure diagram of the current measuring device shown along the section line BB;

[0029] Figure 7 Shown is a top view of a current measuring device of a power semiconductor device test circuit provided by an exemplary embodiment of the present application;

[0030] Figure 8 Shown Figure 7 The cross-sectional structure diagram of the current measuring device shown is along the cross-sectional line CC.

[0031] In the figure: 10-multilayer circuit board; 11-first circuit board; 12-second circuit board; 13-third circuit board; 14-fourth circuit board; 101-first through hole; 102-second through hole; 1021-first sub-through hole group; 1021a-first opening end; 1021b-second opening end; 1022-second sub-through hole group; 1022a-third opening end; 1022b-fourth opening end; 102a-first sub-through hole; 102b-second sub-through hole; 20-chip resistor; 21-first chip resistor group; 22-second chip resistor group; 20a-first chip resistor; 20b second chip resistor; 201-first detection end; 202-second detection end; 31-first electrical connection line; 32-second electrical connection line; 40-surface mount component. DETAILED DESCRIPTION

[0032] Research has found that in high-frequency circuits, excessive inductance can cause signal delay, attenuation, and distortion. At the same time, low bandwidth can limit the frequency range in which high-frequency circuits can work effectively. Low bandwidth can also affect the quality of signals during transmission, leading to signal distortion or attenuation due to frequency limitations. In related technologies, coaxial shunts or Rogowski coils are usually used to measure current in circuits. Specifically, Figure 1 As shown, a shunt resistor 1' (coaxial shunt) is connected in series in the circuit under test, and the voltage signal at both ends of the shunt resistor is measured and converted into current. Figure 2 As shown, the current is measured by the mutual inductance of the Rogowski coil 2'. Figure 1 In the solution, the coaxial shunt 1' is expensive, has a low safe operating temperature, which makes it impossible to perform high-temperature double pulse tests, and has a large insertion inductance. Figure 2 In the solution, the Rogowski coil 2' has low accuracy and low bandwidth in measuring current. Therefore, a current measuring device with high bandwidth and low insertion inductance is urgently needed.

[0033] The current measurement device and the measurement method of the power semiconductor device test circuit provided in the present application are intended to solve the above technical problems of the related art.

[0034] The current measuring device and the measuring method of the power semiconductor device test circuit in the embodiment of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the features in the following embodiments can complement or be combined with each other.

[0035] The present application embodiment provides a current measuring device for a power semiconductor device test circuit, such as Figure 3 and Figure 4As shown, the current measuring device includes a multilayer circuit board 10 and a plurality of chip resistors 20, wherein the multilayer circuit board 10 includes at least a first circuit board 11 and a second circuit board 12 arranged opposite to each other, and the multilayer circuit board 10 is provided with a plurality of first through holes 101 penetrating the multilayer circuit board 10, and the opening direction of the first through holes 101 is parallel to the direction of the first circuit board 11 pointing to the second circuit board 12. At least two of the chip resistors 20 are connected in parallel, and each of the chip resistors 20 is respectively embedded in each of the first through holes 101 of the multilayer circuit board 10. Each of the chip resistors 20 includes a first detection end 201 and a second detection end 202 that are arranged opposite to each other. The first detection end 201 is exposed at one end of the first through hole 101 and is electrically connected to the circuit to be tested in the multilayer circuit board 10. The second detection end 202 is exposed at the other end of the first through hole 101 and is electrically connected to the circuit to be tested in the multilayer circuit board 10. The surface of the first circuit board 11 facing the second circuit board 12 is the inner surface (not shown in the figure). The orthographic projection of the wiring of the circuit to be tested connected to the first detection end 201 on the inner surface is at least partially overlapped with the orthographic projection of the wiring of the circuit to be tested connected to the second detection end 202 on the inner surface. The current direction of the wiring of the circuit to be tested connected to the first detection end 201 is at least partially opposite to the current direction of the wiring of the circuit to be tested connected to the second detection end 202. The first detection end 201 and the second detection end 202 are both used for external voltage measuring devices.

[0036] In this embodiment, multiple chip resistors 20 are embedded in the multilayer circuit board 10, and the multiple chip resistors 20 are connected in parallel and in series to the circuit to be tested. By measuring the voltage signal between the first detection terminal 201 and the second detection terminal 202 of the chip resistor 20, the current of the circuit to be tested can be measured by conversion. When the chip resistors 20 are connected in parallel, the current will be shunted in the parallel chip resistors 20, so the current intensity in each single resistor is relatively small, and the magnetic field intensity generated by the resistor is weak, and the resulting stray inductance effect will also be relatively weakened. In addition, when the chip resistors 20 are connected in parallel, the current will be shunted between the various chip resistors 20, and each chip resistor 20 will bear a part of the current, so the total current that the entire circuit can carry can be increased, that is, the circuit current capacity is improved. In addition, the chip resistor 20 is embedded in the multilayer circuit board 10. Compared with the method of directly soldering the chip resistor 20 on the surface of the circuit board, the current direction of the wiring of the circuit to be tested connected to the first detection terminal 201 is at least partially opposite to the current direction of the wiring of the circuit to be tested connected to the second detection terminal 202. According to Ampere's law, the current loop connected to the first detection terminal 201 and the current loop connected to the second detection terminal 202 can generate magnetic fields in opposite directions. These magnetic fields in opposite directions will cancel each other out, resulting in a weakening of the magnetic field strength in the area between the two current loops. Since stray inductance exists due to the magnetic field effect generated by the current, the weakening of this magnetic field strength will reduce the stray inductance. On the other hand, such a design of the wiring can shorten the physical length of the current loop to a certain extent, thereby reducing the stray inductance; since the chip resistor 20 has a high-frequency bandwidth, it can provide an accurate resistance value in the high-frequency range, and the application range is less limited. Furthermore, the chip resistor 20 is cheaper than the coaxial shunt and the Rogowski coil, so it can also reduce the cost.

[0037] In some embodiments, Figure 4 As shown, the current measuring device also includes a surface mount component 40 (SMA ， SurfaceMount Assembly).

[0038] In some embodiments, Figure 4 As shown, the first detection end 201 is directly electrically connected to the circuit to be tested on the second circuit board 12, and the second detection end 202 is electrically connected to the circuit to be tested on the first circuit board 11. In some embodiments, the first detection end 201 can be electrically connected to the circuit to be tested on the first circuit board 11 by penetrating the second circuit board 12, and the second detection end 202 can be electrically connected to the circuit to be tested on the second circuit board 12 by penetrating the first circuit board 11.

[0039] In some embodiments, Figure 3As shown, the cross-sectional area of ​​the chip resistor 20 on the inner surface is less than or equal to the cross-sectional area of ​​the first through hole 101 on the inner surface, and the length of the chip resistor 20 along the opening direction is less than or equal to the distance between the side of the first circuit board 11 away from the second circuit board 12 and the side of the second circuit board 12 away from the first circuit board 11. By embedding the chip resistor 20 and making the height of the chip resistor 20 not exceed the total thickness of the multi-layer circuit board 10, the thickness of the multi-layer circuit board 10 will not be increased while embedding the chip resistor 20, which can reduce the volume of the current measuring device and increase the space available for accommodating other electronic devices on the multi-layer circuit board 10.

[0040] In some embodiments, the chip resistor 20 is clamped / welded / adhered into the first through hole 101 .

[0041] In some embodiments, Figures 5 to 8 As shown, the plurality of SMD resistors 20 include a first SMD resistor group 21 and a second SMD resistor group 22 arranged at intervals, the first SMD resistor group 21 includes a plurality of first SMD resistors 20a, the second SMD resistor group 22 includes a plurality of second SMD resistors 20b, and each of the first SMD resistors 20a is connected in parallel with each of the second SMD resistors 20b in a one-to-one correspondence. The stray inductance can be reduced while the working range is increased.

[0042] In some embodiments, Figure 6 and Figure 8 As shown, the first detection end 201 of the first chip resistor 20a is electrically connected to the first detection end 201 of the second chip resistor 20b and is commonly electrically connected to the first electrical connection line 31, and the first electrical connection line 31 is connected to the circuit to be tested in the multi-layer circuit board 10; the second detection end 202 of the first chip resistor 20a is electrically connected to the second detection end 202 of the second chip resistor 20b and is commonly electrically connected to the second electrical connection line 32, and the second electrical connection line 32 is connected to the circuit to be tested in the multi-layer circuit board 10.

[0043] In some embodiments, Figures 5 to 8As shown, the multilayer circuit board 10 also includes a third circuit board 13 and a fourth circuit board 14 sequentially stacked on the first circuit board 11; the third circuit board 13 and the fourth circuit board 14 are located between the first circuit board 11 and the second circuit board 12; the multilayer circuit board 10 is also provided with a plurality of second through holes 102 penetrating the multilayer circuit board 10, the opening direction of the second through holes 102 is parallel to the direction of the first circuit board 11 pointing to the second circuit board 12, the plurality of second through holes 102 include a first sub-through hole group 1021 and a second sub-through hole group 1022, the first sub-through hole group 1021 includes a plurality of first sub-through holes 102a, the second sub-through hole group 1022 includes a plurality of second sub-through holes 102b, the first electrical connection line 31 sequentially passes through the first sub-through holes 102a from the end connected to the first detection end 201 and is electrically connected to at least part of the circuit to be tested located in the first circuit board 11; the second electrical connection line 32 sequentially passes through the second sub-through holes 102b from the end connected to the second detection end 202 and is electrically connected to at least part of the circuit to be tested located in the second circuit board 12.

[0044] In some embodiments, Figure 6 As shown, the third circuit board 13 is connected to any second sub-through hole 102b in the second sub-through hole group 1022 and is electrically connected to the second electrical connection line 32. In this way, when the circuit to be tested is powered on, the direction of the current flowing through the wiring of the circuit to be tested located on the third circuit board 13 is opposite to the direction of the current flowing through the wiring of the circuit to be tested located on the first circuit board 11, and the magnetic fields generated by the currents flowing through the first circuit board 11 and the third circuit board 13 are opposite in direction and can cancel each other, thereby further reducing stray inductance.

[0045] In some embodiments, Figure 6 As shown, the fourth circuit board 14 is connected to any first sub-through hole 102a in the first sub-through hole group 1021 and is electrically connected to the first electrical connection line 31. Similar to the above-mentioned embodiment, in this embodiment, when the circuit to be tested is powered on, the direction of the current flowing through the wiring of the circuit to be tested on the fourth circuit board 14 is opposite to the direction of the current flowing through the wiring of the circuit to be tested on the second circuit board 12, and the magnetic fields generated by the currents flowing through the fourth circuit board 14 and the second circuit board 12 are opposite in direction and can cancel each other, thereby further reducing the stray inductance.

[0046] In some embodiments, Figure 6As shown, the third circuit board 13 is connected to the second sub-through hole 102b in the second sub-through hole group 1022 and is electrically connected to the second electrical connection line 32. The fourth circuit board 14 is connected to the first sub-through hole 102a in the first sub-through hole group 1021 and is electrically connected to the first electrical connection line 31. In this embodiment, when the circuit to be tested is powered on, the first circuit board 11, the third circuit board 13, the fourth circuit board 14 and the second circuit board 12 are sequentially stacked and arranged in the direction from the first circuit board 11 to the second circuit board 12, wherein the direction of the current flowing through the circuit to be tested on the first circuit board 11 is opposite to the direction of the current flowing through the circuit to be tested on the third circuit board 13, the direction of the current flowing through the circuit to be tested on the third circuit board 13 is opposite to the direction of the current flowing through the circuit to be tested on the fourth circuit board 14, and the direction of the current flowing through the circuit to be tested on the fourth circuit board 14 is opposite to the direction of the current flowing through the circuit to be tested on the second circuit board 12. Then the magnetic fields generated by the currents between adjacent circuit boards are opposite in direction and can offset each other, thereby further reducing the stray inductance.

[0047] In some embodiments, Figure 5 As shown, the first SMD resistor group 21 is adjacently arranged with the first sub-through hole group 1021, the second SMD resistor group 22 is arranged on the side of the first sub-through hole group 1021 away from the first SMD resistor group 21, and the second sub-through hole group 1022 is arranged on the side of the first SMD resistor group 21 away from the first through hole group 101. In this embodiment, the first SMD resistor group 21 and the second sub-through hole group 1022 are adjacently arranged, and the second SMD resistor group 22 and the first sub-through hole group 1021 are adjacently arranged. When the circuit to be tested is powered on, the direction of the current flowing through the first SMD resistor group 21 is opposite to the direction of the current flowing through the second electrical connection line 32 in the second sub-through hole group 1022, and the direction of the current flowing through the second SMD resistor group 22 is opposite to the direction of the current flowing through the first electrical connection line 31 in the first sub-through hole group 1021. It can be achieved that the magnetic fields generated by the current can cancel each other out, which can reduce the stray inductance and improve the accuracy of current measurement.

[0048] In some embodiments, Figure 6 As shown, the direction of the current flowing through the first SMD resistor group 21 and the direction of the current flowing through the second SMD resistor group 22 are both in the direction from the first circuit board 11 to the second circuit board 12; the direction of the current flowing through the first electrical connection line 31 in any first sub-through hole 102a located in the first sub-through hole group 1021 and the direction of the current flowing through the second electrical connection line 32 in any second sub-through hole 102b located in the second sub-through hole group 1022 are both in the direction from the second circuit board 12 to the first circuit board 11.

[0049] In some embodiments, the direction of the current flowing through the first chip resistor group 21 and the direction of the current flowing through the second chip resistor group 22 are both in the direction from the second circuit board 12 to the first circuit board 11; the direction of the current flowing through the first electrical connection line 31 in any first sub-through hole 102a located in the first sub-through hole group 1021 and the direction of the current flowing through the second electrical connection line 32 in any second sub-through hole 102b located in the second sub-through hole group 1022 are both in the direction from the first circuit board 11 to the second circuit board 12.

[0050] In some embodiments, Figure 6 As shown, each first sub-through hole 102a of the first sub-through hole group 1021 has a first opening end 1021a and a second opening end 1021b arranged opposite to each other, the first opening end 1021a is arranged on the second circuit board 12, and the second opening end 1021b is arranged on the first circuit board 11, and the end of the first electrical connection line 31 close to the first detection end 201 passes through the first opening end 1021a and the second opening end 1021b in sequence to be electrically connected to at least part of the circuit to be tested located in the first circuit board 11; Figure 7 As shown, each second sub-through hole 102b of the second sub-through hole group 1022 has a third opening end 1022a and a fourth opening end 1022b that are relatively arranged; the third opening end 1022a is arranged on the first circuit board 11, and the fourth opening end 1022b is arranged on the second circuit board 12, and the second electrical connection line 32 passes through the third opening end 1022a and the fourth opening end 1022b in sequence and is electrically connected to at least a portion of the circuit to be tested located on the second circuit board 12.

[0051] In some embodiments, Figure 5 As shown, the first chip resistor group 21 includes five first chip resistors 20a, and the second chip resistor group 22 includes five second chip resistors 20b. Each first chip resistor 20a is disposed adjacent to each second chip resistor 20b.

[0052] Based on the same inventive concept, the present application also provides a current measurement method for a power semiconductor device test circuit, wherein a current measurement device is connected in parallel to the wiring of the circuit to be tested, for example, Figure 6 As shown, the wiring on the second circuit board 12 and the wiring on the third circuit board 13 in the circuit to be tested are connected to the second detection end 202 of the first SMD resistor 20a and the second SMD resistor 20b. Figure 8As shown, the wiring located on the first circuit board 11 and the wiring located on the third circuit board 14 in the circuit to be tested are commonly connected to the first detection terminal 201 of the first SMD resistor 20a and the second SMD resistor 20b. The measurement method includes: when the circuit to be tested is powered on, collecting the voltage signal between the first detection terminal 201 and the second detection terminal 202, and determining the current to be tested of the power semiconductor device test circuit according to the voltage signal. In the measurement method of this embodiment, the current of the circuit to be tested can be obtained by measuring the voltage signal between the first detection terminal 201 and the second detection terminal 202 in combination with the resistance value of the SMD resistor 20.

[0053] It should be pointed out that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0054] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0055] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the claims.

[0056] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A current measuring device for a power semiconductor device test circuit, characterized in that: include: A multilayer circuit board, comprising at least a first circuit board and a second circuit board arranged opposite to each other, wherein the multilayer circuit board is provided with a plurality of first through holes penetrating the multilayer circuit board, and the opening direction of the first through holes is parallel to the direction from the first circuit board to the second circuit board; A plurality of chip resistors, at least two of which are connected in parallel, each of which is embedded in each of the first through holes of the multilayer circuit board, each of which comprises a first detection end and a second detection end which are arranged opposite to each other, the first detection end being exposed at one end of the first through hole and being electrically connected to the circuit to be tested in the multilayer circuit board, the second detection end being exposed at the other end of the first through hole and being electrically connected to the circuit to be tested in the multilayer circuit board, the surface of the first circuit board facing the second circuit board being the inner surface, the orthographic projection of the wiring of the circuit to be tested connected to the first detection end on the inner surface is at least partially overlapped with the orthographic projection of the wiring of the circuit to be tested connected to the second detection end on the inner surface, the current direction of the wiring of the circuit to be tested connected to the first detection end is at least partially opposite to the current direction of the wiring of the circuit to be tested connected to the second detection end, and both the first detection end and the second detection end are used for an external voltage measuring device.

2. The current measuring device for a power semiconductor device test circuit according to claim 1, characterized in that: The cross-sectional area of ​​the chip resistor on the inner surface is less than or equal to the cross-sectional area of ​​the first through hole on the inner surface, and the length of the chip resistor along the opening direction is less than or equal to the distance between a side of the first circuit board facing away from the second circuit board and a side of the second circuit board facing away from the first circuit board.

3. The current measuring device for a power semiconductor device test circuit according to claim 1, characterized in that: The multiple chip resistors include a first chip resistor group and a second chip resistor group arranged at intervals, the first chip resistor group includes multiple first chip resistors, the second chip resistor group includes multiple second chip resistors, and each of the first chip resistors is connected in parallel with each of the second chip resistors in a one-to-one correspondence.

4. The current measuring device for a power semiconductor device test circuit according to claim 3, characterized in that: The first detection end of the first SMD resistor is electrically connected to the first detection end of the second SMD resistor and is electrically connected to a first electrical connection line, and the first electrical connection line is connected to the circuit to be tested in the multi-layer circuit board; The second detection end of the first chip resistor is electrically connected to the second detection end of the second chip resistor and is commonly electrically connected to a second electrical connection line, and the second electrical connection line is connected to the circuit to be tested in the multi-layer circuit board.

5. The current measuring device for a power semiconductor device test circuit according to claim 4, characterized in that: The multi-layer circuit board also includes a third circuit board and a fourth circuit board sequentially stacked on the first circuit board; the third circuit board and the fourth circuit board are located between the first circuit board and the second circuit board; the multi-layer circuit board is also provided with a plurality of second through holes penetrating the multi-layer circuit board, the opening direction of the second through holes is parallel to the direction of the first circuit board pointing to the second circuit board, the plurality of second through holes include a first sub-through hole group and a second sub-through hole group, the first sub-through hole group includes a plurality of first sub-through holes, the second sub-through hole group includes a plurality of second sub-through holes, the first electrical connection line sequentially passes through the first sub-through holes from the end connected to the first detection end to be electrically connected to at least part of the circuit to be tested in the first circuit board; the second electrical connection line sequentially passes through the second sub-through holes from the end connected to the second detection end to be electrically connected to at least part of the circuit to be tested in the second circuit board; wherein, The third circuit board is connected to the second sub-through holes in the second sub-through hole group and is electrically connected to the second electrical connection line; And / or, the fourth circuit board is communicated with the first sub-through holes in the first sub-through hole group and is electrically connected to the first electrical connection line.

6. The current measuring device for a power semiconductor device test circuit according to claim 5, characterized in that: The direction of the current flowing through the wiring of at least part of the circuit to be tested located on the third circuit board is opposite to the direction of the current flowing through the wiring of at least part of the circuit to be tested located on the first circuit board; the direction of the current flowing through the wiring of at least part of the circuit to be tested located on the fourth circuit board is opposite to the direction of the current flowing through the wiring of at least part of the circuit to be tested located on the second circuit board.

7. The current measuring device for a power semiconductor device test circuit according to claim 5, characterized in that: The first chip resistor group is arranged adjacent to the first sub-through hole group, the second chip resistor group is arranged on a side of the first sub-through hole group away from the first chip resistor group, and the second sub-through hole group is arranged on a side of the first chip resistor group away from the first through hole group.

8. The current measuring device for a power semiconductor device test circuit according to claim 5, characterized in that: The direction of current flowing through any chip resistor in the first chip resistor group is the same as the direction of current flowing through any chip resistor in the second chip resistor group; the direction of current flowing through the first electrical connection line in any first sub-through hole group located in the first sub-through hole group is opposite to the direction of current flowing through any chip resistor in the first chip resistor group, and the direction of current flowing through the second electrical connection line in any second sub-through hole group located in the second sub-through hole group is opposite to the direction of current flowing through any chip resistor in the second chip resistor group.

9. The current measuring device for a power semiconductor device test circuit according to claim 8, characterized in that: The direction of the current flowing through the first SMD resistor group and the direction of the current flowing through the second SMD resistor group are both in the direction from the first circuit board to the second circuit board; the direction of the current flowing through the first electrical connection line in any first sub-through hole located in the first sub-through hole group and the direction of the current flowing through the second electrical connection line in any second sub-through hole located in the second sub-through hole group are both in the direction from the second circuit board to the first circuit board; Or, the direction of the current flowing through the first chip resistor group and the direction of the current flowing through the second chip resistor group are both in the direction from the second circuit board to the first circuit board; the direction of the current flowing through the first electrical connection line in any first sub-through hole located in the first sub-through hole group and the direction of the current flowing through the second electrical connection line in any second sub-through hole located in the second sub-through hole group are both in the direction from the first circuit board to the second circuit board.

10. The current measuring device for a power semiconductor device test circuit according to claim 5, characterized in that: Each first sub-through hole of the first sub-through hole group has a first opening end and a second opening end that are arranged oppositely, the first opening end is arranged on the second circuit board, and the second opening end is arranged on the first circuit board, and the end of the first electrical connection line close to the first detection end passes through the first opening end and the second opening end in sequence to be electrically connected to at least a portion of the circuit to be tested located in the first circuit board; each second sub-through hole of the second sub-through hole group has a third opening end and a fourth opening end that are arranged oppositely; the third opening end is arranged on the first circuit board, and the fourth opening end is arranged on the second circuit board, and the second electrical connection line passes through the third opening end and the fourth opening end in sequence to be electrically connected to at least a portion of the circuit to be tested located on the second circuit board.

11. A current measurement method for a power semiconductor device test circuit, characterized in that: Based on the current measuring device according to any one of claims 1 to 10, the current measuring method comprises: When the circuit to be tested is powered on, a voltage signal between the first detection terminal and the second detection terminal is collected, and a current to be tested of the power semiconductor device test circuit is determined according to the voltage signal.

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