Circuit and method for detecting plane short circuit of main power supply in S5 state

Abstract

The invention provides a main power supply plane short circuit detection circuit and method in an S5 state. The detection circuit comprises a logic device, a first electronic switch, a second electronic switch and a third electronic switch. The logic device outputs a control signal to turn on the first electronic switch, and short circuit detection is started. The standby power supply is grounded through the first electronic switch, the first pull-up resistor and the first pull-down resistor; the connection point of the first pull-up resistor and the first pull-down resistor is a first node; the first node is connected with the main power supply plane. When the main power supply plane is not short-circuited, the first node is in a high level to control the second electronic switch to be switched on so as to control the third electronic switch to be switched off, and the third electronic switch outputs a high level signal to the logic device; and when the main power supply plane is short-circuited, the first node is at a low level, the second electronic switch is switched off, the gate of the third electronic switch is at a high level, the third electronic switch is switched on, and a low-level signal is output to the logic device. According to the application, the short circuit condition of the main power supply plane can be detected in the S5 state before the server is started.

Description

Technical Field

[0001] The present application belongs to the field of power supply detection technology, and specifically relates to a main power supply plane short circuit detection circuit and method in the S5 state. Background Art

[0002] With the rapid development of artificial intelligence applications, artificial intelligence (AI) servers have shown explosive growth. A typical AI server can be configured with 8 to 10 PCIe (a high-speed serial computer expansion bus standard) standard card-shaped GPUs. As GPU performance improves, the current general GPU power consumption has reached 350W and above. The GPU card is inserted into the slot of the single board through the gold finger, and the power is supplied through the power pin on the gold finger, which can supply 75W. For GPUs with a higher power consumption of more than 75W, it is not enough to supply power only through the gold finger. There is also an auxiliary power connector for providing main power. The GPU auxiliary power line connects to the server single board through the auxiliary power connector to power the GPU. There are many GPU manufacturers, and the auxiliary power connector signal definitions of different manufacturers and different models of GPUs are different. The auxiliary power connector anti-fool function cannot completely avoid the risk of wrong insertion of the GPU auxiliary power line and the insertion of mismatched power lines. The wrong insertion of the GPU auxiliary power line is likely to cause a power short circuit, thereby causing serious faults such as single board burnout and GPU damage. Therefore, GPU servers face a greater risk of short circuits when used by customers. The existing solution is to detect and monitor the circuit through an electronic fuse (EFUSE) circuit. The EFUSE circuit is located before the GPU power supply. After the server is turned on and the main power plane (such as 12V power supply) is powered on, real-time monitoring of this main power is carried out, including overcurrent detection, etc. After a fault occurs, the power supply is turned off and the fault is reported. This solution monitors and detects the power supply status after the main power is supplied after the server is turned on.

[0003] Currently, there is still a lack of technology for short-circuit risk assessment before the main power is turned on. Summary of the invention

[0004] The purpose of the present invention is to provide a main power plane short circuit detection circuit and method in the S5 state, which can complete the main power plane short circuit detection in the S5 state before the server is turned on.

[0005] The technical solution provided by this application is:

[0006] In a first aspect, the present application provides a main power plane short circuit detection circuit in the S5 state, comprising: a logic device, a first electronic switch, a second electronic switch, a third electronic switch, a first pull-up resistor, a second pull-up resistor, and a third pull-up resistor;

[0007] The detection enable signal output terminal of the logic device is connected to the first terminal of the first electronic switch, the second terminal of the first electronic switch is connected to the standby power terminal, and the third terminal of the first electronic switch is grounded via the first pull-up resistor and the first pull-down resistor; the first terminal of the first electronic switch is the control terminal of the first electronic switch, and is used to control the on-off between the second terminal and the third terminal of the first electronic switch;

[0008] The connection point between the first pull-up resistor and the first pull-down resistor is a first node; the first node is connected to the main power plane;

[0009] The first node is connected to the first end of the second electronic switch, the second end of the second electronic switch is grounded, and the third end of the second electronic switch is connected to the first end of the third switch; the first end of the second electronic switch is the control end of the second electronic switch, and is used to control the on-off between the second end and the third end of the second electronic switch;

[0010] The second end of the third switch is grounded, and the third end of the third switch is connected to the short-circuit detection signal input end of the logic device; the first end of the third electronic switch is the control end of the third electronic switch, which is used to control the on-off between the second end and the third end of the third electronic switch;

[0011] The third terminal of the second electronic switch is connected to the standby power terminal via a second pull-up resistor;

[0012] The third terminal of the third switch is connected to the standby power terminal via a third pull-up resistor.

[0013] In a possible implementation of the first aspect, the first electronic switch is a PMOS, and the first end, the second end, and the third section of the first electronic switch are divided into a gate (G pole), a source (S pole), and a drain (D pole);

[0014] The second electronic switch is an NMOS, and the first end, the second end and the third section of the first electronic switch are divided into a gate, a source and a drain thereof;

[0015] The third electronic switch is an NMOS, and the first end, the second end and the third section of the first electronic switch are divided into a gate, a source and a drain thereof.

[0016] In a possible implementation manner of the first aspect, the logic device is a CPLD or an FPGA.

[0017] In a possible implementation of the first aspect, the logic device is connected to an alarm device; if the logic device outputs a control signal through the detection enable signal output terminal, controls the first electronic switch Q3 to turn on, starts detection, and the short-circuit detection signal input terminal of the logic device receives a fault signal, then the logic device controls the alarm device to issue a power failure alarm.

[0018] In a second aspect, the present application provides a main power plane short circuit detection method in the S5 state, which implements the main power plane short circuit detection in the S5 state based on the above-mentioned main power plane short circuit detection circuit in the S5 state, including:

[0019] The logic device outputs a control signal through the detection enable signal output terminal to control the first electronic switch Q3 to be turned on and start detection;

[0020] If the short-circuit detection signal input terminal of the logic device receives a fault signal, the logic device determines that the main power plane is short-circuited, otherwise the logic device determines that the main power plane is normal.

[0021] In a possible implementation of the second aspect, the first electronic switch is a PMOS, and the first end, the second end, and the third section of the first electronic switch are divided into its gate, source, and drain; the second electronic switch is an NMOS, and the first end, the second end, and the third section of the first electronic switch are divided into its gate, source, and drain; the third electronic switch is an NMOS, and the first end, the second end, and the third section of the first electronic switch are divided into its gate, source, and drain;

[0022] The control signal is a low level signal; the fault signal is also a low level signal.

[0023] In a possible implementation of the second aspect, if the logic device determines that the main power plane is short-circuited, the alarm device is controlled to issue a power failure alarm.

[0024] Beneficial effects:

[0025] The present application provides a main power plane short-circuit detection solution in the S5 state through the coordination of hardware circuit design and logic judgment. In the S5 state before the server is turned on, although the main power has no output, the short-circuit condition can be judged by detecting the impedance of the main power plane to the ground and the feedback is given to the logic device. The short-circuit condition detection of the main power plane can be completed in the S5 state before the server is turned on, and the short-circuit risk judgment can be performed in advance before the main power plane is powered on, providing more effective short-circuit detection and safety protection for the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 PCIe 8-pin power connector;

[0027] Figure 2 CPU 8-pin power connector;

[0028] Figure 3 This is a circuit diagram of an embodiment of the present application;

[0029] Figure 4 This is a logic block diagram of an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0031] It should be noted that the terms such as "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is a specific relationship or order between these entities or operations. It should be understood that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first" and "second" and the like do not limit them to be necessarily different. It should be understood that the data used in this way can be interchanged under appropriate circumstances. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, article or device including a series of elements includes not only those elements clearly listed, but also other elements that are not clearly listed, or may also include elements inherent to such process, method, product or device. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0032] In addition, the terms "installed", "set", "provided with", "connected", "connected", and "socketed" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0033] like Figure 1 and Figure 2 Shown are two commonly used GPU auxiliary power interface definitions. Figure 1 For PCIe 8-pin, Figure 2 For CPU 8-pin. Figure 1 and Figure 2It can be seen that different power interfaces define the 12V power pin and the GND (ground wire) pin in opposite directions. Connecting them incorrectly will directly lead to a short circuit. The connector is only foolproof with square corners and rounded corners, but the foolproof strength is weak, and forced insertion can still be performed.

[0034] The power status of the server includes the S0 status, which is the normal working status after the server is turned on and the main power is supplied.

[0035] The existing solution can only monitor and detect the power supply status in the S0 state.

[0036] The present application provides a technical solution that can detect the short circuit of the main power plane domain when the power state of the server is in the S5 state, that is, the shutdown state, and the main power has not been output.

[0037] The present invention relates to a hardware circuit short-circuit detection solution, which can be applied to server products or other application scenarios that require improved short-circuit detection capabilities.

[0038] This solution provides a main power plane short-circuit detection solution in the S5 state through the cooperation of hardware circuits and logic devices. In the S5 state before the server is powered on, the impedance of the power plane to the ground is detected to determine the short-circuit condition and the solution is fed back to the logic device to realize the function of detecting the short-circuit condition of the main power plane in the S5 state. The short-circuit risk judgment can be completed in advance before the main power plane is powered on, providing more effective short-circuit detection and safety protection for the product.

[0039] The following will refer to Figure 1 Specific embodiments according to the present application are described.

[0040] picture Figure 3 As shown, an embodiment of the present application provides a main power plane short circuit detection circuit in the S5 state, including: a logic device, a first electronic switch, a second electronic switch, a third electronic switch, a first pull-up resistor, a second pull-up resistor and a third pull-up resistor;

[0041] The detection enable signal output terminal of the logic device is connected to the first terminal of the first electronic switch, the second terminal of the first electronic switch is connected to the standby power terminal, and the third terminal of the first electronic switch is grounded via the first pull-up resistor and the first pull-down resistor; the first terminal of the first electronic switch is the control terminal of the first electronic switch, and is used to control the on-off between the second terminal and the third terminal of the first electronic switch;

[0042] The connection point between the first pull-up resistor and the first pull-down resistor is a first node; the first node is connected to the main power plane;

[0043] The first node is connected to the first end of the second electronic switch, the second end of the second electronic switch is grounded, and the third end of the second electronic switch is connected to the first end of the third switch; the first end of the second electronic switch is the control end of the second electronic switch, and is used to control the on-off between the second end and the third end of the second electronic switch;

[0044] The second end of the third switch is grounded, and the third end of the third switch is connected to the short-circuit detection signal input end of the logic device; the first end of the third electronic switch is the control end of the third electronic switch, which is used to control the on-off between the second end and the third end of the third electronic switch;

[0045] The third terminal of the second electronic switch is connected to the standby power terminal via a second pull-up resistor;

[0046] The third terminal of the third switch is connected to the standby power terminal via a third pull-up resistor.

[0047] Further, the first electronic switch is a PMOS, and the first end, the second end and the third section of the first electronic switch are divided into its gate, source and drain;

[0048] The second electronic switch is an NMOS, and the first end, the second end and the third section of the first electronic switch are divided into a gate, a source and a drain thereof;

[0049] The third electronic switch is an NMOS, and the first end, the second end and the third section of the first electronic switch are divided into a gate, a source and a drain thereof.

[0050] Furthermore, the logic device is CPLD or FPGA.

[0051] Furthermore, the logic device is connected to an alarm device; if the logic device outputs a control signal through the detection enable signal output terminal, controls the first electronic switch Q3 to turn on, starts detection, and the short-circuit detection signal input terminal of the logic device receives a fault signal, then the logic device controls the alarm device to issue a power failure alarm.

[0052] A main power plane short circuit detection method in the S5 state, based on the main power plane short circuit detection circuit in the S5 state, comprises:

[0053] The logic device outputs a control signal through the detection enable signal output terminal to control the first electronic switch Q3 to be turned on and start detection;

[0054] If the short-circuit detection signal input terminal of the logic device receives a fault signal, the logic device determines that the main power plane is short-circuited, otherwise the logic device determines that the main power plane is normal.

[0055] Furthermore, if the logic device determines that the main power plane is short-circuited, the alarm device is controlled to issue a power failure alarm.

[0056] Further, the first electronic switch is a PMOS, and the first end, the second end and the third section of the first electronic switch are divided into its gate, source and drain; the second electronic switch is an NMOS, and the first end, the second end and the third section of the first electronic switch are divided into its gate, source and drain; the third electronic switch is an NMOS, and the first end, the second end and the third section of the first electronic switch are divided into its gate, source and drain;

[0057] The control signal is a low level signal; the fault signal is also a low level signal.

[0058] The following combination Figure 3 The working principle of this application is explained in detail.

[0059] The working principle of the present invention is that the logic device detection enable signal output terminal TEST_Enable_N outputs a low level signal to control the first electronic switch Q3 to be turned on and start detection.

[0060] When TEST_Enable_N is low, Q3 is turned on and detection is enabled. When TEST_Enable_N is high, Q3 is turned off and detection is disabled.

[0061] In the S5 state, some components are powered, that is, they are powered by the standby power supply (STBY_POWER), but there is no main power supply (MAIN_POWER) plane and it is not powered.

[0062] Case 1: The main power plane is short-circuited. At this time, the impedance of the first node to ground is close to 0, the gate level of the second electronic switch Q2 is close to 0, the second electronic switch Q2 is turned off, and the gate of the third electronic switch Q3 is connected to the standby power terminal STBY_POWER (STBY_POWER is a power supply with a voltage of 3.3V in the S5 shutdown state). The level after the pull-up resistor R3 is high, the third electronic switch Q3 is turned on, and the drain and source of the third electronic switch Q3 are connected to the ground at a low level, thereby outputting a low-level signal to the short-circuit detection signal input terminal SHORT_TEST_N of the logic device. The logic device determines that the main power plane is short-circuited and issues a power failure alarm.

[0063] Case 2: There is no short circuit on the main power plane. At this time, the main power plane has a certain impedance to the ground. After the voltage of the standby power terminal STBY_POWER is divided by the pull-up resistor R8 and the pull-down resistor R9, the divided voltage level (the level of the first node) is greater than the threshold voltage Vgs(th) of the second electronic switch Q2, and the second electronic switch Q2 is turned on. At this time, the drain and source of the second electronic switch Q2 are connected to the ground at a low level, resulting in the gate of the third electronic switch Q3 being at a low level. The third electronic switch Q3 is turned off, and the detection circuit outputs a high-level signal to the short-circuit detection signal input terminal SHORT_TEST_N of the logic device. The logic device determines that the main power plane is normal and controls the power state machine to start up normally.

[0064] like Figure 4 As shown, the present application can control the start of short-circuit detection by detecting the output control signal of the enable signal output terminal TEST_Enable_N through the logic device when the server is in the S5 state with the power supply (i.e., power supply unit, English: Powersupply unit, referred to as PSU) in place, and the control signal is turned on at the same time. According to the preset detection completion time, such as t seconds, the detection is turned off after t seconds of turning on, so as to avoid unnecessary coupling effects of the related circuits after power-on.

[0065] In different application scenarios, the electronic switch and resistor value need to be debugged according to the actual circuit to ensure that the electronic switch can be stably turned on under normal conditions.

[0066] This detection circuit uses only simple discrete devices and cooperates with the power-on timing control of logic devices to realize the function of detecting short-circuit conditions on the main power plane in the S5 state. The short-circuit risk judgment is completed in advance before the main power plane is powered on, providing more effective short-circuit detection and safety protection for the product.

[0067] The above description of the embodiments of the present application is only a partial embodiment of the present application, which is used to enable professionals in the field to implement or use the content of the present application, and is not used to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A main power plane short circuit detection circuit in the S5 state, characterized in that: include: A logic device, a first electronic switch, a second electronic switch, a third electronic switch, a first pull-up resistor, a second pull-up resistor, and a third pull-up resistor; The detection enable signal output terminal of the logic device is connected to the first terminal of the first electronic switch, the second terminal of the first electronic switch is connected to the standby power terminal, and the third terminal of the first electronic switch is grounded via the first pull-up resistor and the first pull-down resistor; the first terminal of the first electronic switch is the control terminal of the first electronic switch, and is used to control the on-off between the second terminal and the third terminal of the first electronic switch; The connection point between the first pull-up resistor and the first pull-down resistor is a first node; the first node is connected to the main power plane; The first node is connected to the first end of the second electronic switch, the second end of the second electronic switch is grounded, and the third end of the second electronic switch is connected to the first end of the third switch; the first end of the second electronic switch is the control end of the second electronic switch, and is used to control the on-off between the second end and the third end of the second electronic switch; The second end of the third switch is grounded, and the third end of the third switch is connected to the short-circuit detection signal input end of the logic device; the first end of the third electronic switch is the control end of the third electronic switch, which is used to control the on-off between the second end and the third end of the third electronic switch; The third terminal of the second electronic switch is connected to the standby power terminal via a second pull-up resistor; The third terminal of the third switch is connected to the standby power terminal via a third pull-up resistor.

2. The main power plane short circuit detection circuit in the S5 state according to claim 1, characterized in that: The first electronic switch is a PMOS, and the first end, the second end and the third section of the first electronic switch are divided into a gate, a source and a drain thereof; The second electronic switch is an NMOS, and the first end, the second end and the third section of the first electronic switch are divided into a gate, a source and a drain thereof; The third electronic switch is an NMOS, and the first end, the second end and the third section of the first electronic switch are divided into a gate, a source and a drain thereof.

3. The main power plane short circuit detection circuit in the S5 state according to claim 1, characterized in that: The logic device is CPLD or FPGA.

4. The main power plane short circuit detection circuit in the S5 state according to claim 1, characterized in that: The logic device is connected to the alarm device; if the logic device outputs a control signal through the detection enable signal output terminal, controls the first electronic switch Q3 to be turned on, starts detection, and the short-circuit detection signal input terminal of the logic device receives a fault signal, then the logic device controls the alarm device to issue a power failure alarm.

5. A main power plane short circuit detection method in the S5 state, based on the main power plane short circuit detection circuit in the S5 state according to any one of claims 1 to 4 to implement the main power plane short circuit detection in the S5 state, comprising: The logic device outputs a control signal through the detection enable signal output terminal to control the first electronic switch Q3 to be turned on and start detection; If the short-circuit detection signal input terminal of the logic device receives a fault signal, the logic device determines that the main power plane is short-circuited, otherwise the logic device determines that the main power plane is normal.

6. The main power plane short circuit detection method in the S5 state according to claim 5, characterized in that: The first electronic switch is a PMOS, and the first end, the second end and the third section of the first electronic switch are divided into a gate, a source and a drain thereof; The second electronic switch is an NMOS, and the first end, the second end and the third section of the first electronic switch are divided into a gate, a source and a drain thereof; The third electronic switch is an NMOS, and the first end, the second end and the third section of the first electronic switch are divided into its gate, source and drain; The control signal is a low level signal; the fault signal is also a low level signal.

7. The main power plane short circuit detection method in the S5 state according to claim 5 or 6, characterized in that: If the logic device determines that the main power plane is short-circuited, the alarm device is controlled to issue a power failure alarm.

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