A driving substrate, a preparation method thereof, and a display panel

Abstract

The application provides a driving substrate and a preparation method thereof and a display panel, relates to the technical field of display, and comprises a switching area and a capacitor area arranged on at least one side of the switching area. The driving substrate comprises a substrate, a first electrode layer, a second electrode layer and a third electrode layer which are sequentially arranged on one side of the substrate. The first electrode layer is arranged close to the substrate. The second electrode layer and the first electrode layer at least partially overlap in orthographic projection on the substrate. The third electrode layer and the second electrode layer at least partially overlap in orthographic projection on the substrate. The first electrode layer comprises a plurality of first electrode patterns which are arranged at intervals in the capacitor area. Each first electrode pattern comprises a first ramp area. The thickness of the first electrode pattern in the first ramp area gradually decreases along a first direction. The first direction is a direction in which a central region of the first electrode pattern points to an edge of the first electrode pattern.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, in particular, to a driving substrate, a preparation method thereof and a display panel. BACKGROUND

[0002] Electronic Paper Display (EPD) is a kind of paper-like display technology, which is developed early. It is a kind of display technology that uses charged balls of different colors to move in a liquid environment to show different colors.

[0003] The design of the driving substrate of the EPD display is quite different from that of the ordinary LCD display. In order to maintain the bistability of the EPD, a double-layer storage capacitor (DL-Cst) needs to be designed in the circuit of the EPD driving substrate. The conventional double-capacitor design usually connects the upper and lower two metal electrodes to form an upper and lower double-layer capacitor opposite to the middle metal electrode. However, the three-layer metal electrodes in the existing double-capacitor design are in a block structure. The metal stress is accumulated in the pixel electrode, which causes the film layer on it, such as the transparent electrode layer, to fall off due to stress release. In severe cases, the transparent electrode layer of the entire pixel will fall off. Therefore, how to effectively avoid the electrode layer on the driving substrate from falling off and improve the product competitiveness has become a problem to be solved in the current field. SUMMARY

[0004] Embodiments of the present application provide a driving substrate, a preparation method thereof and a display panel, which aims to solve the problem of how to effectively avoid the electrode layer on the driving substrate from falling off.

[0005] The first aspect of the embodiments of the present application provides a driving substrate, comprising a switching area and a capacitor area arranged on at least one side of the switching area, the driving substrate comprising:

[0006] a substrate substrate;

[0007] a first electrode layer, a second electrode layer and a third electrode layer are sequentially stacked on one side of the substrate substrate, the first electrode layer is arranged close to the substrate substrate, the second electrode layer and the first electrode layer are at least partially overlapped on the substrate substrate, and the third electrode layer and the second electrode layer are at least partially overlapped on the substrate substrate;

[0008] The first electrode layer comprises a plurality of first electrode patterns arranged at intervals in the capacitor area, each first electrode pattern comprises a first ramp area, the thickness of the first electrode pattern gradually decreases in the first ramp area along a first direction, and the first direction is a direction from the center region of the first electrode pattern to the edge of the first electrode pattern.

[0009] In an alternative embodiment, the second electrode layer comprises a second electrode pattern, the second electrode pattern is disposed within the capacitor region, the second electrode pattern is insulated from the first electrode layer, and the second electrode pattern is insulated from the third electrode layer.

[0010] In an alternative embodiment, the second electrode pattern has a footprint on the substrate that covers at least the footprint of the plurality of first electrode patterns and the gap between adjacent first electrode patterns on the substrate.

[0011] In an alternative embodiment, the second electrode pattern comprises a plurality of second electrode sub-patterns, the plurality of second electrode sub-patterns are arranged in an alternating and spaced-apart manner with the plurality of first electrode patterns.

[0012] The footprint of the second electrode sub-pattern on the substrate covers the footprint of the gap between adjacent first electrode patterns on the substrate, and the footprint of the second electrode sub-pattern on the substrate partially overlaps with the footprint of an adjacent first electrode pattern on the substrate.

[0013] In an alternative embodiment, each of the second electrode sub-patterns comprises a second ramp region, the thickness of the second electrode sub-pattern gradually decreases along a second direction from a center region of the second electrode sub-pattern to an edge of the second electrode sub-pattern, the maximum thickness of the second electrode sub-pattern is the same as the maximum thickness of the first electrode pattern, and the second direction is a direction from the center region of the second electrode sub-pattern to the edge of the second electrode sub-pattern.

[0014] In an alternative embodiment, the second electrode layer further comprises a first conductive film layer, the first conductive film layer is disposed between the second electrode sub-pattern and the third electrode layer, the first conductive film layer covers the plurality of second electrode sub-patterns and the gap between adjacent second electrode sub-patterns, and the thickness of the first conductive film layer is less than the maximum thickness of the second electrode sub-pattern.

[0015] In an alternative embodiment, the second electrode layer further comprises a source-drain electrode pattern, the source-drain electrode pattern covers the substrate within the switch region and extends to the capacitor region, and the source-drain electrode pattern is insulated from the second electrode pattern.

[0016] The source-drain electrode pattern is provided with a first via in the capacitor region, and the source-drain electrode pattern and the first electrode layer are electrically connected through the first via.

[0017] In an alternative implementation, the first electrode layer further comprises a second conductive film layer, the second conductive film layer is disposed between the first electrode pattern and the second electrode layer, the second conductive film layer covers the plurality of first electrode patterns and the gaps between adjacent first electrode patterns in its entirety, and the thickness of the second conductive film layer is less than the maximum thickness of the first electrode pattern.

[0018] In an alternative implementation, the driving substrate further comprises a passivation insulating layer, the passivation insulating layer is disposed between the second electrode layer and the third electrode layer, and the orthogonal projection of the passivation insulating layer on the substrate substrate covers the capacitor region and the switch region.

[0019] The passivation insulating layer is provided with a second via hole in the capacitor region, the third electrode layer covers the side surface of the second via hole away from the substrate substrate in its entirety, the orthogonal projection of the second via hole on the substrate substrate at least partially overlaps the orthogonal projection of the first via hole on the substrate substrate, and the third electrode layer and the first electrode layer are electrically connected through the first via hole and the second via hole.

[0020] In an alternative implementation, the plurality of first electrode patterns are arranged at intervals along a third direction, and the gaps between adjacent first electrode patterns form a hollow structure extending along a fourth direction, the third direction being the arrangement direction of the switch region and the capacitor region, and the fourth direction being a direction perpendicular to the third direction.

[0021] In an alternative implementation, the plurality of first electrode patterns are arranged at intervals along a third direction, and the gaps between adjacent first electrode patterns form a hollow structure;

[0022] The hollow structure comprises a plurality of hollow substructures arranged at intervals along a fourth direction, the third direction being the arrangement direction of the switch region and the capacitor region, and the fourth direction being a direction perpendicular to the third direction.

[0023] In an alternative implementation, the maximum thickness of the first electrode pattern is greater than or equal to 500 nm.

[0024] In an alternative implementation, the slope angle of the first ramp region of the first electrode pattern is less than or equal to 40°.

[0025] The second aspect of the embodiments of the present application provides a preparation method of a driving substrate, the driving substrate comprising a switch region and a capacitor region arranged on at least one side of the switch region, and the preparation method comprising:

[0026] providing a substrate substrate;

[0027] The first electrode layer is arranged close to the substrate substrate, the second electrode layer at least partially overlaps the orthogonal projection of the first electrode layer on the substrate substrate, and the third electrode layer at least partially overlaps the orthogonal projection of the second electrode layer on the substrate substrate.

[0028] The first electrode layer includes a plurality of first electrode patterns arranged at intervals in the capacitor region, each first electrode pattern includes a first ramping region, and the thickness of the first electrode pattern gradually decreases in the first direction at the first ramping region.

[0029] The display panel includes a liquid crystal layer, a counter substrate, and the driving substrate as any one of the first aspect of the embodiments.

[0030] Beneficial effects:

[0031] The application provides a driving substrate, a preparation method thereof, and a display panel. The driving substrate includes a switching region and a capacitor region arranged on at least one side of the switching region. The driving substrate includes a substrate substrate, a first electrode layer, a second electrode layer, and a third electrode layer sequentially and layerwisely arranged on one side of the substrate substrate. The first electrode layer is arranged close to the substrate substrate. The second electrode layer at least partially overlaps the orthogonal projection of the first electrode layer on the substrate substrate. The third electrode layer at least partially overlaps the orthogonal projection of the second electrode layer on the substrate substrate. The first electrode layer includes a plurality of first electrode patterns arranged at intervals in the capacitor region. Each first electrode pattern includes a first ramping region. The thickness of the first electrode pattern gradually decreases in the first direction at the first ramping region. The first direction is the direction from the central region of the first electrode pattern to the edge of the first electrode pattern. The application increases the overlapping area between the electrode layers by arranging the first electrode pattern with the first ramping region and forming the second electrode layer and the third electrode layer on the first electrode pattern, thereby effectively increasing the capacitance of the double-layer capacitor, releasing the stress of the large metal electrode of the double-layer capacitor, and improving the problem of electrode layer falling caused by stress pulling. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without any creative labor.

[0033] Figure 1 is a schematic diagram of a cross section structure of a driving substrate along A-A' according to an embodiment of the present application;

[0034] Figure 2 is a schematic diagram of a cross section structure of a driving substrate along A-A' according to an embodiment of the present application;

[0035] Figure 3 is a schematic diagram of a cross section structure of a driving substrate along A-A' according to an embodiment of the present application;

[0036] Figure 4 is a schematic diagram of a cross section structure of a driving substrate along A-A' according to an embodiment of the present application;

[0037] Figure 5 is a schematic diagram of a cross section structure of a driving substrate along A-A' according to an embodiment of the present application;

[0038] Figure 6 is a schematic diagram of a cross section structure of a driving substrate along A-A' according to an embodiment of the present application;

[0039] Figure 7a is a schematic diagram of a cross section structure of a driving substrate along A-A' according to an embodiment of the present application;

[0040] Figure 7b is a schematic diagram of a cross section structure of a driving substrate along A-A' according to an embodiment of the present application;

[0041] Figure 8a is a schematic diagram of a cross section structure of a driving substrate along A-A' according to an embodiment of the present application;

[0042] Figure 8b is a schematic diagram of a cross section structure of a driving substrate along A-A' according to an embodiment of the present application;

[0043] Figure 9a is a structural layout diagram of a first electrode layer of a driving substrate according to an embodiment of the present application;

[0044] Figure 9b is a structural layout diagram of a first electrode layer and an active layer of a driving substrate according to an embodiment of the present application;

[0045] Figure 9c is a structural layout diagram of a first electrode layer, an active layer and a data line of a driving substrate according to an embodiment of the present application;

[0046] Figure 9d is a structural layout diagram of a first electrode layer, an active layer and a data line of a driving substrate according to an embodiment of the present application;

[0047] Figure 9e is a structural layout diagram of a first electrode layer, an active layer, a pixel electrode and a data line of a driving substrate according to an embodiment of the present application;

[0048] Figure 9f is a structural layout diagram of a driving substrate according to an embodiment of the present application;

[0049] Figure 10 is an equivalent circuit diagram of a circuit unit of a driving substrate according to an embodiment of the present application;

[0050] Figure 11a is a sectional structural diagram of a driving substrate in a capacitor region according to the prior art;

[0051] Figure 11b is a size diagram of a sectional structure of a driving substrate in a capacitor region along A-A' according to an embodiment of the present application;

[0052] Figure 11c is a size diagram of a sectional structure of a driving substrate in a capacitor region along A-A' according to an embodiment of the present application;

[0053] Figure 12a is a structural diagram of forming a first electrode material layer in a first driving substrate preparation method according to an embodiment of the present application;

[0054] Figure 12b is a structural diagram of forming a first electrode layer in a first driving substrate preparation method according to an embodiment of the present application;

[0055] Figure 12c is a structural diagram of forming a gate insulating layer and an active layer in a first driving substrate preparation method according to an embodiment of the present application;

[0056] Figure 12d is a structural schematic diagram of forming a second electrode layer in the first preparation method of the driving substrate according to an embodiment of the present application;

[0057] Figure 12e is a structural schematic diagram of forming an organic layer in the first preparation method of the driving substrate according to an embodiment of the present application;

[0058] Figure 12f is a structural schematic diagram of forming a passivation insulating layer in the first preparation method of the driving substrate according to an embodiment of the present application;

[0059] Figure 12g is a structural schematic diagram of forming a third electrode layer in the first preparation method of the driving substrate according to an embodiment of the present application;

[0060] Figure 12h is a structural schematic diagram of forming a transparent electrode layer in the first preparation method of the driving substrate according to an embodiment of the present application;

[0061] Figure 13a is a structural schematic diagram of forming a first electrode material layer in the second preparation method of the driving substrate according to an embodiment of the present application;

[0062] Figure 13b is a structural schematic diagram of forming a first electrode layer including a second conductive film layer in the second preparation method of the driving substrate according to an embodiment of the present application;

[0063] Figure 13c is a structural schematic diagram of forming a gate insulating layer in the second preparation method of the driving substrate according to an embodiment of the present application;

[0064] Figure 13d is a structural schematic diagram of forming a second electrode layer and an active layer in the second preparation method of the driving substrate according to an embodiment of the present application;

[0065] Figure 13e is a structural schematic diagram of forming an organic layer in the second preparation method of the driving substrate according to an embodiment of the present application;

[0066] Figure 13f is a structural schematic diagram of forming a passivation insulating layer in the second preparation method of the driving substrate according to an embodiment of the present application;

[0067] Figure 13g is a structural schematic diagram of forming a third electrode layer in the second preparation method of the driving substrate according to an embodiment of the present application;

[0068] Figure 13his a structural diagram of forming a transparent electrode layer in a second preparation method of a driving substrate according to an embodiment of the present application;

[0069] Figure 14a is a structural diagram of forming a first electrode layer in a third preparation method of a driving substrate according to an embodiment of the present application;

[0070] Figure 14b is a structural diagram of forming a gate insulating layer in the third preparation method of the driving substrate according to the embodiment of the present application;

[0071] Figure 14c is a structural diagram of forming a second electrode sub-pattern in the third preparation method of the driving substrate according to the embodiment of the present application;

[0072] Figure 14d is a structural diagram of forming a first conductive film layer in the third preparation method of the driving substrate according to the embodiment of the present application;

[0073] Figure 14e is a structural diagram of forming a passivation insulating layer in the third preparation method of the driving substrate according to the embodiment of the present application;

[0074] Figure 14f is a structural diagram of forming a third electrode layer in the third preparation method of the driving substrate according to the embodiment of the present application;

[0075] Figure 15a is a structural diagram of forming a first electrode pattern and a second conductive film layer in a fourth preparation method of a driving substrate according to an embodiment of the present application;

[0076] Figure 15b is a structural diagram of forming a gate insulating layer in the fourth preparation method of the driving substrate according to the embodiment of the present application;

[0077] Figure 15c is a structural diagram of forming a second electrode sub-pattern in the fourth preparation method of the driving substrate according to the embodiment of the present application;

[0078] Figure 15d is a structural diagram of forming a first conductive film layer in the fourth preparation method of the driving substrate according to the embodiment of the present application;

[0079] Figure 15e is a structural diagram of forming a passivation insulating layer in the fourth preparation method of the driving substrate according to the embodiment of the present application;

[0080] Figure 15f is a structural diagram of forming a third electrode layer in the fourth preparation method of the driving substrate according to the embodiment of the present application.

[0081] Explanation of reference numerals: 0, substrate; 1, first electrode material layer; 11, first electrode pattern; 12, second conductive film layer; 13, hollow structure; 131, hollow substructure; 14, gate pattern; 2, gate insulating layer; 3, active layer; 4, second electrode layer; 41, second electrode sub-pattern; 42, first conductive film layer; 5, organic layer; 6, passivation insulating layer; 7, third electrode layer; 8, transparent electrode layer; A1, switching region; A2, capacitance region; 101, gate signal electrode; 102, first signal electrode input; 103, second signal electrode input; 200, active layer; 300, gate insulating via; 401, signal electrode; 402, VCOM electrode; 500, organic film via; 600, second via; 700, third electrode layer; 800, transparent electrode layer. DETAILED DESCRIPTION

[0082] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0083] In the drawings, the size of the constituent elements, the thickness of the layers, or the region may be exaggerated for the sake of clearness and convenience in some cases. Therefore, any one of the implementations of the present disclosure is not necessarily limited to the size shown in the drawings. The shapes and the sizes of the components in the drawings do not reflect the true proportions of the components. Furthermore, the drawings schematically show ideal examples, and any one of the implementations of the present disclosure is not limited to the shapes or the values shown in the drawings.

[0084] Electronic Paper Display (EPD) is a paper-like display technology developed earlier, which is to use the charged ball with color to move in the liquid environment by the external electric field to show the display effect of different colors. The electrophoresis technology has several advantages, one is low energy consumption, because of the bistable characteristics, the image can be kept on the display for several days or months after the power is off; two is that the display produced by electrophoresis technology is reflective, so it has good sunlight readability, and it can also be combined with the front or side light together for dark environment; three is the potential of low production cost, because the technology does not need strict packaging, and it is feasible to use solution processing technology such as printing; four is that the electrophoretic display is characterized by flexible shape factor, allowing them to be manufactured on plastic, metal or glass surface, so it is the best choice for flexible display technology. With the progress of science and technology, EPD will gradually be applied to electronic readers, ink screen labels, electronic notebooks, ink screen mobile phones, ink screen transportation, electronic paper wear, ink screen education, ink screen medical treatment and other smart applications and Internet of Things applications.

[0085] In the related art, the design of the driving substrate of the EPD display is quite different from the design of the driving substrate of the ordinary LCD display. In order to maintain the bistability of the EPD, a double-layer storage capacitor (DL-Cst) needs to be designed in the circuit of the EPD driving substrate. The conventional double-capacitor design usually connects the upper and lower two metal electrodes to form an upper and lower double-layer capacitor opposite to the middle metal electrode. However, the three-layer metal electrodes in the existing double-capacitor design are all in a block surface structure, and the metal stress is accumulated in the pixel electrode, which causes the film layer on it, such as the transparent electrode layer, to fall off due to stress release, and even the transparent electrode layer of the entire pixel.

[0086] Therefore, an embodiment of the present application provides a driving substrate, Figure 1 A cross-sectional structure along A-A' of the driving substrate provided by an embodiment of the present application is shown in the figure, Figure 1As shown, the driving substrate includes a switching area A1 and a capacitor area A2 arranged at least one side of the switching area A1, the switching area A1 is used to form a thin film transistor TFT on the driving substrate, and the capacitor area A2 is used to form a double-layer storage capacitor (DL-Cst) on the driving substrate. In the embodiment of the present application, the driving substrate includes: a substrate 0; a first electrode layer, a second electrode layer 4 and a third electrode layer 7 arranged in sequence on one side of the substrate 0, and the first electrode layer is arranged close to the substrate 0. Wherein, the second electrode layer 4 and the first electrode layer at least partially overlap in the orthographic projection on the substrate 0, so that the second electrode layer 4 and the first electrode layer form a first capacitor; and the third electrode layer 7 and the second electrode layer 4 at least partially overlap in the orthographic projection on the substrate 0, so that the second electrode layer 4 and the third electrode layer 7 form a second capacitor.

[0087] In the case of the electrode layer of the capacitor area A2 being a flat electrode layer with a block-shaped surface structure, a large amount of metal stress will accumulate between the layers, causing the transparent electrode layer on the first electrode layer, the second electrode layer and the third electrode layer forming the double capacitor in the driving substrate to fall off due to stress release, and in severe cases, the transparent electrode layer of the entire pixel will fall off. In order to avoid the above problems, in the embodiment of the present application, the first electrode layer includes a plurality of first electrode patterns 11 arranged at intervals in the capacitor area A2, each first electrode pattern 11 includes a first ramp area, and the thickness of the first electrode pattern 11 gradually decreases in the first direction at the first ramp area, and the first direction is the direction of the center region of the first electrode pattern 11 pointing to the edge of the first electrode pattern 11.

[0088] It should be noted that the thickness mentioned in the embodiment of the present application refers to the height difference of the two side surfaces of the film layer along the arrangement direction of the first electrode layer, the second electrode layer 4 and the third electrode layer 7.

[0089] In the embodiment of the present application, the first electrode pattern 11 of the first electrode layer is set to have a slope pattern, and there is a gap between adjacent first electrode patterns 11, so that the first electrode layer avoids forming a large block of metal electrode, and the stress of the metal electrode of the first electrode layer is released through the gap between the adjacent first electrode patterns 11, effectively improving the problem of the transparent electrode layer on the electrode layer falling off due to stress pulling; in the flexible application scenario, the damage of the pixel electrode caused by bending can be reduced, the bendability and reliability of the flexible electronic paper can be improved, and the product competitiveness can be improved.

[0090] In another aspect, in the embodiment of the present application, the thickness of the first electrode pattern 11 gradually changes in the first ramp region, and the thickness of the first electrode pattern 11 gradually decreases along the first direction, so that the second electrode layer 4 and the third electrode layer 7 formed on the side of the first electrode layer away from the substrate 0 are affected by the shape of the first electrode pattern 11, and a wavy structure is formed, thereby increasing the projection overlap area between the second electrode layer 4 and the first electrode pattern 11 of the first electrode layer, and the projection overlap area between the second electrode layer 4 and the third electrode layer 7, which can effectively increase the capacitance values of the first and second capacitances, and meet the requirements of higher specifications of electrophoretic display driving. In addition, the first electrode pattern 11 with the first ramp region can reduce the reflection of EPD display and improve the image quality of EPD.

[0091] In some optional embodiments, the material of the substrate can be a glass substrate or a flexible substrate. Optionally, the glass material of the glass substrate can be alkali-free glass, alkali-containing glass, and strengthened glass, and the material of the flexible substrate can be a composite material of YPI and silicon dioxide.

[0092] In some optional embodiments, Figure 7a A top view structural schematic diagram of an embodiment of the present application is shown, which shows a driving substrate in which a first electrode layer in a capacitor region is provided with a hollow structure extending in a fourth direction, as shown in Figure 7a As shown, the plurality of first electrode patterns 11 are arranged at intervals along a third direction, and the gap between adjacent first electrode patterns 11 forms a hollow structure 13 extending in a fourth direction. The adjacent first electrode patterns 11 are isolated by the hollow structure 13, and the adjacent first electrode patterns 11 are connected to each other at the edges of the hollow structure 13 between the adjacent first electrode patterns 11. In the embodiment of the present application, the stress in the first electrode layer is released by the hollow structure 13. The third direction is the arrangement direction of the switching region and the capacitor region, and the fourth direction is perpendicular to the third direction.

[0093] In some optional embodiments, Figure 8a A top view structural schematic diagram of an embodiment of the present application is shown, which shows a driving substrate in which a first electrode layer in a capacitor region is provided with a hollow substructure arranged at intervals in a fourth direction, as shown in Figure 8aAs shown, the plurality of first electrode patterns 11 are arranged along the third direction with gaps between adjacent first electrode patterns 11 forming a hollow structure 13. In order to ensure that the hollow structure 13 can release the stress of the first electrode layer while improving the area of the electrode material of the first electrode layer and ensuring the performance of the first electrode layer, the hollow structure 13 includes a plurality of hollow substructures 131 arranged along the fourth direction, and the gap between adjacent hollow substructures 131 in the fourth direction is provided with the electrode material of the first electrode layer, thereby effectively improving the area of the electrode material of the first electrode layer and ensuring the performance of the first electrode layer.

[0094] In some optional embodiments, Figure 11b A size schematic diagram of a cross-sectional structure of a driving substrate along A-A' according to an embodiment of the present application is shown in FIG. 4. As shown in FIG. 4, the driving substrate includes a substrate 10, a first electrode layer 1, a second electrode layer 2, and a transparent electrode layer 3. Figure 11b As shown, in order to ensure that the first ramp area of the first electrode pattern 11 can effectively improve the capacitance value, the maximum thickness of the first electrode pattern 11 is greater than or equal to 500 nm, and the maximum thickness refers to the thickness of the ramp area of the first electrode pattern 11 close to the side of the central region of the first electrode pattern 11. The slope angle θ of the first ramp area of the first electrode pattern 11 is less than or equal to 40°. Optionally, the cross-sectional shape of the first electrode pattern 11 along the first plane is a trapezoidal shape, a triangular shape, or other irregular shapes, and the first plane is a plane perpendicular to the surface of the substrate 10 and extending along the arrangement direction of the plurality of first electrode patterns 11.

[0095] In some optional embodiments, the material of the first electrode layer includes but is not limited to single metals (such as copper, aluminum, molybdenum, etc.) and metal alloys (such as molybdenum niobium, molybdenum nickel titanium alloy, etc.), etc. Since the cross section of copper metal is relatively regular, it is beneficial for the first electrode pattern 11 of the first electrode layer to form a surface with a regular first ramp area, and therefore the material of the first electrode layer is preferably copper metal.

[0096] In some optional embodiments, since the plurality of first electrode patterns 11 with gaps can release the stress of the first electrode layer and prevent the transparent electrode layer of the capacitance area A2 from falling off, the area between the gaps of the adjacent first electrode patterns 11 cannot form a capacitance with the second electrode layer, which affects the improvement of the capacitance value of the double-layer capacitance. Figure 2 A cross-sectional structure schematic diagram of a driving substrate provided with a second conductive film layer along A-A' according to an embodiment of the present application is shown in FIG. 5. As shown in FIG. 5, the driving substrate includes a substrate 10, a first electrode layer 1, a second electrode layer 2, and a transparent electrode layer 3. Figure 2As shown, the first electrode layer further comprises a second conductive film layer 12, which is arranged between the first electrode pattern 11 and the second electrode layer 4, and covers the plurality of first electrode patterns 11 and the gaps between adjacent first electrode patterns 11, and the thickness of the second conductive film layer 12 is less than the maximum thickness of the first electrode pattern 11. In the embodiment of the present application, by arranging the second conductive film layer 12 between the first electrode pattern 11 and the second electrode layer 4, the gaps between the first electrode patterns 11 are filled, so that when the second electrode layer 4 forms a first capacitor with the first electrode layer, the first capacitor can be formed with the second conductive film layer 12 covering the first electrode pattern 11 and the gaps between the first electrode patterns 11, effectively increasing the projection overlap area of the first electrode layer and the second electrode layer, and improving the capacitance value of the first capacitor without affecting the structure of the first electrode pattern 11 and the gaps.

[0097] In some optional embodiments, the material of the second conductive film layer 12 includes but is not limited to transparent conductive oxide material (such as ITO material), metal material (such as metal Mo material). Optionally, the thickness of the second conductive film layer 12 is greater than or equal to 50 nm and less than or equal to 150 nm.

[0098] In some optional embodiments, Figure 7b A top view structural schematic diagram of a first electrode layer provided with a second conductive film layer in a driving substrate and provided with a hollow structure extending along a fourth direction in a capacitor region is shown, as shown in FIG. 6. Figure 7b As shown, the plurality of first electrode patterns 11 are arranged at intervals along the third direction, and the gaps between adjacent first electrode patterns 11 form a hollow structure 13 extending along the fourth direction, which separates adjacent first electrode patterns 11, and adjacent first electrode patterns 11 are connected to each other at the edges of the hollow structure 13 between adjacent first electrode patterns 11, and the second conductive film layer 12 covers the first electrode patterns 11 and the plurality of hollow structures 13.

[0099] In some optional embodiments, Figure 8b A top view structural schematic diagram of a first electrode layer provided with a second conductive film layer in a driving substrate and provided with a hollow substructure extending along a fourth direction at intervals is shown, as shown in FIG. 7. Figure 8bAs shown, the plurality of first electrode patterns 11 are arranged along the third direction with intervals, and the gaps between adjacent first electrode patterns 11 form a hollow structure 13. In order to ensure that the hollow structure 13 can release the stress of the first electrode layer while improving the area of the electrode material of the first electrode layer and ensuring the performance of the first electrode layer, the hollow structure 13 includes a plurality of hollow substructures 131 arranged along the fourth direction, and the second conductive film layer 12 covers the first electrode patterns 11 and the plurality of hollow substructures 131.

[0100] In some optional embodiments, the second electrode layer 4 includes a second electrode pattern arranged in the capacitor region A2, the second electrode pattern is insulated from the first electrode layer, and the second electrode pattern is insulated from the third electrode layer 7. The second electrode pattern is used to form a first capacitor with the first electrode layer and a second capacitor with the third electrode layer 7. The orthographic projection of the second electrode pattern on the substrate 0 covers at least the orthographic projection of the plurality of first electrode patterns 11 and the gaps between adjacent first electrode patterns 11 on the substrate 0. Optionally, the material of the second electrode layer 4 includes but is not limited to single metal (such as copper, aluminum, molybdenum, etc.) and metal alloy (such as molybdenum niobium, molybdenum nickel titanium alloy, etc.), and the thickness of the second electrode pattern of the second electrode layer is greater than or equal to 200 nm and less than or equal to 500 nm.

[0101] In some optional embodiments, the second electrode layer 4 further includes a source-drain electrode pattern covering the substrate 0 in the switching region A1 and extending to the capacitor region A2. The source-drain electrode pattern is arranged in the same layer as the second electrode pattern and is insulated from each other. The source-drain electrode pattern is provided with a first via in the capacitor region A2, and the source-drain electrode pattern and the first electrode layer are electrically connected through the first via.

[0102] In some optional embodiments, the third electrode layer 7 is a block-shaped metal structure, and the orthographic projection of the third electrode layer 7 on the substrate 0 covers the switching region A1 and the capacitor region A2. By covering the thin film transistor in the switching region A1 with the third electrode layer 7, the problem of large photo-induced leakage current caused by light exposure is effectively avoided. Optionally, the material of the third electrode layer 7 is single metal (such as copper, aluminum, molybdenum, etc.) and metal alloy (such as molybdenum niobium, molybdenum nickel titanium alloy, etc.), and is preferably molybdenum. The thickness of the third electrode layer 7 is greater than or equal to 100 nm and less than or equal to 200 nm.

[0103] In some optional embodiments, the first electrode layer further comprises a gate pattern 14 disposed in the switching region A1, and the gate pattern 14 is disposed in the same layer as the first electrode pattern 11. The driving substrate further comprises a gate insulating layer 2 disposed between the first electrode layer and the second electrode layer 4, and an active layer 3 disposed in the switching region A1 on the side of the gate pattern 14 away from the substrate 0, between the source-drain electrode pattern of the second electrode layer 4 and the gate pattern 14. Optionally, the material of the gate insulating layer 2 can be SiN x , SiO2, the film layer thickness of the gate insulating layer 2 is greater than or equal to 300 nm and less than or equal to 400 nm, and the material of the active layer 3 can be amorphous silicon or metal oxide semiconductor material.

[0104] In some optional embodiments, the driving substrate further comprises a passivation insulating layer 6 disposed between the second electrode layer 4 and the third electrode layer 7, and the orthographic projection of the passivation insulating layer 6 on the substrate 0 covers the capacitor region A2 and the switching region A1. Optionally, the film layer material of the passivation insulating layer 6 can be SiN x , SiO2, the film layer thickness of the passivation insulating layer 6 is greater than or equal to 200 nm and less than or equal to 400 nm.

[0105] Optionally, the passivation insulating layer 6 is provided with a second via hole in the capacitor region A2, and the orthographic projection of the second via hole on the substrate 0 at least partially overlaps with the orthographic projection of the first via hole on the substrate 0, so that the first via hole and the second via hole form a sleeve hole structure, and the third electrode layer 7 and the first electrode layer are electrically connected through the first via hole and the second via hole. In addition, the third electrode layer 7 covers the surface of the side of the second via hole away from the substrate 0, so as to prevent the metal of the first electrode layer from being corroded due to the penetration of etching liquid.

[0106] In the embodiments of the present application, Figure 10 a circuit unit equivalent circuit diagram of a driving substrate is shown, as Figure 10 shown, the capacitor region A2 of the driving substrate forms a double-layer capacitor, which is a first capacitor Cst1 and a second capacitor Cst2, and the first capacitor, the second capacitor and an electronic paper capacitor (Cepl) for driving the electronic paper display are in parallel with each other. Figure 11a a cross-sectional structure schematic diagram of a capacitor region of a driving substrate in the prior art is shown, Figure 11b a size schematic diagram of a cross-sectional structure of a capacitor region of a driving substrate along A-A' according to an embodiment of the present application is shown, Figure 11cA schematic diagram of the cross-sectional structure of a driving substrate provided with a second conductive film layer in the capacitor region along the line A-A' is shown in FIG. Figures 11a-11c , the capacitance enhancement effect of the driving substrate proposed in the embodiment of the present application is described in detail:

[0107] for Figure 11a The capacitance of the conventional double-layer storage capacitor shown is calculated according to the following formula:

[0108]

[0109] Among them, Cst A for Figure 11a The capacitance value of the storage capacitor shown is shown; ε1 is the dielectric constant of the gate insulating layer, ε2 is the dielectric constant of the passivation insulating layer, d1 is the dielectric constant of the gate insulating layer, d2 is the dielectric constant of the passivation insulating layer, k is the electrostatic force constant, S is the relative area of ​​the double-layer capacitor storage, and the area of ​​the capacitor with a side length of L is substituted into the above formula (1) to obtain the following formula (2), which is then sorted out to obtain formula (3):

[0110]

[0111]

[0112] for Figure 11b In the embodiment of the present application shown, a double-layer storage capacitor formed by a first electrode pattern 11 is provided. Assuming that there are M columns of the first electrode pattern 11 of the storage capacitor, the capacitance value thereof is calculated according to the following formula:

[0113]

[0114] Substituting formula (5) into formula (4), we can obtain:

[0115]

[0116] If you want to implement Cst B Cst A Big, that is, Cst B >Cst A ,that is:

[0117]

[0118] get:

[0119]

[0120] At the same time, we can also know:

[0121] L=M(2w1+w0+s) Formula (9)

[0122] Substitute equation (9) into equation (8), we can get:

[0123]

[0124] wherein w1 is the horizontal width (line width) of the first ramp region in the first electrode pattern, w0 is the width of the center region of the first electrode pattern, θ is the slope angle of the first ramp region, and s is the gap width (line space) between adjacent first electrode patterns.

[0125] From the above, the gap s of the first electrode pattern 11 is designed to satisfy the above relationship, and the corresponding Figure 11b capacitance of the driving substrate in the embodiment of the present application is larger than that of the existing storage capacitor scheme corresponding to Figure 11a

[0126] In the case where the slope angle θ of the first ramp region of the first electrode pattern 11 is less than or equal to 40°, the equation (10) relationship is simplified as:

[0127] s < w1

[0128] Exemplarily, in the embodiment of the present application, the horizontal width w of the first electrode pattern 11 is greater than or equal to 3 μm and less than or equal to 5 μm, and the gap width s between adjacent first electrode patterns 11 is less than the horizontal width w of the first electrode pattern 11. For example, the horizontal width w of the first electrode pattern 11 is 4 μm, and the gap width s between adjacent first electrode patterns 11 is 3 μm, which can ensure that the capacitance of the driving substrate is effectively improved compared with the capacitance of the existing capacitor.

[0129] For the double-layer storage capacitor formed by the second conductive film layer 12 and the first electrode pattern 11 shown in the embodiment of the present application, the capacitance value is calculated according to the following formula: Figure 11c

[0130] Because cos θ ≤ 1, it can be seen from equation (13) that:

[0131]

[0132] Therefore, it can be confirmed that from the above capacitance relationship (14), the capacitance of the driving substrate in the embodiment of the present application corresponding to

[0133] is larger than that of the existing storage capacitor scheme corresponding to Figure 11c Figure 11a ​​The capacitance of the drive substrate is greater than that of the existing storage capacitor solution and is not related to the line width w1 and line spacing s of the first electrode pattern 11. Exemplarily, the horizontal width w of the first electrode pattern 11 is greater than or equal to 3 μm and less than or equal to 5 μm, and the gap width s between adjacent first electrode patterns 11 is less than the horizontal width w of the first electrode pattern 11. For example, the horizontal width w of the first electrode pattern 11 is 4 μm, and the gap width s between adjacent first electrode patterns 11 is 3 μm, which can ensure that the capacitance of the drive substrate is effectively improved compared to the capacitance of the existing capacitor.

[0134] In some optional implementations, in order to further increase the second capacitor in the driver backplane, Figure 3 FIG. 1 shows a schematic cross-sectional structure diagram of a driving substrate provided with a second conductive sub-pattern in a capacitor region along line AA′, as shown in FIG. Figure 3 As shown, the second electrode pattern includes a plurality of second electrode sub-patterns 41, and the plurality of second electrode sub-patterns 41 are arranged alternately with the plurality of first electrode patterns 11; the orthographic projection of the second electrode sub-pattern 41 on the base substrate 0 covers the orthographic projection of the gap between adjacent first electrode patterns 11 on the base substrate 0, and the orthographic projection of the second electrode sub-pattern 41 on the base substrate 0 partially overlaps with the orthographic projection of the adjacent first electrode pattern 11 on the base substrate 0.

[0135] Specifically, each second electrode sub-pattern 41 includes a second climbing region, and the thickness of the second electrode sub-pattern 41 in the second climbing region gradually decreases along a second direction. The maximum thickness of the second electrode sub-pattern 41 is the same as the maximum thickness of the first electrode pattern 11. The second direction is the direction from the center area of ​​the second electrode sub-pattern to the edge of the second electrode sub-pattern. In the embodiment of the present application, because the thickness of the second climbing region of the second electrode sub-pattern 41 gradually changes, the thickness of the second electrode sub-pattern 41 in the second climbing region gradually decreases along the second direction, which increases the projected overlapping area between the second electrode sub-pattern 41 and the third electrode layer 7, and can effectively increase the capacitance value of the second capacitor.

[0136] In some optional embodiments, the maximum thickness of the second electrode sub-pattern 41 is greater than or equal to 500 nm, and the slope angle θ of the second climbing region of the second electrode sub-pattern 41 is less than or equal to 40°. Optionally, the cross-sectional shape of the second electrode sub-pattern 41 along the first plane is a trapezoid, a triangle, or other irregular shape.

[0137] In some optional embodiments, the material of the second electrode sub-pattern 41 includes but is not limited to single metal (such as copper, aluminum, molybdenum, etc.) and metal alloy (such as molybdenum-niobium, molybdenum-nickel-titanium alloy, etc.), etc. Since the cross section of copper metal is relatively regular, the material of the second electrode sub-pattern 41 is preferably copper metal, which is conducive to forming a surface with a regular second ramp area for the second electrode sub-pattern 41.

[0138] Optionally, as shown in Figure 3 the second electrode layer 4 further includes a first conductive film layer 42, the first conductive film layer 42 is arranged between the second electrode sub-pattern 41 and the third electrode layer 7, the first conductive film layer 42 covers the plurality of second electrode sub-patterns 41 and the gaps between adjacent second electrode sub-patterns 41, and the thickness of the first conductive film layer 42 is less than the maximum thickness of the second electrode sub-pattern 41. In the embodiment of the present application, by arranging the first conductive film layer 42 to fill the gaps between the second electrode sub-patterns 41, when the second electrode layer 4 and the third electrode layer 7 form a second capacitor, the second capacitor can be formed with the first conductive film layer 42 covering the second electrode sub-patterns 41 and the gaps between the second electrode sub-patterns 41, effectively increasing the projection overlap area of the second electrode layer and the third electrode layer, while not affecting the structure of the second electrode sub-patterns 41 and the gaps, and improving the capacitance value of the second capacitor.

[0139] Further, Figure 4 a cross-sectional structure diagram of a driving substrate provided with a second conductive film layer and a second conductive sub-pattern along A-A' in a capacitor area is shown, as shown in Figure 4 the first electrode layer is provided with the first electrode pattern 11 and the second conductive film layer 12, and the second electrode layer 4 is provided with the second electrode sub-pattern 41 and the first conductive film layer 42. By means of the first electrode pattern 11 with a ramp area and the second electrode sub-pattern 41, the projection overlap area of the first electrode layer and the second electrode layer 4 and the projection overlap area of the second electrode layer 4 and the third electrode layer 7 are effectively improved. At the same time, the second conductive film layer 12 and the first conductive film layer 42 are respectively used to ensure that the gaps between adjacent first electrode patterns 11 and the gaps between adjacent second electrode sub-patterns will not cause the capacitance value to decrease, thereby effectively realizing the capacitance value improvement of the double capacitors of the driving substrate.

[0140] In some optional embodiments, the material of the first conductive film layer 42 includes but is not limited to transparent conductive oxide material (such as ITO material) and metal material (such as metal Mo material). Optionally, the thickness of the first conductive film layer 42 is greater than or equal to 50 nm and less than or equal to 150 nm.

[0141] Figure 5 Fig. 2 shows a schematic diagram of a cross-section of an electron microscope of a driving substrate with a second conductive film layer and a second conductive pattern in a capacitor region according to an embodiment of the present application, Figure 6 Fig. 2 shows a schematic diagram of a cross-section of an electron microscope of a driving substrate with a second conductive film layer and a second conductive pattern in a capacitor region according to an embodiment of the present application, Figure 5 and Figure 6 As shown in Figs. 1 and 2, in the case that the maximum thickness of the first electrode pattern 11 and the second electrode sub-pattern 41 is greater than or equal to 500 nm, the projection overlapping area of the third electrode layer 7 and the second electrode layer 4, and the projection overlapping area of the second electrode layer 4 and the first electrode layer can be significantly increased, and the first capacitor and the second capacitor can be effectively improved.

[0142] In some optional embodiments, the driving substrate further comprises a transparent electrode layer 8, which is arranged on the side of the third electrode layer 7 away from the substrate 0 and covers the third electrode layer 7 entirely, forming a block structure with the same size as the pixel. Optionally, the material of the transparent electrode layer 8 can be metal oxide material, and the thickness of the transparent electrode layer 8 is greater than or equal to 20 nm and less than or equal to 60 nm. For example, the material of the transparent electrode layer 8 is ITO material, and the thickness of the transparent electrode layer 8 is 40 nm.

[0143] In some optional embodiments, Figure 9a Fig. 3 shows a schematic diagram of a structure layout of a first electrode layer in a driving substrate according to an embodiment of the present application, Figure 9b Fig. 4 shows a schematic diagram of a structure layout of a first electrode layer and an active layer in a driving substrate according to an embodiment of the present application, Figure 9c Fig. 5 shows a schematic diagram of a structure layout of a first electrode layer, an active layer and a data line in a driving substrate according to an embodiment of the present application, Figure 9d Fig. 6 shows a schematic diagram of a structure layout of a first electrode layer, an active layer and a data line containing a second conductive film layer in a driving substrate according to an embodiment of the present application, Figure 9e Fig. 7 shows a schematic diagram of a structure layout of a first electrode layer, an active layer, a pixel electrode and a data line containing a second conductive film layer in a driving substrate according to an embodiment of the present application, Figure 9f Fig. 8 shows a schematic diagram of a structure layout of a driving substrate according to an embodiment of the present application, Figures 9a-9fAs shown, the driving substrate comprises: a gate signal electrode 101; a first signal electrode input 102 and a second signal electrode input 103 connected through a gate insulation layer via hole 300; an active layer 200; a gate insulation via hole 300; a signal electrode 401; a VCOM electrode 402; an organic film via hole 500; a second via hole 600; a third electrode layer 700; and a transparent electrode layer 800.

[0144] The application provides a driving substrate, comprising a switching area and a capacitor area arranged on at least one side of the switching area, and the driving substrate comprises: a substrate substrate; a first electrode layer, a second electrode layer and a third electrode layer sequentially stacked and arranged on one side of the substrate substrate, the first electrode layer is arranged close to the substrate substrate, the second electrode layer and the first electrode layer are at least partially overlapped in the orthographic projection on the substrate substrate, and the third electrode layer and the second electrode layer are at least partially overlapped in the orthographic projection on the substrate substrate; wherein the first electrode layer comprises a plurality of first electrode patterns arranged at intervals in the capacitor area, each first electrode pattern comprises a first ramping area, the thickness of the first electrode pattern gradually decreases in the first ramping area, and the first direction is the direction in which the central region of the first electrode pattern points to the edge of the first electrode pattern. The application forms the second electrode layer and the third electrode layer on the first electrode pattern by arranging the first electrode pattern with the first ramping area, increases the overlapping area between the electrode layers by using the ramping structure of the first electrode pattern, thereby effectively increasing the capacitance of the double-layer capacitor, releasing the stress of the large metal electrode of the double-layer capacitor, and improving the problem of electrode layer falling off caused by stress pulling.

[0145] Based on the same inventive concept, the application discloses a preparation method of a driving substrate, which comprises the following steps: providing a substrate substrate; sequentially forming a first electrode layer, a second electrode layer and a third electrode layer which are stacked and arranged on one side of the substrate substrate, the first electrode layer is arranged close to the substrate substrate, the second electrode layer and the first electrode layer are at least partially overlapped in the orthographic projection on the substrate substrate, and the third electrode layer and the second electrode layer are at least partially overlapped in the orthographic projection on the substrate substrate.

[0146] Wherein, the first electrode layer comprises a plurality of first electrode patterns arranged at intervals in the capacitor area, each first electrode pattern comprises a first ramping area, the thickness of the first electrode pattern gradually decreases in the first ramping area, and the first direction is the direction in which the central region of the first electrode pattern points to the edge of the first electrode pattern.

[0147] In some optional embodiments, Figure 12aA structural diagram of forming a first electrode material layer in the first driving substrate preparation method is shown, Figure 12b A structural diagram of forming a first electrode layer in the first driving substrate preparation method is shown, Figure 12c A structural diagram of forming a gate insulating layer and an active layer in the first driving substrate preparation method is shown, Figure 12d A structural diagram of forming a second electrode layer in the first driving substrate preparation method is shown, Figure 12e A structural diagram of forming an organic layer in the first driving substrate preparation method is shown, Figure 12f A structural diagram of forming a passivation insulating layer in the first driving substrate preparation method is shown, Figure 12g A structural diagram of forming a third electrode layer in the first driving substrate preparation method is shown, Figure 12h A structural diagram of forming a transparent electrode layer in the first driving substrate preparation method is shown, Figures 12a-12h As shown in the figure, the driving substrate is prepared according to the following steps:

[0148] First, a substrate 0 is provided; a first electrode material layer 1 is formed on the substrate 0, and a first electrode layer is formed by magnetron sputtering film formation, the first electrode layer includes a plurality of first electrode patterns 11 located in the capacitor area A2 and a gate pattern 14 located in the switching area; a gate insulating layer 2 of inorganic non-metal film and an active layer material are plated on the first electrode layer by chemical vapor deposition, and the active layer 3 is formed by a photoetching process; the second electrode layer 4 is formed by magnetron sputtering film formation, the second electrode layer 4 includes a data signal line, a source-drain electrode pattern and a second electrode pattern, the second electrode pattern is a block structure; the source-drain electrode pattern is provided with a first via in the capacitor area, the first via penetrates the source-drain electrode pattern and the gate insulating layer 2, and the source-drain electrode pattern is electrically connected to the first electrode layer through the first via.

[0149] A layer of organic film material is coated on the side of the second electrode layer 4 facing away from the base substrate 0 by a slit or suspended coating method, and the thickness of the organic film material is approximately in the range of 2.0μm to 6.0μm, preferably 3.0μm; after film formation, the organic film thin film is pre-cured under certain temperature conditions, the temperature is preferably 100-110°C, and the pre-curing time is preferably 60 seconds; after development is completed, the organic film layer is subjected to an annealing and curing process, the temperature range is 200-250°C, preferably 230°C; the organic layer material of the switching area A1 is retained to form the organic layer 5, and the organic layer material located in the capacitor area A2 is developed and removed to expose the second electrode pattern of the capacitor area A2.

[0150] Subsequently, the passivation insulating layer 6 is formed by chemical vapor deposition, and a source-drain electrode pattern connected to the second electrode layer 4 and a second via hole of the first via hole are manufactured using a photolithography process, and the first via hole and the second via hole form a sleeve hole structure; the third electrode layer 7 is formed by magnetron sputtering, and the third electrode layer 7 covers the entire surface of the passivation insulating layer 6 to form a block structure; finally, a transparent electrode layer 8 is formed on the side of the third electrode layer 7 away from the base substrate 0 using a photolithography process, and the transparent electrode layer 8 is a block structure.

[0151] In some optional embodiments, Figure 13a A schematic structural diagram of forming a first electrode material layer in a second method for preparing a drive substrate according to an embodiment of the present application is shown; Figure 13b A schematic structural diagram of forming a first electrode layer including a second conductive film layer in a second method for preparing a drive substrate proposed in an embodiment of the present application is shown; Figure 13c A schematic structural diagram of forming a gate insulating layer in a second method for preparing a drive substrate according to an embodiment of the present application is shown; Figure 13d A schematic structural diagram of forming a second electrode layer and an active layer in a second method for preparing a drive substrate according to an embodiment of the present application is shown; Figure 13e A schematic structural diagram of forming an organic layer in a second method for preparing a drive substrate according to an embodiment of the present application is shown; Figure 13f A schematic structural diagram of forming a passivation insulating layer in a second method for preparing a drive substrate according to an embodiment of the present application is shown; Figure 13g A schematic structural diagram of forming a third electrode layer in a second method for preparing a drive substrate according to an embodiment of the present application is shown; Figure 13h FIG. 1 shows a schematic structural diagram of forming a transparent electrode layer in a second method for preparing a drive substrate according to an embodiment of the present application. Figures 13a-13h As shown, the driving substrate is prepared according to the following steps:

[0152] Firstly, a substrate 0 is provided; a first electrode material layer 1 is formed on the substrate 0, and a first electrode layer is formed by magnetron sputtering film forming, the first electrode layer includes a plurality of first electrode patterns 11 in the capacitor region A2 and a gate pattern 14 in the switching region; a second conductive film layer 12 is made on the side of the first electrode pattern 11 away from the substrate 0 using a photoetching process; a gate insulating layer 2 of inorganic non-metallic film and an active layer material are plated on the first electrode layer by chemical vapor deposition, and the active layer 3 is formed by a photoetching process; the second electrode layer 4 is formed by magnetron sputtering film forming, the second electrode layer 4 includes a data signal line, a source-drain electrode pattern and a second electrode pattern, the second electrode pattern is a block structure; the source-drain electrode pattern is provided with a first via in the capacitor region, the first via penetrates the source-drain electrode pattern and the gate insulating layer 2, and the source-drain electrode pattern is electrically connected to the first electrode layer through the first via.

[0153] A layer of organic film material is coated on the side of the second electrode layer 4 away from the substrate 0 by a slit or a suspension coating method, the thickness of the organic film material ranges from about 2.0 μm to 6.0 μm, preferably 3.0 μm; after film forming, the organic film is pre-cured under certain temperature conditions, the temperature is preferably 100-110°C, and the pre-curing time is preferably 60 seconds; after development, the organic film layer is annealed and cured, the temperature ranges from 200-250°C, preferably 230°C; the organic layer 5 is formed by retaining the organic layer material in the switching region A1, and the organic layer material in the capacitor region A2 is developed and removed, exposing the second electrode pattern in the capacitor region A2.

[0154] Subsequently, the passivation insulating layer 6 is formed by chemical vapor deposition plating, a second via is made by a photoetching process, the second via is connected to the source-drain electrode pattern of the second electrode layer 4 and the first via, the first via and the second via form a sleeve hole structure; the third electrode layer 7 is formed by magnetron sputtering film forming, the third electrode layer 7 covers the passivation insulating layer 6 to form a block structure; finally, a transparent electrode layer 8 is formed on the side of the third electrode layer 7 away from the substrate 0 by a photoetching process, the transparent electrode layer 8 is a block structure.

[0155] In some optional embodiments, Figure 14a A structure diagram of forming the first electrode layer in the third preparation method of the driving substrate is shown, Figure 14b A structure diagram of forming the gate insulating layer in the third preparation method of the driving substrate is shown, Figure 14c A structure diagram of forming the second electrode sub-pattern in the third preparation method of the driving substrate is shown, Figure 14dFig. 2 shows a structure diagram of forming the first conductive film layer in the third preparation method of the driving substrate according to an embodiment of the present application, Figure 14e Fig. 3 shows a structure diagram of forming the passivation insulating layer in the third preparation method of the driving substrate according to an embodiment of the present application, Figure 14f Fig. 4 shows a structure diagram of forming the third electrode layer in the third preparation method of the driving substrate according to an embodiment of the present application, Figures 14a-14f As shown in Fig. 1, the driving substrate is prepared according to the following steps:

[0156] First, a substrate 0 is provided; a first electrode layer is formed on the substrate 0 by magnetron sputtering film formation, the first electrode layer includes a plurality of first electrode patterns 11 in the capacitor region A2 and a gate pattern 14 in the switching region; a gate insulating layer 2 of inorganic non-metallic film and an active layer material are plated on the first electrode layer by chemical vapor deposition, and the active layer 3 is formed by a photoetching process; a second electrode sub-pattern 41 is plated on the side of the gate insulating layer 2 away from the substrate 0 and formed by a photoetching process, and a first conductive film layer 42 is formed on the side of the second electrode sub-pattern 41 away from the substrate 0 by a photoetching process.

[0157] A layer of organic film material is coated on the side of the second electrode layer 4 away from the substrate 0 by a slit or a suspension coating method, the thickness of the organic film material is about 2.0 μm to 6.0 μm, preferably 3.0 μm; after film formation, the organic film is pre-cured under certain temperature conditions, the temperature is preferably 100-110°C, and the pre-curing time is preferably 60 seconds; after development, the organic film layer is annealed and cured, the temperature is 200-250°C, preferably 230°C; the organic layer material in the switching region A1 is reserved to form the organic layer 5, and the organic layer material in the capacitor region A2 is developed and removed to expose the second electrode pattern in the capacitor region A2.

[0158] Subsequently, the passivation insulating layer 6 is plated by chemical vapor deposition, a second via hole connected to the source-drain electrode pattern of the second electrode layer 4 and the first via hole are manufactured by a photoetching process, the first via hole and the second via hole form a sleeve hole structure; the third electrode layer 7 is formed by magnetron sputtering film formation, the third electrode layer 7 covers the passivation insulating layer 6 to form a block structure; finally, a transparent electrode layer 8 is formed on the side of the third electrode layer 7 away from the substrate 0 by a photoetching process, the transparent electrode layer 8 is a block structure.

[0159] In some optional embodiments, Figure 15a Fig. 5 shows a structure diagram of forming the first electrode pattern and the second conductive film layer in the fourth preparation method of the driving substrate according to an embodiment of the present application, Figure 15bFIG. 1 shows a schematic structural diagram of forming a gate insulating layer in a fourth method for preparing a driving substrate proposed in an embodiment of the present application. Figure 15c FIG2 shows a schematic structural diagram of forming a second electrode sub-pattern in a fourth method for preparing a drive substrate proposed in an embodiment of the present application. Figure 15d FIG2 shows a schematic structural diagram of forming a first conductive film layer in a fourth method for preparing a drive substrate proposed in an embodiment of the present application. Figure 15e FIG2 shows a schematic structural diagram of forming a passivation insulating layer in a fourth method for preparing a drive substrate proposed in an embodiment of the present application. Figure 15f FIG. 1 shows a schematic structural diagram of forming a third electrode layer in a fourth method for preparing a drive substrate according to an embodiment of the present application. Figures 15a-15f As shown, the driving substrate is prepared according to the following steps:

[0160] First, a base substrate 0 is provided; a first electrode layer is formed on the base substrate 0 by magnetron sputtering, wherein the first electrode layer includes a plurality of first electrode patterns 11 located in the capacitor area A2 and a gate pattern 14 located in the switch area; a second conductive film layer 12 is produced on the side of the first electrode pattern 11 facing away from the base substrate 0 by using a photolithography process; a gate insulating layer 2 and an active layer material of an inorganic non-metallic film are formed by chemical vapor deposition on the first electrode layer, and the active layer 3 is formed by a photolithography process; a second electrode sub-pattern 41 is formed by coating on the side of the gate insulating layer 2 facing away from the base substrate 0 and by using a photolithography process; a first conductive film layer 42 is formed on the side of the second electrode sub-pattern 41 facing away from the base substrate 0 by using a photolithography process.

[0161] A layer of organic film material is coated on the side of the second electrode layer 4 facing away from the base substrate 0 by a slit or suspended coating method, and the thickness of the organic film material is approximately in the range of 2.0μm to 6.0μm, preferably 3.0μm; after film formation, the organic film thin film is pre-cured under certain temperature conditions, the temperature is preferably 100-110°C, and the pre-curing time is preferably 60 seconds; after development is completed, the organic film layer is subjected to an annealing and curing process, the temperature range is 200-250°C, preferably 230°C; the organic layer material of the switching area A1 is retained to form the organic layer 5, and the organic layer material located in the capacitor area A2 is developed and removed to expose the second electrode pattern of the capacitor area A2.

[0162] Subsequently, the passivation insulating layer 6 is formed by chemical vapor deposition, and a source-drain electrode pattern connected to the second electrode layer 4 and a second via hole are manufactured by using a photolithography process, the first via hole and the second via hole forming a sleeve hole structure; the third electrode layer 7 is formed by magnetron sputtering, the third electrode layer 7 covering the passivation insulating layer 6 to form a block structure; finally, a transparent electrode layer 8 is formed on the side of the third electrode layer 7 away from the substrate 0 by using a photolithography process, the transparent electrode layer 8 being a block structure.

[0163] Based on the same inventive concept, the display panel provided in the embodiments of the present application comprises a liquid crystal layer, a counter substrate, and a driving substrate as described in the embodiments of the present application, and the liquid crystal layer is located between the counter substrate and the driving substrate.

[0164] It should be noted that the display device provided in the present application has all the beneficial effects of the driving substrate described in the embodiments of the present application, and thus the display device provided in the present application has all the beneficial effects of the driving substrate, which will not be described here.

[0165] In some optional embodiments, the display panel is an electronic paper display panel, and exemplary examples of the display panel include, but are not limited to, any electronic paper product or component having a display function, such as an ESL (electronic label), an electronic book, an electronic paper notebook, etc., and a person skilled in the art can select the display panel according to the actual use of the display panel, which will not be described here.

[0166] Each of the embodiments in the present specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0167] In the description of the present specification, it should be understood that the terms "center", "thickness", "upper", "lower", "front", "back", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0168] In this application, unless otherwise indicated and / or unless explicitly contradicted by context, the use of the term "about" including when used in a conjugation such as "about shoulder" means that the value significantly close to the stated value. Unless specifically stated otherwise, and / or unless explicitly contradicted by context, in this specification, the use of the term "about" means that the value significantly close to the stated value.

[0169] In this application, unless otherwise explicitly specified and / or unless explicitly contradicted by context, the first feature "on", "above", or "over" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above", and "over" the second feature includes that the first feature is directly above and obliquely above the second feature, or only means that the first feature is higher in horizontal height than the second feature. The first feature "under", "below", and "underneath" the second feature includes that the first feature is directly above and obliquely above the second feature, or only means that the first feature is lower in horizontal height than the second feature.

[0170] The above specification provides many different embodiments or examples for implementing different structures of the application. For the sake of brevity, descriptions of all possible combinations of the various embodiments and / or features are not provided. It is noted that the above description is intended to include all possible combinations of the various features and / or embodiments described herein. Additionally, the above specification, examples, and data include that the word "comprise" and variations thereof such as "comprising" and "comprises" are not used as a listing of elements to be recited following that word, but instead that they are used to teach that the broad scope of the application encompasses not only the listed elements but also elements that are in one or more embodiments replace those elements. Thus, the word "comprise" and variations thereof are used expansively and in an open-ended fashion to encompass the specific instances, groups, subgroups, and classes of instances that are described but also to cover all structural, functional, and positional modifications, enhancements, additions, equivalent, and / or substitutes for the elements described.

[0171] As used herein, the terms "one embodiment", "an embodiment", or "one or more embodiments” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0172] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0173] Finally, it is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting; it is not intended to exclude myriad other embodiments of the present application that other inventors can develop based on the same general inventive concepts embodied by the described embodiments. That is, although the present application is described in terms of particular embodiments and implementations, it is to be understood that the terminology used is for the purpose of descriptive clarity and that it should be taken in its broadest possible sense. For example, the terms "first" and "second" are used herein only to differentiate one element from another, without necessarily requiring or implying any actual relationship or order between or among the elements. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0174] The above provides a kind of driving substrate and its preparation method, display panel provided by the present application, have carried out detailed introduction, the principle and implementation mode of the present application are described in this paper by specific example, the above example is only for helping understanding the method of the present application and its core idea;For the person skilled in the art, according to the idea of the present application, there will be changes in specific implementation mode and application range, as described above, the content of the specification should not be understood as the limitation of the present application.

Claims

1. A driving substrate, characterized in that: The driving substrate includes a switch area and a capacitor area provided on at least one side of the switch area, and the driving substrate includes: substrate; a first electrode layer, a second electrode layer, and a third electrode layer stacked sequentially on one side of the base substrate, wherein the first electrode layer is disposed close to the base substrate, the second electrode layer at least partially overlaps with an orthographic projection of the first electrode layer on the base substrate, and the third electrode layer at least partially overlaps with an orthographic projection of the second electrode layer on the base substrate; The first electrode layer includes a plurality of first electrode patterns spaced apart in the capacitor region, each of the first electrode patterns includes a first climbing region, and the thickness of the first electrode pattern in the first climbing region gradually decreases along a first direction, where the first direction is a direction from the center region of the first electrode pattern to the edge of the first electrode pattern; The second electrode layer includes a second electrode pattern, the second electrode pattern is arranged in the capacitor region, the second electrode pattern is insulated from the first electrode layer, and the second electrode pattern is insulated from the third electrode layer; The second electrode pattern includes a plurality of second electrode sub-patterns, and the plurality of second electrode sub-patterns are alternately arranged with the plurality of first electrode patterns; The orthographic projection of the second electrode sub-pattern on the base substrate covers the orthographic projection of the gap between adjacent first electrode patterns on the base substrate, and the orthographic projection of the second electrode sub-pattern on the base substrate partially overlaps with the orthographic projection of the adjacent first electrode pattern on the base substrate.

2. The driving substrate according to claim 1, wherein: Each of the second electrode sub-patterns includes a second climbing region, and the thickness of the second electrode sub-pattern in the second climbing region gradually decreases along a second direction. The maximum thickness of the second electrode sub-pattern is the same as the maximum thickness of the first electrode pattern, and the second direction is the direction from the center area of ​​the second electrode sub-pattern to the edge of the second electrode sub-pattern.

3. The driving substrate according to claim 2, wherein: The second electrode layer also includes a first conductive film layer, which is arranged between the second electrode sub-pattern and the third electrode layer. The first conductive film layer covers the entire surface of the multiple second electrode sub-patterns and the gaps between adjacent second electrode sub-patterns. The thickness of the first conductive film layer is less than the maximum thickness of the second electrode sub-pattern.

4. The driving substrate according to claim 1, wherein: The second electrode layer further includes a source-drain electrode pattern, the source-drain electrode pattern covers the base substrate in the switch area and extends to the capacitor area, and the source-drain electrode pattern and the second electrode pattern are insulated from each other; The source-drain electrode pattern is provided with a first via hole in the capacitor region, and the source-drain electrode pattern is electrically connected to the first electrode layer through the first via hole.

5. The driving substrate according to any one of claims 1 to 4, characterized in that: The first electrode layer also includes a second conductive film layer, which is arranged between the first electrode pattern and the second electrode layer. The second conductive film layer covers the entire surface of the multiple first electrode patterns and the gaps between adjacent first electrode patterns. The thickness of the second conductive film layer is less than the maximum thickness of the first electrode pattern.

6. The driving substrate according to claim 4, wherein: The driving substrate further includes a passivation insulating layer, which is arranged between the second electrode layer and the third electrode layer, and an orthographic projection of the passivation insulating layer on the base substrate covers the capacitor area and the switch area; The passivation insulating layer is provided with a second via in the capacitor area, the third electrode layer entirely covers the surface of the second via facing away from the base substrate, the orthographic projection of the second via on the base substrate at least partially overlaps with the orthographic projection of the first via on the base substrate, and the third electrode layer is electrically connected to the first electrode layer through the first via and the second via.

7. The driving substrate according to claim 1, wherein: The multiple first electrode patterns are arranged at intervals along a third direction, and the gaps between adjacent first electrode patterns form a hollow structure extending along a fourth direction. The third direction is the arrangement direction of the switch area and the capacitor area, and the fourth direction is a direction perpendicular to the third direction.

8. The driving substrate according to claim 1, wherein: The plurality of first electrode patterns are arranged at intervals along the third direction, and the gaps between adjacent first electrode patterns form a hollow structure; The hollow structure includes a plurality of hollow sub-structures arranged at intervals along a fourth direction, the third direction is an arrangement direction of the switch area and the capacitor area, and the fourth direction is a direction perpendicular to the third direction.

9. The driving substrate according to claim 1, wherein: The maximum thickness of the first electrode pattern is greater than or equal to 500 nm.

10. The driving substrate according to claim 1, wherein: The slope angle of the first climbing region of the first electrode pattern is less than or equal to 40°.

11. A method for preparing a driving substrate, characterized in that: The driving substrate includes a switch area and a capacitor area provided on at least one side of the switch area, and the preparation method includes: providing a substrate; A first electrode layer, a second electrode layer, and a third electrode layer are sequentially formed on one side of the base substrate, wherein the first electrode layer is disposed close to the base substrate, the second electrode layer at least partially overlaps with an orthographic projection of the first electrode layer on the base substrate, and the third electrode layer at least partially overlaps with an orthographic projection of the second electrode layer on the base substrate; The first electrode layer includes a plurality of first electrode patterns spaced apart in the capacitor region, each of the first electrode patterns includes a first climbing region, and the thickness of the first electrode pattern in the first climbing region gradually decreases along a first direction, where the first direction is a direction from the center region of the first electrode pattern to the edge of the first electrode pattern; The second electrode layer includes a second electrode pattern, the second electrode pattern is arranged in the capacitor region, the second electrode pattern is insulated from the first electrode layer, and the second electrode pattern is insulated from the third electrode layer; The second electrode pattern includes a plurality of second electrode sub-patterns, and the plurality of second electrode sub-patterns are alternately arranged with the plurality of first electrode patterns; The orthographic projection of the second electrode sub-pattern on the base substrate covers the orthographic projection of the gap between adjacent first electrode patterns on the base substrate, and the orthographic projection of the second electrode sub-pattern on the base substrate partially overlaps with the orthographic projection of the adjacent first electrode pattern on the base substrate.

12. A display panel, characterized in that: The display panel includes a liquid crystal layer, a cell-aligning substrate, and the driving substrate according to any one of claims 1 to 10, wherein the liquid crystal layer is located between the cell-aligning substrate and the driving substrate.

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