Reset circuit capable of protecting operation site of MCU (Microprogrammed Control Unit)

Abstract

The invention provides a reset circuit capable of protecting an MCU operation site. The reset circuit comprises an MCU control chip, a VSS pin and a reset pin of the MCU control chip are connected with an LD0 chip, a GPIOX1 pin is connected with an external watchdog chip, and a GPIOX2 pin outputs a reset signal. The reset pin of the MCU control chip is also connected with a pull-up resistor. Through the power supply monitoring capability of an LD0 chip, power-on hard reset is carried out on an MCU, protection of an operation site is realized through an external watchdog chip, soft reset is carried out on the MCU, in the soft reset process, firstly, on-site protection is carried out on a key control part of the operation site, and a control signal is recovered after reset. In the reset process, the output control pin of the MCU is in a high-resistance intermediate level state, and stable output of the state can be achieved according to the externally connected pull-up resistor or pull-down resistor.

Description

Technical Field

[0001] The invention relates to a reset circuit capable of protecting an MCU operation site. Background Art

[0002] As the requirements for intelligence and digitization of aerospace systems become higher and higher, the secondary power distribution, secondary power supply, electromechanical management computer and other equipment of the airborne power system have put forward higher requirements for intelligence. Conventional primary power distribution and other equipment cannot maintain the MCU operation site after reset, and the control of the load fails after reset, which may cause the aircraft to lose power during flight. The aircraft and the pilot face serious safety hazards. The traditional equipment reset solution can no longer meet the needs. Considering the high standards of safety and reliability, the only way to meet the usage requirements is to adopt a reset circuit method that can protect the operation site.

[0003] At present, the reset circuit schemes of primary power distribution, secondary power supply and other equipment have the following deficiencies after reset: 1. There is a deadlock situation when the internal embedded software runs away; 2. After the embedded software of the equipment runs away, there is a situation where the software running site cannot be protected, and the control site cannot be restored after reset, and the aircraft loses power or the MCU loses control of the load in a short period of time; 3. During the software reset process, the external control of the equipment cannot maintain the control state before reset. For example, a MCU reset and restart method and circuit disclosed in CN111090548B solves the problems caused by MCU crashes and reduces the product defect rate; it solves the problem that the MCU cannot be restarted when the startup program crashes. However, its watchdog does not have the protection function of the MCU running site. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides a reset circuit which can protect the MCU operation site.

[0005] The present invention is achieved through the following technical solutions.

[0006] The present invention provides a reset circuit capable of protecting an MCU operation site, comprising an MCU control chip, wherein a VSS pin and a reset pin of the MCU control chip are connected to an LD0 chip, a GPIOX1 pin is connected to an external watchdog chip, and a GPIOX2 pin outputs a reset signal. The reset pin of the MCU control chip is also connected to a pull-up resistor.

[0007] The LD0 chip converts the external power supply into 3.3V to power the MCU chip.

[0008] The pull-up resistor is connected to the LD0 reset output pin. When the LD0 power conversion chip is no longer in the reset output, the pull-up circuit pulls the level high.

[0009] The GPIOX1 pin is used to trigger a non-maskable interrupt to protect the running scene.

[0010] The GPIOX2 is connected to the hardware reset pin ( / NRST pin) of the MCU to implement software reset of the MCU.

[0011] The beneficial effects of the present invention are: through the power supply monitoring capability of the LD0 chip, the MCU is hard reset when powered on, the protection of the operating scene is realized through an external watchdog chip, and the MCU is soft reset. During the soft reset process, the key control part of the operating scene is firstly protected on site, and the control signal is restored after the reset. During the reset process, the output control pin of the MCU is in a high-impedance intermediate level state, and a stable output of the state can be realized according to an external pull-up resistor or a pull-down resistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the principle of the present invention; DETAILED DESCRIPTION

[0013] The technical solution of the present invention is further described below, but the scope of protection claimed is not limited to the description.

[0014] A reset circuit capable of protecting an MCU operation site comprises an MCU control chip, wherein a VSS pin and a reset pin of the MCU control chip are connected to an LD0 chip, a GPIOX1 pin is connected to an external watchdog chip, and a GPIOX2 pin outputs a reset signal. The reset pin of the MCU control chip is also connected to a pull-up resistor.

[0015] The LD0 chip converts the external power supply into 3.3V to power the MCU chip.

[0016] The pull-up resistor is connected to the LD0 reset output pin. When the LD0 power conversion chip is no longer in the reset output, the pull-up circuit pulls the level high.

[0017] The GPIOX1 pin is used to trigger a non-maskable interrupt to protect the running scene.

[0018] The GPIOX2 is connected to the hardware reset pin ( / NRST pin) of the MCU to implement software reset of the MCU.

[0019] The external input power is converted into 3.3V by the LDO power conversion chip to power the MCU, and a reset signal with a falling edge pulse (TTL level from high to low) is output to reset and power on the MCU. After the external power-on outputs a high level for 200ms and then a low level, the reset signal is no longer output and a high impedance state appears.

[0020] The pull-up resistor is connected to the LDO reset output pin. When the LDO power conversion chip does not perform reset output, the pull-up circuit pulls the level high.

[0021] The hardware reset pin ( / NRST pin) of the MCU chip is connected to the signal output by the LDO after passing through the pull-up resistor. After receiving the falling edge pulse of the LDO output, the MCU performs a hardware power-on reset. A common output pin (GPIOX1) of the MCU is connected to the input pin of the external watchdog chip, and the watchdog output pin is connected to the non-shielded pin of the MCU. When the software runs away and deadlocks, and the external watchdog is not fed for a specified time, the external watchdog chip outputs a falling edge signal to the non-shielded pin of the MCU to trigger a non-shielded interrupt; a common output pin (GPIOX2) of the MCU is connected to the hardware reset pin ( / NRST pin) of the MCU. After the MCU completes the storage of the running scene before the reset in the non-shielded interrupt, it outputs a low level to the hardware reset pin ( / NRST pin) of the MCU, and the MCU performs a software reset.

Claims

1. A reset circuit capable of protecting an MCU operation site, characterized in that: The invention comprises an MCU control chip, wherein the VSS pin and the reset pin of the MCU control chip are connected to the LD0 chip, the GPIOX1 pin is connected to the external watchdog chip, and the GPIOX2 pin outputs a reset signal. The reset pin of the MCU control chip is also connected to a pull-up resistor.

2. The reset circuit capable of protecting the MCU operation site as claimed in claim 1, characterized in that: The LD0 chip converts the external power supply into 3.3V to power the MCU chip.

3. The reset circuit capable of protecting the MCU operation site as claimed in claim 1, characterized in that: The pull-up resistor is connected to the LD0 reset output pin. When the LD0 power conversion chip is no longer in the reset output, the pull-up circuit pulls the level high.

4. The reset circuit capable of protecting the MCU operation site as claimed in claim 1, characterized in that: The GPIOX1 pin is used to trigger a non-maskable interrupt to protect the running scene.

5. The reset circuit capable of protecting the MCU operation site as claimed in claim 1, characterized in that: The GPIOX2 is connected to the hardware reset pin ( / NRST pin) of the MCU to implement software reset of the MCU.

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