Low dropout linear regulator

Abstract

The application discloses a low-dropout linear voltage regulator, which is divided into three parts in total, the first part is an error amplifier, which ensures that the output voltage of the low-dropout linear voltage regulator remains unchanged under different load currents; the second part is a source-followed current output stage, the output current of which is divided into two branches, one of which flows to the base of an NPN triode, and the other of which flows to the first NMOS tube of a diode connection; the third part is a zero tracking part, the principle of which is to obtain a current proportional to the current flowing to the base of the NPN triode, and then obtain a zero point, the frequency of which increases with the increase of the load current, and is used for frequency compensation. The three parts, together with a power NPN triode, a voltage dividing feedback resistor and an external capacitor, constitute the whole circuit. The application can achieve an ampere level of driving current, and reduces the equivalent series resistance value requirement of the external capacitor of the whole circuit, and expands the resistance value range of the equivalent series resistance of the external capacitor.

Description

Technical Field

[0001] This invention relates to power management technology, and in particular to a low dropout linear regulator. Background Technology

[0002] Low dropout regulators (LDOs) are widely used in various chips. As chip current increases to the ampere level with increasing chip size and decreasing process node, the power transistor of the LDO is often placed externally for cost, process compatibility, and chip heat dissipation considerations, to achieve better overall system performance. In this case, a regulator circuit is needed to drive the external power transistor to provide a stable core voltage to the chip.

[0003] There is a low dropout linear regulator circuit, such as Figure 1 As shown, by reasonably setting the Miller resistor Rc and capacitor Cc, making the value of R2 much larger than R3, and selecting an appropriate equivalent series resistance (ESR) Resr for the external capacitor CL, this circuit can achieve normal operation with load current ranging from 0 to 10 mA.

[0004] As mentioned above, the focus is on analyzing how the dominant poles are allocated in this circuit. Figure 2 for Figure 1 The simplified small-signal equivalent diagram can be obtained from this small-signal diagram and its description.

[0005] Its principal pole P1 is placed at Figure 1 The Vout output terminal in the code. Its size is:

[0006]

[0007] gmn is the equivalent transconductance of an NPN transistor.

[0008] Secondly, the extreme point P2 is placed at... Figure 1 It is located at the output terminal of MOSFET PM2. Its size is:

[0009]

[0010] Where Ro-pass is Figure 1 The equivalent impedance seen at the drain terminal of MOSFET PM2.

[0011] When the load current is small (in the μA range), almost no current flows through the NPN transistor. At this time, all current flows to the load through resistor R3, creating a zero point Z2 for frequency compensation. Its magnitude is:

[0012]

[0013] The circuit can be stabilized by reasonably setting the pole P2 and the zero Z2.

[0014] When the load current is large (mA level), the NPN transistor starts to work normally, most of the current is supplied to the load end through the NPN transistor, at this time the zero Z2 has been pushed to high frequency and cannot play a compensation effect, and an additional zero Z1 needs to be generated through a suitable equivalent series resistance Resr for compensation. The size is:

[0015]

[0016] The circuit can be stabilized by reasonably setting the pole P2 and the additional zero Z1.

[0017] The existing low dropout linear regulator circuit, the equivalent series resistance Resr of the external capacitor CL participates in the overall circuit frequency compensation, so the value range is small, and the compatibility is poor; the load current cannot be expanded to the ampere level due to the main pole setting at the load end. SUMMARY

[0018] The technical problem to be solved by the present application is to provide a low dropout linear regulator (LDO) which can achieve a driving current of ampere level and reduce the equivalent series resistance value requirement of the overall circuit to the external capacitor, thereby expanding the resistance value range of the equivalent series resistance of the external capacitor.

[0019] To solve the above technical problems, the low dropout linear regulator provided by the present application comprises an error amplifier, a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, a fourth NMOS tube NM4, a first capacitor C1, a fifth resistor R5, an NPN transistor Q1, an external capacitor CL, a sixth resistor R6 and a seventh resistor R7.

[0020] The source end of the first PMOS tube PM1, the second PMOS tube PM2, the third PMOS tube PM3, the fourth PMOS tube PM4 and the fifth PMOS tube PM5, the collector of the NPN transistor and one end of the fifth resistor R5 are connected to a working voltage VDD.

[0021] The NPN transistor Q1, whose emitter is used as the output end of the low dropout linear regulator, has its base VB connected to the drain end of the second PMOS tube PM2, the drain end of the first NMOS tube NM1, the gate end of the first NMOS tube NM1 and the gate end of the second NMOS tube NM2.

[0022] The external capacitor CL is connected between the emitter of the NPN transistor Q1 and the ground.

[0023] The sixth resistor R6 and the seventh resistor R7 are connected in series between the emitter of the NPN transistor Q1 and the ground.

[0024] The negative input terminal of the error amplifier is connected to the connection point of the sixth resistor R6 and the seventh resistor R7, the positive input terminal is connected to the reference voltage Vref, and the output terminal is connected to the gate terminal of the sixth PMOS transistor PM6 and one end of the first capacitor C1.

[0025] The other end of the first capacitor C1 is connected to the drain terminal of the fifth PMOS transistor PM5 and the other end of the fifth resistor R5.

[0026] The source terminal of the sixth PMOS transistor PM6 is connected to the drain terminal of the first PMOS transistor PM1, the gate terminal of the first PMOS transistor PM1, the gate terminal of the second PMOS transistor PM2, and the gate terminal of the third PMOS transistor PM3, and the drain terminal is connected to the ground.

[0027] The drain terminal of the third PMOS transistor PM3 is connected to the drain terminal of the second NMOS transistor NM2, the drain terminal of the third NMOS transistor NM3, the gate terminal of the third NMOS transistor NM3, and the gate terminal of the fourth NMOS transistor NM4.

[0028] The fourth PMOS transistor PM4 has its gate and drain terminals shorted and connected to the gate terminal of the fifth PMOS transistor PM5 and the drain terminal of the fourth NMOS transistor NM4.

[0029] The source terminals of the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4 are connected to the ground.

[0030] Preferably, the drain current I_PM1 of the first PMOS transistor PM1 is controlled by the output of the error amplifier to obtain the gate voltage of the sixth PMOS transistor PM6, and the drain current I_PM2 of the second PMOS transistor PM2 is obtained by mirroring I_PM1, I_PM1:I_PM2=1:N, N≥1.

[0031] Preferably, the error amplifier, the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, the fourth NMOS transistor NM4, the first capacitor C1, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are placed inside a chip, and the NPN transistor and the external capacitor CL are placed outside the chip.

[0032] Preferably, the fourth capacitor C4 is connected in parallel across the sixth resistor R6.

[0033] Preferably, the drain of the sixth PMOS transistor PM6 is connected to ground through a current limiter.

[0034] Preferably, the current limiter is a current limiting resistor.

[0035] Preferably, the first capacitor C1 is 10 pF to 100 pF.

[0036] The low dropout regulator (LDO) circuit of the present application can achieve an ampere-level driving current, and reduces the equivalent series resistance Resr value requirement of the overall circuit to the external capacitor, expands the resistance value range of the equivalent series resistance Resr of the external capacitor, and theoretically, the equivalent series resistance Resr value of the external capacitor can be from 0 to 1 ohm. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the present application, the following briefly introduces the drawings used in the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0038] Figure 1 is a circuit diagram of a low dropout regulator in the prior art;

[0039] Figure 2 is Figure 1 is a simplified small signal equivalent diagram of the low dropout regulator shown in FIG.

[0040] Figure 3 is a circuit diagram of an embodiment of the low dropout regulator of the present application;

[0041] Figure 4 is Figure 3 is a simplified small signal equivalent diagram of the low dropout regulator shown in FIG. DETAILED DESCRIPTION

[0042] The technical solutions in the present application will be described clearly and completely below in combination with the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0043] Embodiment one

[0044] A low dropout regulator (LDO) is as shown in FIG. Figure 3As shown, it comprises an error amplifier, a first PMOS PM1, a second PMOS PM2, a third PMOS PM3, a fourth PMOS PM4, a fifth PMOS PM5, a sixth PMOS PM6, a first NMOS NM1, a second NMOS NM2, a third NMOS NM3, a fourth NMOS NM4, a first capacitor C1, a fifth resistor R5, an NPN transistor Q1, an external capacitor CL, a sixth resistor R6 and a seventh resistor R7;

[0045] The source end of the first PMOS PM1, the second PMOS PM2, the third PMOS PM3, the fourth PMOS PM4, the fifth PMOS PM5, the collector of the NPN transistor Q1 and one end of the fifth resistor R5 are connected to a working voltage VDD;

[0046] The emitter of the NPN transistor Q1 is connected to a low-dropout linear regulator output end, and the base VB is connected to the drain of the second PMOS PM2, the drain of the first NMOS NM1, the gate of the first NMOS NM1 and the gate of the second NMOS NM2;

[0047] The external capacitor CL is connected between the emitter of the NPN transistor Q1 and the ground;

[0048] The sixth resistor R6 and the seventh resistor R7 are connected in series between the emitter of the NPN transistor Q1 and the ground;

[0049] The negative input end of the error amplifier is connected to the connection point of the sixth resistor R6 and the seventh resistor R7, the positive input end is connected to a reference voltage Vref, and the output end is connected to the gate of the sixth PMOS PM6 and one end of the first capacitor C1;

[0050] The other end of the first capacitor C1 is connected to the drain of the fifth PMOS PM5 and the other end of the fifth resistor R5;

[0051] The source end of the sixth PMOS PM6 is connected to the drain of the first PMOS PM1, the gate of the first PMOS PM1, the gate of the second PMOS PM2 and the gate of the third PMOS PM3, and the drain is connected to the ground;

[0052] The drain of the third PMOS PM3 is connected to the drain of the second NMOS NM2, the drain of the third NMOS NM3, the gate of the third NMOS NM3 and the gate of the fourth NMOS NM4;

[0053] The fourth PMOS PM4 is connected to the gate of the fifth PMOS PM5 and the drain of the fourth NMOS NM4;

[0054] The source terminals of the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are connected to ground.

[0055] Preferably, the drain current I_PM1 of the first PMOS transistor PM1 is controlled by the output of the error amplifier to obtain the gate voltage of the sixth PMOS transistor PM6, and the drain current I_PM2 of the second PMOS transistor PM2 is obtained by mirroring I_PM1, with a ratio of 1:N, N≥1.

[0056] The low dropout regulator (LDO) of the embodiment one is divided into three parts in total. The first part is an error amplifier. The error amplifier functions to keep the voltage of the voltage feedback of the low dropout regulator output voltage VOUT under different load currents substantially consistent with the reference voltage Vref through its high gain and loop negative feedback mechanism, thereby ensuring that the low dropout regulator output voltage VOUT remains unchanged under different load currents. The second part is a current output stage of a source follower composed of the sixth PMOS transistor PM6, the first PMOS transistor PM1 and the second PMOS transistor PM2. The output current I_PM2 of the current output stage is divided into two branches, one of which flows to the base of the NPN transistor (IB_NPN), and the other of which flows to the first NMOS transistor NM1 in the diode connection (I_NM1), I_PM2=IB_NPN+I_NM1. The third part is the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3 and the fourth NMOS transistor NM4, together with the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the first capacitor C1 and the fifth resistor R5, which constitute a zero tracking part. The principle is that a current proportional to the current flowing to the base of the NPN transistor (IB_NPN) is obtained on the sixth PMOS transistor PM6, and then a zero point is obtained, the frequency of which increases with the increase of the load current, for frequency compensation. The three parts, together with the power NPN transistor, the voltage dividing feedback resistor and the external capacitor CL, constitute the entire circuit.

[0057] Figure Four For the sake of simplifying the small signal analysis diagram, the third part of the zero tracking part is not included in the diagram, which is not functionally clear and is not associated with the other parts. The whole is divided into green box and blue box parts. The green box part is Figure 3 The error amplifier and the sixth PMOS transistor PM6 and the first PMOS transistor PM1 are simplified, in which r1 is the equivalent resistance of the output end of the error amplifier, r2 and c2 are the equivalent resistance and capacitance at net2. The values of c1 and r1 are both relatively large, c1 is in the order of tens of pF, and r1 is in the order of tens of MΩ. The main pole P1 is: P1=1 / r1*c1. The blue box part is Figure 3The second PMOS PM2 and the power NPN triode and the external capacitor CL are simplified, and the overall transfer function is:

[0058]

[0059] Wherein, Rp and Cp are the equivalent resistance and capacitance at VB, and Re, Ce and gmn are parameters in the equivalent simplified hybrid Pi model of the power NPN triode. The secondary pole P2 at the output end Vout of the low-dropout linear regulator and the third pole P3 at the base VB of the NPN triode can be obtained by calculating the transfer function.

[0060] The main pole is placed at the output net1 of the error amplifier, so that the main pole will not move to high frequency with the increase of the load current. The secondary pole and the third pole are at the output end VOUT of the low-dropout linear regulator and the base VB of the NPN triode respectively. The zero point following circuit is added to generate a zero point following the secondary pole. The influence of the secondary pole can be offset by the additional zero point, the main pole and the third pole are different, and the overall loop can ensure that the load current is stable from the mA level to the A level. After the above design, the bandwidth of the overall loop is not high due to the low frequency point of the main pole, and the frequency Z1 of the zero point generated by the equivalent series resistance (ESR) Resr of the external capacitor CL is outside or close to the bandwidth. As long as the equivalent series resistance Resr resistance does not reach 1Ω level, it will not have a negative impact on the overall loop stability.

[0061] As long as the appropriate external capacitor CL is selected and the parameters of the MOS tube in the circuit are reasonably adjusted, the amperes-level voltage regulator circuit driving the external NPN triode can be realized.

[0062] There are many specific circuit implementation methods for the zero point tracking part, which are not limited to the embodiments, as long as the resistance value and the IB_NPN current are related.

[0063] The low-dropout linear regulator (LDO) of the application can drive the current to reach the amperes level, and reduces the equivalent series resistance Resr value requirement of the overall circuit to the external capacitor, expands the resistance value range of the equivalent series resistance Resr of the external capacitor, and theoretically the equivalent series resistance Resr value of the external capacitor can be from 0-1 ohm.

[0064] Embodiment two

[0065] Based on the low dropout linear regulator (LDO) of embodiment one, the error amplifier, the first PMOS PM1, the second PMOS PM2, the third PMOS PM3, the fourth PMOS PM4, the fifth PMOS PM5, the sixth PMOS PM6, the first NMOS NM1, the second NMOS NM2, the third NMOS NM3, the fourth NMOS NM4, the first capacitor C1, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 are placed inside a chip, and the NPN transistor and the external capacitor CL are placed outside the chip.

[0066] Preferably, the sixth resistor R6 has the fourth capacitor C4 connected in parallel across the two ends thereof.

[0067] Preferably, the drain of the sixth PMOS PM6 is connected to ground through a current limiter.

[0068] Preferably, the current limiter is a current limiting resistor.

[0069] Preferably, the first capacitor C1 is 10 pF to 100 pF.

[0070] The above merely provides the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of protection of the present application.

Claims

1. A low dropout linear regulator, characterized by, Error amplifier, first PMOS (PM1), second PMOS (PM2), third PMOS (PM3), fourth PMOS (PM4), fifth PMOS (PM5), sixth PMOS (PM6), first NMOS (NM1), second NMOS (NM2), third NMOS (NM3), fourth NMOS (NM4), first capacitor (C1), fifth resistor (R5), NPN transistor (Q1), external capacitor (CL), sixth resistor (R6) and seventh resistor (R7); The source end of the first PMOS (PM1), the second PMOS (PM2), the third PMOS (PM3), the fourth PMOS (PM4), the fifth PMOS (PM5), the collector of the NPN transistor and one end of the fifth resistor (R5) are connected to the working voltage. The NPN transistor (Q1) has its emitter as the output end of the low dropout linear regulator, and its base VB is connected to the drain of the second PMOS (PM2), the drain of the first NMOS (NM1), the gate of the first NMOS (NM1) and the gate of the second NMOS (NM2). The external capacitor (CL) is connected between the emitter of the NPN transistor (Q1) and the ground. The sixth resistor (R6) and the seventh resistor (R7) are connected in series between the emitter of the NPN transistor (Q1) and the ground. The negative input end of the error amplifier is connected to the series connection point of the sixth resistor (R6) and the seventh resistor (R7), the positive input end is connected to the reference voltage Vref, and the output end is connected to the gate of the sixth PMOS (PM6) and one end of the first capacitor (C1). The other end of the first capacitor (C1) is connected to the drain of the fifth PMOS (PM5) and the other end of the fifth resistor (R5). The sixth PMOS (PM6) has its source end connected to the drain of the first PMOS (PM1), the gate of the first PMOS (PM1), the gate of the second PMOS (PM2) and the gate of the third PMOS (PM3), and its drain is connected to the ground. The drain of the third PMOS (PM3) is connected to the drain of the second NMOS (NM2), the drain of the third NMOS (NM3), the gate of the third NMOS (NM3) and the gate of the fourth NMOS (NM4). The fourth PMOS (PM4) has its gate and drain shorted and connected to the gate of the fifth PMOS (PM5) and the drain of the fourth NMOS (NM4). The source ends of the first NMOS (NM1), the second NMOS (NM2), the third NMOS (NM3) and the fourth NMOS (NM4) are connected to the ground.

2. The low dropout linear regulator according to claim 1, wherein the drain current I_PM1 of the first PMOS (PM1) is controlled by the output of the error amplifier to obtain the gate voltage of the sixth PMOS (PM6), and the drain current I_PM2 of the second PMOS (PM2) is obtained by mirroring I_PM1, I_PM1:I_PM2=1:N, N≥1. ​ 3. The low dropout linear regulator of claim 1, wherein The error amplifier, the first PMOS transistor (PM1), the second PMOS transistor (PM2), the third PMOS transistor (PM3), the fourth PMOS transistor (PM4), the fifth PMOS transistor (PM5), the sixth PMOS transistor (PM6), the first NMOS transistor (NM1), the second NMOS transistor (NM2), the third NMOS transistor (NM3), the fourth NMOS transistor (NM4), the first capacitor (C1), the fifth resistor (R5), the sixth resistor (R6), and the seventh resistor (R7) are disposed inside a chip, and the NPN transistor and the external capacitor (CL) are disposed outside the chip.

4. The low dropout linear regulator of claim 1, wherein The sixth resistor (R6) is connected in parallel with the fourth capacitor (C4).

5. The low dropout linear regulator of claim 1, wherein The drain of the sixth PMOS transistor (PM6) is connected to ground through a current limiter.

6. The low dropout linear regulator of claim 5, wherein The current limiter is a current limiting resistor.

7. The low dropout linear regulator of claim 1, wherein The first capacitor (C1) is 10 pF to 100 pF.

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