Overvoltage control circuit, control device, storage device and control method

Abstract

The invention provides an overvoltage control circuit, a control device, storage equipment and a control method, and relates to the technical field of circuit control, the circuit comprises an operational amplifier circuit, a first detection circuit, a second detection circuit and a mode control circuit; the bias end of the operational amplifier circuit receives preset bias current, the positive input end of the operational amplifier circuit is connected with a voltage detection end corresponding to the output end of the negative charge pump circuit, the negative input end of the operational amplifier circuit is grounded, and the output end of the operational amplifier circuit is connected with the mode control circuit; the detection end of the operational amplifier circuit is connected with the first detection circuit; the detection end of the operational amplifier circuit is connected with the second detection circuit; the first detection circuit and the second detection circuit are respectively connected with a first control end and a second control end of the mode control circuit; the output end of the mode control circuit is used for being connected with the output end of the negative charge pump circuit through a Miller capacitor. The output of the charge pump circuit is optimized, and the manufacturing cost of a circuit board is reduced.

Description

Technical Field

[0001] The present application relates to the field of circuit control technology, and in particular to an overvoltage control circuit, a control device, a storage device, and a control method. Background Art

[0002] In the existing FLASH programming and erasing technology, the negative (positive) charge pump may produce overshoot during the voltage establishment process. This overshoot phenomenon is manifested as a voltage pulse exceeding the target voltage value, sometimes even exceeding 400 millivolts. This excessive overshoot voltage will not only cause instantaneous damage to the FLASH storage unit, but may also cause the gradual degradation of device performance, thereby affecting the overall reliability of the product.

[0003] At present, the output of the driving signal is mainly realized during the voltage establishment process of the negative (positive) charge pump by setting a fixed bias current and a fixed Miller capacitor, and the output of the clock circuit connected to the negative charge pump circuit is controlled, thereby controlling the output voltage of the negative (positive) charge pump. Specifically, the voltage establishment time of the negative (positive) charge pump can be extended by reducing the bias current or by increasing the Miller capacitor, thereby optimizing the output voltage of the negative (positive) charge pump.

[0004] However, the processing method in the prior art has a limited range of changes to the bias current. When the bias current is the minimum, the voltage build-up time of the negative (positive) charge pump cannot be extended, making it impossible to optimize the output voltage of the negative (positive) charge pump. When the Miller capacitor is increased, the area of ​​the Miller capacitor increases, which increases the size of the circuit board and the manufacturing cost of the circuit board. Therefore, it is currently impossible to optimize the output voltage of the negative (positive) charge pump without increasing the manufacturing cost of the circuit board. Summary of the invention

[0005] The purpose of the present application is to provide an overvoltage control circuit, a control device, a storage device and a control method to address the deficiencies in the above-mentioned prior art. The present application optimizes the output of the charge pump circuit without changing the input bias circuit and the Miller capacitor, thereby reducing the manufacturing cost of the circuit board.

[0006] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0007] In a first aspect, an embodiment of the present application provides an overvoltage control circuit, the overvoltage control circuit comprising: an operational amplifier circuit, a first detection circuit, a second detection circuit and a mode control circuit;

[0008] The bias terminal of the operational amplifier circuit is used to receive a preset bias current, the positive input terminal of the operational amplifier circuit is used to connect to the voltage detection terminal corresponding to the output terminal of the negative charge pump circuit, the negative input terminal of the operational amplifier circuit is grounded, and the output terminal of the operational amplifier circuit is connected to the input terminal of the mode control circuit;

[0009] The first detection end of the operational amplifier circuit is connected to the first detection circuit, and the second detection end of the operational amplifier circuit is also connected to the first detection circuit, so that the first detection circuit generates a first logic trigger signal; the first detection end of the operational amplifier circuit is connected to the second detection circuit, and the second detection end of the operational amplifier circuit is connected to the second detection circuit, so that the second detection circuit generates a second logic trigger signal;

[0010] The first detection circuit and the second detection circuit are respectively connected to the first control terminal and the second control terminal of the mode control circuit, so that the mode control circuit outputs a first clamping voltage or a second clamping voltage based on the first logic trigger signal and the second logic trigger signal;

[0011] The output end of the mode control circuit is used to connect the output end of the negative charge pump circuit through a Miller capacitor, so that the negative charge pump circuit outputs an output voltage of a first mode based on the first clamping voltage, or outputs an output voltage of a second mode based on the second clamping voltage.

[0012] Optionally, the mode control circuit includes: a timing control circuit and a mode switching circuit;

[0013] The first input terminal and the second input terminal of the timing control circuit are respectively the first control terminal and the second control terminal of the mode control circuit, and are used to connect the first detection circuit and the second detection circuit respectively; the first mode output terminal of the timing control circuit is connected to the first control terminal of the mode switching circuit to output a first control signal based on the first logic trigger signal; the second mode output terminal of the timing control circuit is connected to the second control terminal of the mode switching circuit to output a second control signal based on the second logic trigger signal;

[0014] The input end of the mode switching circuit is the input end of the mode control circuit, which is used to connect the output end of the operational amplifier circuit, so that the mode switching circuit outputs the first clamping voltage or the second clamping voltage based on the first control signal and the second control signal.

[0015] Optionally, the operational amplifier circuit includes: a first current mirror, an operational amplifier unit, a second current mirror, a third current mirror and a fourth current mirror;

[0016] The input end of the first current mirror is the bias end of the operational amplifier circuit, which is used to receive the preset bias current, the output end of the first current mirror is connected to the bias end of the operational amplifier unit, and the positive input end and the negative input end of the operational amplifier unit are respectively the positive input end and the negative input end of the operational amplifier circuit;

[0017] The first output end of the operational amplifier unit is connected to the input end of the second current mirror, and the output end of the second current mirror is connected to the input end of the third current mirror;

[0018] The second output end of the operational amplifier unit is connected to the input end of the fourth current mirror, and the series connection point of the output end of the third current mirror and the output end of the fourth current mirror is the output end of the operational amplifier circuit;

[0019] The middle point of the third current mirror and the second output terminal of the operational amplifier unit are respectively the first detection terminal and the second detection terminal of the operational amplifier circuit.

[0020] Optionally, the overvoltage control circuit also includes: an output circuit, wherein the input end of the output circuit is connected to the output end of the operational amplifier circuit, and the output end of the output circuit is connected to the control end of the clock circuit of the negative charge pump circuit to output a driving signal to the clock circuit.

[0021] Optionally, the first detection circuit includes: a first PMOS and a first NMOS whose drains are connected in series; a gate of the first PMOS and a gate of the first NMOS are respectively a first input terminal and a second input terminal of the first detection circuit, and a drain of the first PMOS and a drain of the first NMOS are output terminals of the first detection circuit to output the first logic trigger signal;

[0022] The second detection circuit includes: a second PMOS and a second NMOS whose drains are connected in series; the gate of the second PMOS and the gate of the second NMOS are respectively the first input terminal and the second input terminal of the second detection circuit, and the drain of the second PMOS and the drain of the second NMOS are the output terminals of the second detection circuit to output the second logic trigger signal.

[0023] Optionally, the mode switching circuit includes: a first mode circuit and a second mode circuit;

[0024] The control end of the first mode circuit is the first control end of the mode switching circuit, connected to the first mode output end of the timing control circuit, and used to receive the first control signal; the input end of the first mode circuit is the input end of the mode switching circuit, and used to connect to the output end of the operational amplifier circuit; the output end of the first mode circuit is grounded;

[0025] The control end of the second mode circuit is the second control end of the mode switching circuit, connected to the second mode output end of the timing control circuit, and used to receive the second control signal. The input end of the second mode circuit is the input end of the mode switching circuit, and is used to connect to the output end of the operational amplifier circuit. The output end of the second mode circuit is the output end of the mode switching circuit.

[0026] Optionally, the first mode circuit includes: a third NMOS and a third PMOS, the drain of the third NMOS and the source of the third PMOS are input terminals of the first mode circuit, the gate of the third NMOS and the gate of the third PMOS are control terminals of the first mode circuit, and the source of the third NMOS and the drain of the third PMOS are output terminals of the first mode circuit;

[0027] The second mode circuit includes: a fourth NMOS and a fourth PMOS, the drain of the fourth NMOS and the source of the fourth PMOS are input terminals of the second mode circuit, the gate of the fourth NMOS and the gate of the fourth PMOS are control terminals of the second mode circuit, and the source of the fourth NMOS and the drain of the fourth PMOS are output terminals of the second mode circuit.

[0028] In a second aspect, another embodiment of the present application provides a control device, the control device comprising: the overvoltage control circuit, the negative charge pump circuit, the clock circuit and the voltage detection circuit described in the first aspect of the above claims;

[0029] The output end of the clock circuit is connected to the clock control end of the negative charge pump circuit, so that the negative charge pump circuit generates an output voltage under the action of the clock signal; the voltage detection circuit is connected to the output end of the negative charge pump circuit to obtain a detection voltage corresponding to the output voltage;

[0030] The overvoltage control circuit is connected to the output end of the voltage detection circuit, and the overvoltage control circuit is also connected to the output end of the negative charge pump circuit, so that the negative charge pump circuit outputs an output voltage of a first mode based on a first clamping voltage, or outputs an output voltage of a second mode based on a second clamping voltage.

[0031] In a third aspect, another embodiment of the present application provides a storage device, the storage device comprising at least: the control device and the storage unit described in the second aspect above;

[0032] The output end of the control device is connected to the driving end of the storage unit.

[0033] In a fourth aspect, another embodiment of the present application provides an overvoltage control method for a negative charge pump circuit, which is applied to the overvoltage control circuit described in the first aspect above, and the method includes:

[0034] When the output voltage of the negative charge pump circuit drops to a preset first inflection point voltage but is greater than a preset second inflection point voltage, the overvoltage control circuit generates a high-level first logic trigger signal and a low-level second logic trigger signal, and outputs a first clamping voltage based on the high-level first logic trigger signal and the low-level second logic trigger signal, so that the negative charge pump circuit outputs an output voltage of a first mode based on the first clamping voltage;

[0035] When the output voltage of the negative charge pump circuit drops from the output voltage of the first mode to the preset second inflection point voltage, the overvoltage control circuit generates a low-level first logic trigger signal and a high-level second logic trigger signal, and outputs a second clamping voltage based on the low-level first logic trigger signal and the high-level second logic trigger signal, so that the negative charge pump circuit outputs the output voltage of the second mode based on the second clamping voltage.

[0036] The beneficial effects of this application are:

[0037] The present application provides an overvoltage control circuit, a control device, a storage device and a control method, including: an operational amplifier circuit, a first detection circuit, a second detection circuit and a mode control circuit; the bias end of the operational amplifier circuit is used to receive a preset bias current, the positive input end of the operational amplifier circuit is used to connect to the voltage detection end corresponding to the output end of a negative charge pump circuit, the negative input end of the operational amplifier circuit is grounded, and the output end of the operational amplifier circuit is connected to the input end of the mode control circuit; the first detection end of the operational amplifier circuit is connected to the first detection circuit, and the second detection end of the operational amplifier circuit is also connected to the first detection circuit, so that the first detection circuit generates a first logic trigger signal; the operational amplifier circuit The first detection end of the circuit is connected to the second detection circuit, and the second detection end of the operational amplifier circuit is connected to the second detection circuit, so that the second detection circuit generates a second logic trigger signal; the first detection circuit and the second detection circuit are respectively connected to the first control end and the second control end of the mode control circuit, so that the mode control circuit outputs a first clamping voltage or a second clamping voltage based on the first logic trigger signal and the second logic trigger signal; the output end of the mode control circuit is used to connect the output end of the negative charge pump circuit through the Miller capacitor, so that the negative charge pump circuit outputs an output voltage of the first mode based on the first clamping voltage, or outputs an output voltage of the second mode based on the second clamping voltage. The present application sets a first detection circuit and a second detection circuit, thereby determining the working state of the charge pump circuit through the first logic trigger signal and the second logic trigger signal of the first detection circuit and the second detection circuit. By setting a mode control circuit, the corresponding control mode is determined according to the first logic trigger signal and the second logic trigger signal, thereby outputting a clamping voltage, so that the negative charge pump circuit outputs a corresponding output voltage under the action of the clamping voltage and the Miller capacitor. The present application can optimize the output of the charge pump circuit without changing the input bias circuit and the Miller capacitor, thereby reducing the manufacturing cost of the circuit board, and at the same time avoiding the output voltage of the charge pump circuit from exceeding the overshoot voltage, thereby protecting the normal operation of the charge pump circuit and improving the life of the charge pump circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 A schematic diagram of the structure of an overvoltage control circuit provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of the structure of a mode control circuit in an overvoltage control circuit provided in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of the structure of a calculation method circuit in an overvoltage control circuit provided in an embodiment of the present application;

[0042] Figure 4 A schematic diagram of the structure of an output circuit in an overvoltage control circuit provided in an embodiment of the present application;

[0043] Figure 5 A schematic diagram of the structure of a detection circuit in an overvoltage control circuit provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram of the structure of a mode switching circuit in an overvoltage control circuit provided in an embodiment of the present application;

[0045] Figure 7a A schematic diagram of the structure of a mode circuit in a first overvoltage control circuit provided in an embodiment of the present application;

[0046] Figure 7b A schematic diagram of the structure of a mode circuit in a second overvoltage control circuit provided in an embodiment of the present application;

[0047] Figure 7c A schematic diagram of the structure of a mode circuit in a third overvoltage control circuit provided in an embodiment of the present application;

[0048] Figure 8 A voltage control schematic diagram of an overvoltage control circuit provided in an embodiment of the present application;

[0049] Fig. 9 A voltage control schematic diagram of another overvoltage control circuit provided in an embodiment of the present application;

[0050] Fig.10 A schematic diagram of the structure of a control device provided in an embodiment of the present application;

[0051] Fig.11 A schematic diagram of the structure of a storage device provided in an embodiment of the present application;

[0052] Fig.12 A flow chart of an overvoltage control method for a negative charge pump circuit provided in an embodiment of the present application.

[0053] Figure numerals: operational amplifier circuit-100; first current mirror-101; operational amplifier unit-102; second current mirror-103; third current mirror-104; fourth current mirror-105; first detection circuit-200; second detection circuit-300; mode control circuit-400; timing control circuit-404; mode switching circuit-402; first mode circuit-4021; second mode circuit-4022; negative charge pump circuit-500; output circuit-600; clock circuit-700; preset bias current-Ibias; control voltage-Vgate; drive signal-Vsin; detection voltage-Vbias; first clamping voltage-CV1; second clamping voltage-CV2; output voltage of the first mode-V1; output voltage of the second mode-V2; first logic trigger signal-strg1; second logic trigger signal-strg2; first control signal-Mode1; inverse signal of the first control signal-Mode1_b; The second control signal-Mode2; the inverse signal of the second control signal-Mode2_b; the first PMOS tube-PM1; the first NMOS tube-NM1; the second PMOS tube-PM2; the second NMOS tube-NM2; the third NMOS tube-NM3; the third PMOS tube-PM3; the fourth NMOS tube-NM4; the fourth PMOS tube-PM4; the fifth PMOS-PM5; the sixth PMOS tube-PM6; the fifth NMOS tube-NM5; the sixth NMOS tube-NM6; the seventh PMOS tube-PM7; the eighth PMOS tube-PM8; the seventh NMOS tube-NM7; the eighth NMOS tube-NM8; the ninth PMOS tube-PM9; the tenth PMOS tube-PM10; the eleventh NMOS tube-NM11; the overvoltage control circuit-1000; the negative charge pump circuit-2000; the clock circuit-3000; the voltage detection circuit-4000; the control device-10000; the storage unit-20000. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0055] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0057] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the invention is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0058] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0059] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] In the existing FLASH programming and erasing technology, the negative (positive) charge pump may produce an overshoot phenomenon during the voltage establishment process. Mainly by setting a fixed bias current and a fixed Miller capacitor, the output of the drive signal is realized during the voltage establishment process of the negative (positive) charge pump, and the output of the clock circuit connected to the negative charge pump circuit is controlled, thereby controlling the output voltage of the negative (positive) charge pump. Specifically, the voltage establishment time of the negative (positive) charge pump can be extended by reducing the bias current or by increasing the Miller capacitor to optimize the output voltage of the negative (positive) charge pump. However, the processing method in the prior art has a limited range of changes in the bias current. When the bias current is the smallest, the voltage establishment time of the negative (positive) charge pump cannot be extended, so that the output voltage of the negative (positive) charge pump cannot be optimized; when the Miller capacitor is increased, the area of ​​the Miller capacitor will increase, the size of the circuit board will increase, and the manufacturing cost of the circuit board will increase. Therefore, it is currently impossible to optimize the output voltage of the negative (positive) charge pump without increasing the manufacturing cost of the circuit board. For this reason, the present application provides an overvoltage control circuit, which optimizes the output voltage of the negative charge pump without increasing or decreasing the manufacturing cost of the circuit board. It is worth noting that the present application takes a negative charge pump as an example, and the principle of optimizing the output voltage circuit of the positive charge pump is the same as that of the present application, and can be implemented by referring to the overvoltage control circuit in the present application.

[0061] Figure 1 A schematic diagram of the structure of an overvoltage control circuit provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the overvoltage control circuit includes: an operational amplifier circuit 100, a first detection circuit 200, a second detection circuit 300, a mode control circuit 500 and an output circuit 600;

[0062] The bias terminal BIAS of the operational amplifier circuit 100 is used to receive a preset bias current Ibias, the positive input terminal IP of the operational amplifier circuit 100 is used to connect to the voltage detection terminal corresponding to the output terminal OUT of the negative charge pump circuit 500, the negative input terminal IN of the operational amplifier circuit 100 is grounded, and the output terminal OUT of the operational amplifier circuit 100 is connected to the input terminal IN of the mode control circuit 500;

[0063] The first detection terminal Signal1 of the operational amplifier circuit 100 is connected to the first input terminal IN1 of the first detection circuit 200, and the second detection terminal Signal2 of the operational amplifier circuit 100 is connected to the second input terminal IN2 of the first detection circuit 200, so that the first detection circuit 200 generates a first logic trigger signal strg1 based on the detection voltage Vbias of the first detection terminal Signal1 of the operational amplifier circuit 100; the first detection terminal Signal1 of the operational amplifier circuit 100 is connected to the first input terminal IN1 of the second detection circuit 300, and the second detection terminal Signal2 of the operational amplifier circuit 100 is connected to the second input terminal IN2 of the second detection circuit 300, so that the second detection circuit 300 generates a second logic trigger signal strg2 based on the detection voltage Vbias;

[0064] The output terminal OUT of the first detection circuit 200 and the output terminal OUT of the second detection circuit 300 are respectively connected to the first control terminal Control1 and the second control terminal Control2 of the mode control circuit 400, and the input terminal IN of the mode control circuit 400 is connected to the output terminal OUT of the operational amplifier circuit 100, so that the mode control circuit 400 outputs the first clamping voltage CV1 or the second clamping voltage CV2 under the action of the first logic trigger signal strg1 and the second logic trigger signal strg2;

[0065] The output terminal OUT of the mode control circuit 400 is used to connect the output terminal OUT of the negative charge pump circuit 500 through the Miller capacitor CM, so that the negative charge pump circuit 500 outputs the output voltage V1 of the first mode based on the first clamping voltage CV1, or outputs the output voltage V2 of the second mode based on the second clamping voltage CV2.

[0066] The bias current Ibias may be 2 to 4 uA, which is determined according to the requirements of the operational amplifier circuit 100 , and is not limited in the embodiment of the present application.

[0067] The output terminal OUT of the charge pump circuit 500 is connected to the detection circuit, which is a voltage divider circuit. The detection circuit divides the output voltage of the output terminal OUT of the charge pump circuit 500 to obtain a corresponding detection voltage, which is input to the positive input terminal IP of the operational amplifier circuit 100 through the voltage detection terminal. The detection circuit includes a voltage divider resistor and a preset reference voltage. The preset reference voltage can be 0.6V, 0.85V, 1V or 1.2V. The embodiment of the present application does not limit this. The negative input terminal IN of the operational amplifier circuit 100 is grounded. When the positive input terminal IP of the operational amplifier circuit 100 changes, the corresponding output terminal OUT of the operational amplifier circuit 100 generates a positive voltage change, so that the voltage difference between the negative input terminal IN of the operational amplifier circuit 100 and the positive input terminal IP of the operational amplifier circuit 100 is close to zero.

[0068] The first detection circuit 200 and the second detection circuit 300 output a first logic trigger signal strg1 and a second logic trigger signal strg2 respectively. The working condition of the overvoltage control circuit is determined by different judgments of the first logic trigger signal strg1 and the second logic trigger signal strg2.

[0069] The first control terminal Control1 and the second control terminal Control2 of the mode control circuit 400 receive the first logic trigger signal strg1 and the second logic trigger signal strg2 respectively, and are used to perform mode control according to the first logic trigger signal strg1 and the second logic trigger signal strg2, so that the mode control circuit 400 outputs the first clamping voltage CV1 or the second clamping voltage CV2 according to the first logic trigger signal strg1 and the second logic trigger signal strg2.

[0070] Miller capacitance CM can be 4-5pf, which is not limited in the embodiment of the present application and is determined according to the specific usage. The first clamping voltage CV1 or the second clamping voltage CV2 passes through Miller capacitance CM, so that the output voltage V1 of the first mode or the output voltage V2 of the second mode is less than the overshoot voltage of the charge pump circuit 600. Among them, the output voltage V1 of the first mode and the output voltage V2 of the second mode are both less than the overshoot voltage of the charge pump circuit 600. The overshoot voltage of the charge pump circuit 600 can be determined according to the specific circuit of the charge pump circuit 600, which is not limited in the embodiment of the present application.

[0071] The present application provides an overvoltage control circuit, comprising: an operational amplifier circuit, a first detection circuit, a second detection circuit and a mode control circuit; the bias end of the operational amplifier circuit is used to receive a preset bias current, the positive input end of the operational amplifier circuit is used to connect to a voltage detection end corresponding to the output end of a negative charge pump circuit, the negative input end of the operational amplifier circuit is grounded, and the output end of the operational amplifier circuit is connected to the input end of the mode control circuit; the first detection end of the operational amplifier circuit is connected to the first detection circuit, and the second detection end of the operational amplifier circuit is also connected to the first detection circuit, so that the first detection circuit generates a first logic trigger signal; the first detection end of the operational amplifier circuit is connected to the second detection circuit, and the second detection end of the operational amplifier circuit is connected to the second detection circuit, so that the second detection circuit generates a second logic trigger signal; the first detection circuit and the second detection circuit are respectively connected to the first control end and the second control end of the mode control circuit, so that the mode control circuit outputs a first clamping voltage or a second clamping voltage based on the first logic trigger signal and the second logic trigger signal; the output end of the mode control circuit is used to connect to the output end of the negative charge pump circuit through a Miller capacitor, so that the negative charge pump circuit outputs an output voltage of a first mode based on the first clamping voltage, or outputs an output voltage of a second mode based on the second clamping voltage. The present application sets a first detection circuit and a second detection circuit, thereby determining the working state of the charge pump circuit through the first detection circuit and the second detection circuit's first logic trigger signal and the second logic trigger signal. By setting a mode control circuit, the corresponding control mode is determined according to the first logic trigger signal and the second logic trigger signal, thereby outputting a clamping voltage, so that the negative charge pump circuit outputs a corresponding output voltage under the action of the clamping voltage and the Miller capacitor. The present application can optimize the output of the charge pump circuit without changing the input bias circuit and the Miller capacitor, reducing the manufacturing cost of the circuit board, while preventing the output voltage of the charge pump circuit from exceeding the overshoot voltage, protecting the normal operation of the charge pump circuit, and improving the life of the charge pump circuit.

[0072] Based on the above embodiments, the present application further provides a mode control circuit in an overvoltage control circuit. Figure 2 A schematic diagram of the structure of a mode control circuit in an overvoltage control circuit provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the mode control circuit 500 includes: a timing control circuit 401 and a mode switching circuit 402;

[0073] The first input terminal IN1 and the second input terminal IN2 of the timing control circuit 401 are respectively connected to the first control terminal Control1 and the second control terminal Control2 of the mode control circuit 500. Figure 1The output terminal OUT of the first detection circuit 200 and the output terminal OUT of the second detection circuit 300, the first mode output terminal OUT1 of the timing control circuit 401 is connected to the first control terminal Control1 of the mode switching circuit 402, so as to output a first control signal Mode1 to the first control terminal Control1, and the second mode output terminal OUT2 of the timing control circuit 401 is connected to the second control terminal Control1 of the mode switching circuit 402, so as to output a second control signal Mode2 to the second control terminal Control1;

[0074] The input terminal IN of the mode switching circuit 402 is the input terminal IN of the mode control circuit 500, which is used to connect the output terminal OUT of the operational amplifier circuit 100, so that the mode switching circuit 402 outputs the first clamping voltage CV1 or the second clamping voltage CV2 under the action of the first control signal Mode1 and the second control signal Mode2 respectively.

[0075] The timing control circuit 401 includes a clock source, a frequency divider, a counter, a trigger, a register, a logic gate, and a delay element. The timing control circuit 401 is used to receive a first logic trigger signal strg1 and a second logic trigger signal strg2, and generate a first control signal Mode1 and a second control signal Mode2 according to the first logic trigger signal strg1 and the second logic trigger signal strg2.

[0076] The mode switching circuit 402 is used for outputting the first clamping voltage CV1 or the second clamping voltage CV2 according to the control mode of the mode switching circuit 402 determined by the first control signal Mode1 and the second control signal Mode2 .

[0077] In an embodiment of the present application, the mode control circuit includes a timing control circuit and a mode switching circuit. The timing control circuit generates a corresponding control signal according to a logic trigger signal, and the mode switching circuit determines the control mode according to the corresponding control signal, thereby outputting a clamping voltage. The present application can ensure that operations are performed in a precise time sequence through the timing control circuit, and the mode switching circuit can easily switch between different operating modes according to different control signals, thereby improving the stability and reliability of the overvoltage control circuit.

[0078] Based on the above embodiments, the present application further provides a bias circuit in an overvoltage control circuit. Figure 3 A schematic diagram of the structure of an operational amplifier circuit in an overvoltage control circuit provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the operational amplifier circuit 100 includes: an operational amplifier unit 102, a second current mirror 103, a third current mirror 104 and a fourth current mirror 105;

[0079] A first current mirror 101, wherein an input terminal IN of the first current mirror 101 is a bias terminal BIAS of the operational amplifier circuit 100, and is used to receive the preset bias current Ibias; an output terminal OUT of the first current mirror 101 is connected to a bias terminal BIAS of the operational amplifier unit 102; a positive input terminal IP and a negative input terminal IN of the operational amplifier unit 102 are respectively a positive input terminal IP and a negative input terminal IN of the operational amplifier circuit 100;

[0080] The first output terminal OUT1 of the operational amplifier unit 102 is connected to the input terminal IN of the second current mirror 103 , and the output terminal OUT of the second current mirror 103 is connected to the input terminal IN of the third current mirror 104 ;

[0081] The second output terminal OUT of the operational amplifier unit 102 is connected to the input terminal IN of the fourth current mirror 201 , and the series connection point of the output terminal OUT of the third current mirror 104 and the output terminal OUT of the fourth current mirror 105 is the output terminal OUT of the operational amplifier circuit 100 ;

[0082] The middle point of the third current mirror 104 and the second output terminal OUT2 of the operational amplifier unit 102 are respectively the first detection terminal Signal1 and the second detection terminal Signal2 of the operational amplifier circuit 201 .

[0083] Among them, the first current mirror 101 is a bias circuit. The first current mirror 101 includes a fifth PMOS (positive channel Metal Oxide Semiconductor, referred to as PMOS tube) PM5 and a sixth PMOS tube PM6. The drain and gate of the fifth PMOS tube PM5 and the gate of the sixth PMOS tube PM6 are the input terminal IN of the first current mirror 101, which is used to receive the preset bias current Ibisa, the source of the fifth PMOS tube PM5 and the source of the sixth PMOS tube PM6 are connected, and the drain of the sixth PMOS tube PM6 is the output terminal OUT of the first current mirror 101, which is used to connect the bias terminal BIAS of the operational amplifier circuit 100. The width ratio of the fifth PMOS tube PM5 and the sixth PMOS tube PM6 is any ratio of 1:0.2 to 4, and the embodiment of the present application does not limit this. The sixth PMOS tube PM6 can amplify the current flowing through the fifth PMOS tube PM5 by 0.2 to 4 times, and the specific amplification ratio is determined according to the width ratio of the fifth PMOS tube PM5 and the sixth PMOS tube PM6.

[0084] Specifically, the preset bias current Ibisa is input into the first current mirror 101 through the drain of the fifth PMOS transistor PM5 , and after the sixth PMOS transistor PM6 amplifies the preset bias current Ibisa, it enters the bias terminal BIAS of the operational amplifier unit 102 through the drain of the sixth PMOS transistor PM6 .

[0085] The second current mirror 103 includes a fifth NMOS transistor NM5 and a sixth NMOS transistor NM6, the gate and drain of the fifth NMOS transistor NM5 and the gate of the sixth NMOS transistor NM6 are input terminals of the second current mirror 103, and are used to connect to the first output terminal of the operational amplifier power supply 201, the source of the fifth NMOS transistor NM5 and the source of the sixth NMOS transistor NM6 are grounded, and the drain of the sixth NMOS transistor NM6 is the output terminal of the second current mirror 103, and is used to connect to the third current mirror 104. The width ratio of the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 is 1:1, and the fifth NMOS transistor NM5 and the sixth NMOS transistor NM6 are the same.

[0086] The third current mirror 104 includes a seventh PMOS transistor PM7 and an eighth PMOS transistor PM8, the gate and drain of the seventh PMOS transistor PM7 and the gate of the eighth PMOS transistor PM8 are input terminals of the third current mirror 104, and are used to connect the output terminal of the second current mirror 103, the source of the seventh PMOS transistor PM7 and the source of the eighth PMOS transistor PM8 are connected, and the drain of the eighth PMOS transistor PM8 is the output terminal of the third current mirror 104. The width ratio of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 is 1:1, and the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are the same.

[0087] The fourth current mirror 105 includes a seventh NMOS tube NM7 and an eighth NMOS tube NM8, the gate and drain of the seventh NMOS tube NM7 and the gate of the eighth NMOS tube NM8 are input terminals of the fourth current mirror 105, and are used to connect the second output terminal of the operation method unit 201, the source of the seventh NMOS tube NM7 and the source of the eighth NMOS tube NM8 are grounded, and the drain of the eighth NMOS tube NM8 is the output terminal of the fourth current mirror 105. The width ratio of the seventh NMOS tube NM7 and the eighth NMOS tube NM8 is 1:1, and the seventh NMOS tube NM7 and the eighth NMOS tube NM8 are the same.

[0088] The operational amplifier unit 102 includes a ninth PMOS transistor PM9 and a tenth PMOS transistor PM10, the gate of the ninth PMOS transistor PM9 is the positive input terminal IP of the operational amplifier unit 102, the gate of the tenth PMOS transistor PM10 is the negative input terminal IN of the operational amplifier unit 102, the source of the ninth PMOS transistor PM9 and the source of the tenth PMOS transistor PM10 are the bias terminal BIAS of the operational amplifier unit 102, the drain of the ninth PMOS transistor PM9 is the second output terminal of the operational amplifier unit 102, and the drain of the tenth PMOS transistor PM10 is the first output terminal of the operational amplifier unit 102. The width ratio of the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 is 1:1, that is, the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 are the same.

[0089] Specifically, when the gate of the ninth PMOS tube PM9 is the positive input terminal IP of the operational amplifier unit 102, the gate of the tenth PMOS tube PM10 is the negative input terminal IN of the operational amplifier unit 102, and the negative input terminal IN of the operational amplifier unit 102 is grounded, that is to say, the voltage of the gate of the tenth PMOS tube PM10 is 0, at this time, the voltage of the gate of the ninth PMOS tube PM9 is the detection voltage input by the detection circuit, at this time, the voltage of the gate of the ninth PMOS tube PM9 is greater than the voltage of the gate of the tenth PMOS tube PM10, the current flowing through the tenth PMOS tube PM10 is greater than the current flowing through the ninth PMOS tube PM9, the current flowing through the fifth NMOS tube NM5, the current flowing through the sixth NMOS tube NM6, the current flowing through the seventh PMOS tube PM7 and the eighth PMOS tube PM8 are all the same as the current flowing through the tenth PMOS tube PM10, and the current flowing through the seventh NMOS tube NM7 and the eighth NMOS tube NM8 are all the same as the current flowing through the ninth PMOS tube PM9. The current passing through the eighth PMOS transistor PM8 at both ends of the output circuit 600 is greater than the current passing through the eighth NMOS transistor NM8. At this time, the output control voltage Vgate is pulled high and the drive signal Vsin is grounded. At this time, the clock signal clk and the reverse clock signal clkb are fully swinging, and the charge pump starts to work.

[0090] In an embodiment of the present application, the operational amplifier circuit includes an operational amplifier unit, a second current mirror, a third current mirror and a fourth current mirror. The currents at the positive input terminal and the negative input terminal of the operational amplifier unit are compared through multiple current mirrors to generate a control voltage, which can improve the linearity and accuracy of the operational amplifier unit. The current mirrors can maintain a stable input of the operational amplifier circuit and optimize the gain and anti-interference capability of the operational amplifier unit.

[0091] Based on the above embodiments, the present application further provides an output circuit in an overvoltage control circuit, Figure 4A schematic diagram of the structure of an output circuit in an overvoltage control circuit provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the overvoltage control circuit also includes: an output circuit 600, the input terminal IN of the output circuit 600 is connected to the output terminal OUT of the operational amplifier circuit 100, and the output terminal OUT of the output circuit 600 is connected to the control terminal Control of the clock circuit 700 of the negative charge pump circuit 500 to output a driving signal Vsin to the clock circuit 700.

[0092] The output circuit 600 includes an NMOS transistor, and the input terminal IN of the output circuit 600 is connected to the output terminal OUT of the operational amplifier circuit 100. The control voltage Vgate outputted by the output terminal OUT of the amplifier circuit 200 drives the NMOS transistor in the output circuit 600, so that the output circuit 600 outputs a driving signal Vsin to the clock circuit 700. The clock circuit 700 is used to output a clock signal clk and a reverse clock signal clkb. The clock circuit 700 includes a first inverter, a second inverter, and a third inverter. The input terminal of the first inverter is used to receive the main clock signal clock, the output terminal of the first inverter is used to output the clock signal clk, the power supply terminal of the first inverter is used to connect to a voltage regulator, and the control terminal of the first inverter is used to receive the driving signal Vsin. The input terminal of the second inverter is used to receive the main clock signal cl ock, the output terminal of the second inverter is used to connect to the input terminal of the third inverter, the output terminal of the third inverter is used to output the reverse clock signal clkb, the power supply terminal of the third inverter is used to connect to a voltage regulator, and the control terminal of the third inverter is used to receive the driving signal Vsin.

[0093] In an embodiment of the present application, the overvoltage control circuit also includes a clock circuit, which timely adjusts the output signal according to the driving voltage of the operational amplifier circuit, thereby protecting the circuit from damage due to overvoltage. The driving signal is output to the clock circuit through the output circuit, so as to effectively manage the working state of the negative charge pump circuit.

[0094] Based on the above embodiments, the present application further provides a detection circuit in an overvoltage control circuit. Figure 5 A schematic diagram of the structure of a detection circuit in an overvoltage control circuit provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the first detection circuit 200 includes: a first PMOS transistor PM1 and a first NMOS transistor NM1 whose drains are connected in series; the gate of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1 are respectively the first input terminal IN1 and the second input terminal IN2 of the first detection circuit 200, and the drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM2 are the output terminals of the first detection circuit 200 to output the first logic trigger signal strg1;

[0095] The second detection circuit 300 includes: a second PMOS transistor PM2 and a second NMOS transistor NM2 whose drains are connected in series; the gate of the second PMOS transistor PM2 and the gate of the second NMOS transistor NM2 are respectively the first input terminal IN1 and the second input terminal IN2 of the second detection circuit 300, and the drain of the second PMOS transistor ON2 and the drain of the second NMOS transistor NM2 are the output terminal of the second detection circuit 300 to output the second logic trigger signal strg2;

[0096] Among them, the width ratio of the first PMOS tube PM1 to the eighth PMOS tube PM8 is any ratio of 0.2 to 4:1, which is specifically determined according to the first inflection point voltage of the driving voltage Vgate, and the embodiment of the present application does not limit this; the width ratio of the first NMOS tube NM1 to the eighth NMOS tube NM8 is any ratio of 0.2 to 4:1, which is specifically determined according to the first inflection point voltage of the driving voltage Vgate, and the embodiment of the present application does not limit this. The width ratio of the first PMOS tube PM1 to the eighth PMOS tube PM8 and the width ratio of the first NMOS tube NM1 to the eighth NMOS tube NM8 are the same.

[0097] The width ratio of the second PMOS tube PM2 to the eighth PMOS tube PM8 is any ratio of 0.2 to 4:1, which is specifically determined according to the second inflection point voltage of the driving voltage Vgate, and the embodiment of the present application does not limit this; the width ratio of the second NMOS tube NM2 to the eighth NMOS tube NM8 is any ratio of 0.2 to 4:1, which is specifically determined according to the second inflection point voltage of the driving voltage Vgate, and the embodiment of the present application does not limit this. The width ratio of the second PMOS tube PM2 to the eighth PMOS tube PM8 and the width ratio of the second NMOS tube NM2 to the eighth NMOS tube NM8 are the same.

[0098] Specifically, in the case where the first inflection point voltage is greater than the second inflection point voltage, when the sizes of the first PMOS tube PM1 and the second PMOS tube PM2 are the same, the size of the first NMOS tube NM1 is greater than the size of the second NMOS tube NM2; when the size of the first NMOS tube NM1 is equal to the size of the second NMOS tube NM2, the size of the first PMOS tube PM1 is smaller than the size of the second PMOS tube PM2.

[0099] Specifically, when the driving voltage Vgate reaches the first inflection point voltage, the first logic trigger signal strg1 outputs a high level, and the second logic trigger signal strg1 outputs a low level; when the driving voltage Vgate reaches the second inflection point voltage, the first logic trigger signal strg1 outputs a low level, and the second logic trigger signal strg1 outputs a high level. The first inflection point voltage and the second inflection point voltage are determined according to the actual situation of the charge pump circuit 600, and the second inflection point voltage is less than the first inflection point voltage.

[0100] In an embodiment of the present application, a first detection circuit and a second detection circuit are set to detect the first inflection point voltage and the second inflection point voltage respectively, and a corresponding logic trigger signal is output according to the first inflection point voltage or the second inflection point voltage. The first detection circuit and the second detection circuit quickly respond to changes in the inflection point voltage to ensure the accuracy and reliability of generating the logic trigger signal.

[0101] Based on the above embodiments, the present application further provides a mode switching circuit in an overvoltage control circuit. Figure 6 This is a structural diagram of a mode switching circuit in an overvoltage control circuit provided in an embodiment of the present application. The mode switching circuit 402 includes: a first mode circuit 4021 and a second mode circuit 4022;

[0102] The control terminal Control of the first mode circuit 4021 is the first control terminal Control1 of the mode switching circuit 402, connected to the first mode output terminal OUT1 of the timing control circuit 502, and used to receive the first control signal Mode1. The input terminal IN of the first mode circuit 4021 is the input terminal IN of the mode switching circuit, and used to connect Figure 1 The output terminal ONT of the operational amplifier circuit 100 and the output terminal OUT of the first mode circuit 4021 are grounded;

[0103] The control terminal Control of the second mode circuit 4022 is the second control terminal Control2 of the mode switching circuit 402, connected to the second mode output terminal OUT2 of the timing control circuit 502, and used to receive the second control signal Mode2. The input terminal IN of the second mode circuit 5022 is the input terminal IN of the mode switching circuit, and used to connect Figure 1 The input terminal OUT of the operational amplifier circuit 100 in the embodiment of the present invention is the output terminal OUT of the second mode circuit 4022 , and the output terminal OUT of the second mode circuit 4022 is the output terminal OUT of the mode switching circuit 402 .

[0104] Specifically, the working conditions of the first mode circuit 4021 and the second mode circuit 4022 are determined according to the first control signal Mode1 or the second control signal Mode2. When the first control signal Mode1 is at a high level and the second control signal Mode2 is at a low level, the first mode circuit 4021 works and the second mode circuit 4022 does not work. At this time, the driving voltage Vgate is pulled down by the first mode circuit 4021, thereby limiting the control signal Vsin, thereby optimizing the output of the negative charge pump circuit; when the first control signal Mode1 is at a low level and the second control signal Mode2 is at a high level, the first mode circuit 4021 does not work and the second mode circuit 4022 works, and the output voltage of the negative charge pump circuit 600 is controlled to be close to the target voltage through the Miller capacitor CM.

[0105] In the embodiment of the present application, the mode switching circuit includes a first mode circuit and a second mode circuit. The working mode circuit is determined according to the input control signal, and the output voltage of the charge pump circuit can be adjusted according to different working conditions, thereby improving the accuracy and stability of the output voltage, reducing the power consumption of the charge pump circuit, and improving the overall energy efficiency.

[0106] Based on the above embodiments, the present application also provides a variety of mode circuits in overvoltage control circuits. Figure 7a This is a schematic diagram of the structure of the mode circuit in the first overvoltage control circuit provided in the embodiment of the present application, such as Figure 7a As shown, the first mode circuit 4021 includes: a third NMOS transistor NM3 and a third PMOS transistor PM3, the drain of the third NMOS transistor NM3 and the source of the third PMOS transistor PM3 are the input terminal IN of the first mode circuit 4021, the gate of the third NMOS transistor NM3 and the gate of the third PMOS transistor PM3 are the control terminal Control of the first mode circuit 4021, the source of the third NMOS transistor NM3 and the drain of the third PMOS transistor PM3 are the output terminal OUT of the first mode circuit 4021. The first mode circuit 4021 also includes: an eleventh NMOS transistor NM11, the gate and drain of the eleventh NMOS transistor NM11 are connected to the source of the third NMOS transistor NM3 and the drain of the third PMOS transistor PM3, the source of the eleventh NMOS transistor NM11 is the output terminal OUT of the first mode circuit 4021, and the source of the eleventh NMOS transistor NM11 is grounded. Correspondingly, the first control signal Mode1 also includes an inverse signal Mode1_b of the first control signal. The gate of the third NMOS tube NM3 is used to receive the first control signal Mode1, and the gate of the third PMOS tube PM3 is used to receive the inverse signal Mode1_b of the first control signal. When the first control signal Mode1 is at a high level, the inverse signal Mode1_b of the first control signal is at a low level. At this time, the third NMOS tube NM3 and the third PMOS tube PM3 are turned on, and the eleventh NMOS tube NM11 is turned on. At this time, the control voltage Vgate is pulled down, thereby limiting the driving voltage Vsin.

[0107] The second mode circuit 4022 includes: a fourth NMOS transistor NM4 and a fourth PMOS transistor PM4, the drain of the fourth NMOS transistor NM4 and the source of the fourth PMOS transistor PM4 are the input terminal IN of the second mode circuit 4022, the gate of the fourth NMOS transistor NM4 and the gate of the fourth PMOS transistor PM4 are the control terminal Control of the second mode circuit 4022, the source of the fourth NMOS transistor NM4 and the drain of the fourth PMOS transistor NM4 are the output terminal of the second mode circuit. Correspondingly, the second control signal Mode2 also includes an inverse signal Mode2_b of the second control signal, the gate of the fourth NMOS transistor NM4 is used to receive the second control signal Mode2, and the gate of the fourth PMOS transistor PM4 is used to receive the inverse signal Mode2_b of the second control signal. When the second control signal Mode2 is at a high level, the inverse signal Mode2_b of the second control signal is at a low level. At this time, the fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 are turned on, and the output voltage of the charge pump circuit 600 is controlled to be close to the target voltage through the Miller capacitor CM.

[0108] The third NMOS transistor NM3 and the fourth NMOS transistor NM4 have the same size, and the third PMOS transistor PM3 and the fourth PMOS transistor PM4 have exactly the same size.

[0109] Optionally, Figure 7b A schematic diagram of the structure of a mode circuit in a second overvoltage control circuit provided in an embodiment of the present application, such as Figure 7b As shown, in Figure 7a On the basis of, the first mode circuit 4021 also includes: a twelfth NMOS tube NM12, the gate and drain of the twelfth NMOS tube NM12 are connected to the source of the eleventh NMOS tube NM11, the source of the twelfth NMOS tube NM12 is the output terminal OUT of the first mode circuit 4021, and the source of the twelfth NMOS tube NM12 is grounded.

[0110] Optionally, Figure 7c This is a schematic diagram of the structure of the mode circuit in the third overvoltage control circuit provided in the embodiment of the present application, such as Figure 7c As shown, in Figure 7b Based on the above, the gate of the twelfth NMOS tube NM12 is used to receive the above Figure 1 The detection voltage Vbias of the first detection terminal Signal1 of the operational amplifier circuit 100, the drain of the twelfth NMOS tube NM12 is connected to the source of the eleventh NMOS tube NM11, the source of the twelfth NMOS tube NM12 is the output terminal OUT of the first mode circuit 4021, and the source of the twelfth NMOS tube NM12 is grounded.

[0111] It is worth noting that the above-mentioned mode circuit is only a possible implementation method of the mode circuit. In actual use, there are many structures of the mode circuit. The specific mode circuit can be determined according to the actual use scenario, and the embodiments of the present application do not limit this.

[0112] In the embodiment of the present application, by switching the corresponding modes of the multiple NMOS tubes and PMOS tubes in the first mode control circuit and the second mode circuit, the output voltage of the charge pump circuit can be accurately controlled, the efficiency of the charge pump circuit can be optimized, and the power consumption can be reduced. At the same time, the present application can reduce parasitic effects and improve signal integrity through mode circuits with multiple structures, allowing for more precise adjustment of the circuit behavior and improving the flexibility of the mode control circuit.

[0113] As follows, the overvoltage control circuit provided in the embodiment of the present application is described in conjunction with the accompanying drawings. Figure 8 A voltage control schematic diagram of an overvoltage control circuit provided in an embodiment of the present application, such as Figure 8 As shown, the first inflection point voltage of the output voltage of the charge pump circuit is Vtg0, the second inflection point voltage is Vtg1, and the target voltage is Vtg.

[0114] The gate of the ninth PMOS tube PM9 is the positive input terminal IP of the operational amplifier unit 102, the gate of the tenth PMOS tube PM10 is the negative input terminal IN of the operational amplifier unit 102, and when the negative input terminal IN of the operational amplifier unit 102 is grounded, that is, the voltage of the gate of the tenth PMOS tube PM10 is 0, at this time, the voltage of the gate of the ninth PMOS tube PM9 is the detection voltage input by the detection circuit, at this time, the voltage of the gate of the ninth PMOS tube PM9 is greater than the voltage of the gate of the tenth PMOS tube PM10, the current flowing through the tenth PMOS tube PM10 is greater than the current flowing through the ninth PMOS tube PM9, the current flowing through the fifth NMOS tube NM5, the current flowing through the sixth NMOS tube NM6, the current flowing through the seventh PMOS tube PM7 and the eighth PMOS tube PM8 are all the same as the current flowing through the tenth PMOS tube PM10, and the current flowing through the seventh NMOS tube NM7 and the eighth NMOS tube NM8 are all the same as the current flowing through the ninth PMOS tube PM9. The current passing through the eighth PMOS transistor PM8 at both ends of the output circuit 600 is greater than the current passing through the eighth NMOS transistor NM8. At this time, the output control voltage Vgate is pulled high and the drive signal Vsin is grounded. At this time, the clock signal clk and the reverse clock signal clkb are fully swinging, the charge pump starts to work, and the output voltage starts to drop from Vini.

[0115] When the output voltage drops from Vini to the first inflection point voltage Vtg0, the first logic trigger signal strg1 outputs a high level, and the second logic trigger signal strg1 outputs a low level. The first control signal Mode1 is a high level, the inverse signal Mode1_b of the first control signal is a low level, the second control signal Mode2 is a low level, and the inverse signal Mode2_b of the second control signal is a high level. At this time, the third NMOS tube NM3 and the third PMOS tube PM3 are turned on, and the eleventh NMOS tube NM11 is turned on, and the control voltage Vgate is pulled down, thereby limiting the driving voltage Vsin.

[0116] When the output voltage drops from the first inflection point voltage Vtg0 to the second inflection point voltage Vtg1, the first logic trigger signal strg1 outputs a low level, and the second logic trigger signal strg1 outputs a high level. The first control signal Mode1 is at a low level, the inverted signal Mode1_b of the first control signal is at a high level, the second control signal Mode2 is at a high level, the inverted signal Mode2_b of the second control signal is at a low level, the fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 are turned on, and the output voltage of the charge pump circuit 600 is controlled to be close to the target voltage Vtg through the Miller capacitor CM.

[0117] Based on the above embodiment, the present application also provides another voltage control schematic diagram of an overvoltage control circuit. Fig. 9 A voltage control schematic diagram of another overvoltage control circuit provided in an embodiment of the present application, such as Fig. 9 As shown, the first inflection point voltage of the output voltage of the charge pump circuit is Vtg0, the second inflection point voltage is Vtg1, the third inflection point voltage is Vtg2, the fourth inflection point voltage is Vtg3, and the target voltage is Vtg. When there are four inflection point voltages, four detection circuits are set, and the output voltage of the charge pump circuit can be controlled according to the logic signals output by the four detection circuits. When the corresponding step voltage is reached, the inflection point voltage can be maintained for a certain time by setting a timer, so as to accurately control the output voltage of the charge pump circuit, gradually reach the final target voltage Vtg, effectively control the output of the charge pump circuit, and avoid overshoot of the output voltage of the charge pump circuit.

[0118] Another embodiment of the present application further provides a control device, Fig.10 A schematic diagram of the structure of a control device provided in an embodiment of the present application is shown in FIG. Fig.10 As shown, the control device includes: an overvoltage control circuit 1000, a negative charge pump circuit 2000, a clock circuit 3000 and a voltage detection circuit 4000;

[0119] The voltage detection circuit 4000 is connected to the output terminal OUT of the negative charge pump circuit 2000 to obtain a detection voltage corresponding to the output voltage;

[0120] The overvoltage control circuit 1000 is connected to the output terminal OUT of the voltage detection circuit 4000. The overvoltage control circuit 1000 is also connected to the output terminal OUT of the negative charge pump circuit 2000, so that the negative charge pump circuit 2000 outputs the output voltage V1 of the first mode based on the first clamping voltage CV1, or outputs the output voltage V2 of the second mode based on the second clamping voltage CV2.

[0121] Among them, the voltage detection circuit 4000 includes two voltage-dividing resistors, the first voltage-dividing resistor is connected to the input end of the negative charge pump circuit 2000, the second voltage-dividing resistor is used to connect to the preset reference voltage, and the connecting ends of the two voltage-dividing resistors are used to connect to the input end IN of the overvoltage control circuit 1000.

[0122] Another embodiment of the present application further provides a storage device, Fig.11 A schematic diagram of a storage device provided in an embodiment of the present application is shown in FIG. Fig.11 As shown, the storage device includes: a control device 10000 and a storage unit 20000; the output terminal OUT of the control device 10000 is connected to the driving terminal D of the storage unit 20000.

[0123] Another embodiment of the present application further provides an overvoltage control method for a negative charge pump circuit, which is applied to an overvoltage control circuit. Fig.12 A schematic diagram of a flow chart of an overvoltage control method for a negative charge pump circuit provided in an embodiment of the present application is shown in FIG. Fig.12 As shown, the method includes:

[0124] Step 1201, when the output voltage of the negative charge pump circuit drops to a preset first inflection point voltage but is greater than a preset second inflection point voltage, the first detection circuit and the second detection circuit in the overvoltage control circuit generate and output a first logic trigger signal of a high level and a second logic trigger signal of a low level, and output a first clamping voltage based on the first logic trigger signal of the high level and the second logic trigger signal of the low level, so that the negative charge pump circuit outputs an output voltage of a first mode based on the first clamping voltage.

[0125] Step 1202, when the output voltage of the negative charge pump circuit drops from the output voltage of the first mode to a preset second inflection point voltage, the overvoltage control circuit generates a low-level first logic trigger signal and a high-level second logic trigger signal, and outputs a second clamping voltage based on the low-level first logic trigger signal and the high-level second logic trigger signal, so that the negative charge pump circuit outputs the output voltage of the second mode based on the second clamping voltage.

[0126] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An overvoltage control circuit, characterized in that: The overvoltage control circuit comprises: an operational amplifier circuit, a first detection circuit, a second detection circuit and a mode control circuit; The bias terminal of the operational amplifier circuit is used to receive a preset bias current, the positive input terminal of the operational amplifier circuit is used to connect to the voltage detection terminal corresponding to the output terminal of the negative charge pump circuit, the negative input terminal of the operational amplifier circuit is grounded, and the output terminal of the operational amplifier circuit is connected to the input terminal of the mode control circuit; The first detection end of the operational amplifier circuit is connected to the first detection circuit, and the second detection end of the operational amplifier circuit is also connected to the first detection circuit, so that the first detection circuit generates a first logic trigger signal; the first detection end of the operational amplifier circuit is connected to the second detection circuit, and the second detection end of the operational amplifier circuit is connected to the second detection circuit, so that the second detection circuit generates a second logic trigger signal; The first detection circuit and the second detection circuit are respectively connected to the first control terminal and the second control terminal of the mode control circuit, so that the mode control circuit outputs a first clamping voltage or a second clamping voltage based on the first logic trigger signal and the second logic trigger signal; The output end of the mode control circuit is used to connect the output end of the negative charge pump circuit through a Miller capacitor, so that the negative charge pump circuit outputs an output voltage of a first mode based on the first clamping voltage, or outputs an output voltage of a second mode based on the second clamping voltage.

2. The overvoltage control circuit according to claim 1, characterized in that: The mode control circuit includes: a timing control circuit and a mode switching circuit; The first input terminal and the second input terminal of the timing control circuit are respectively the first control terminal and the second control terminal of the mode control circuit, and are used to connect the first detection circuit and the second detection circuit respectively; the first mode output terminal of the timing control circuit is connected to the first control terminal of the mode switching circuit to output a first control signal based on the first logic trigger signal; the second mode output terminal of the timing control circuit is connected to the second control terminal of the mode switching circuit to output a second control signal based on the second logic trigger signal; The input end of the mode switching circuit is the input end of the mode control circuit, which is used to connect the output end of the operational amplifier circuit, so that the mode switching circuit outputs the first clamping voltage or the second clamping voltage based on the first control signal and the second control signal.

3. The overvoltage control circuit according to claim 1, characterized in that: The operational amplifier circuit comprises: a first current mirror, an operational amplifier unit, a second current mirror, a third current mirror and a fourth current mirror; The input end of the first current mirror is the bias end of the operational amplifier circuit, which is used to receive the preset bias current, the output end of the first current mirror is connected to the bias end of the operational amplifier unit, and the positive input end and the negative input end of the operational amplifier unit are respectively the positive input end and the negative input end of the operational amplifier circuit; The first output end of the operational amplifier unit is connected to the input end of the second current mirror, and the output end of the second current mirror is connected to the input end of the third current mirror; The second output end of the operational amplifier unit is connected to the input end of the fourth current mirror, and the series connection point of the output end of the third current mirror and the output end of the fourth current mirror is the output end of the operational amplifier circuit; The middle point of the third current mirror and the second output terminal of the operational amplifier unit are respectively the first detection terminal and the second detection terminal of the operational amplifier circuit.

4. The overvoltage control circuit according to claim 1, characterized in that: The overvoltage control circuit also includes: an output circuit, the input end of the output circuit is connected to the output end of the operational amplifier circuit, and the output end of the output circuit is connected to the control end of the clock circuit of the negative charge pump circuit to output a driving signal to the clock circuit.

5. The overvoltage control circuit according to claim 1, characterized in that: The first detection circuit comprises: a first PMOS and a first NMOS whose drains are connected in series; a gate of the first PMOS and a gate of the first NMOS are respectively a first input terminal and a second input terminal of the first detection circuit, and a drain of the first PMOS and a drain of the first NMOS are output terminals of the first detection circuit to output the first logic trigger signal; The second detection circuit includes: a second PMOS and a second NMOS whose drains are connected in series; the gate of the second PMOS and the gate of the second NMOS are respectively the first input terminal and the second input terminal of the second detection circuit, and the drain of the second PMOS and the drain of the second NMOS are the output terminals of the second detection circuit to output the second logic trigger signal.

6. The overvoltage control circuit according to claim 2, characterized in that: The mode switching circuit includes: a first mode circuit and a second mode circuit; The control end of the first mode circuit is the first control end of the mode switching circuit, connected to the first mode output end of the timing control circuit, and used to receive the first control signal; the input end of the first mode circuit is the input end of the mode switching circuit, and used to connect to the output end of the operational amplifier circuit; the output end of the first mode circuit is grounded; The control end of the second mode circuit is the second control end of the mode switching circuit, connected to the second mode output end of the timing control circuit, and used to receive the second control signal. The input end of the second mode circuit is the input end of the mode switching circuit, and is used to connect to the output end of the operational amplifier circuit. The output end of the second mode circuit is the output end of the mode switching circuit.

7. The overvoltage control circuit according to claim 6, characterized in that: The first mode circuit comprises: a third NMOS and a third PMOS, the drain of the third NMOS and the source of the third PMOS are input terminals of the first mode circuit, the gate of the third NMOS and the gate of the third PMOS are control terminals of the first mode circuit, and the source of the third NMOS and the drain of the third PMOS are output terminals of the first mode circuit; The second mode circuit includes: a fourth NMOS and a fourth PMOS, the drain of the fourth NMOS and the source of the fourth PMOS are input terminals of the second mode circuit, the gate of the fourth NMOS and the gate of the fourth PMOS are control terminals of the second mode circuit, and the source of the fourth NMOS and the drain of the fourth PMOS are output terminals of the second mode circuit.

8. A control device, characterized in that: The control device comprises: the overvoltage control circuit, the negative charge pump circuit and the voltage detection circuit according to any one of claims 1 to 7 above; The voltage detection circuit is connected to the output end of the negative charge pump circuit to obtain a detection voltage corresponding to the output voltage; The overvoltage control circuit is connected to the output end of the voltage detection circuit, and the overvoltage control circuit is also connected to the output end of the negative charge pump circuit, so that the negative charge pump circuit outputs an output voltage of a first mode based on a first clamping voltage, or outputs an output voltage of a second mode based on a second clamping voltage.

9. A storage device, characterized in that: The storage device at least comprises: the control device and the storage unit according to claim 8; The output end of the control device is connected to the driving end of the storage unit.

10. An overvoltage control method for a negative charge pump circuit, characterized in that: Applied to the overvoltage control circuit according to any one of claims 1 to 7, the method comprises: When the output voltage of the negative charge pump circuit drops to a preset first inflection point voltage but is greater than a preset second inflection point voltage, the overvoltage control circuit generates a high-level first logic trigger signal and a low-level second logic trigger signal, and outputs a first clamping voltage based on the high-level first logic trigger signal and the low-level second logic trigger signal, so that the negative charge pump circuit outputs an output voltage of a first mode based on the first clamping voltage; When the output voltage of the negative charge pump circuit drops from the output voltage of the first mode to the preset second inflection point voltage, the overvoltage control circuit generates a low-level first logic trigger signal and a high-level second logic trigger signal, and outputs a second clamping voltage based on the low-level first logic trigger signal and the high-level second logic trigger signal, so that the negative charge pump circuit outputs the output voltage of the second mode based on the second clamping voltage.

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