Chirp digital signal generation method and system based on linear feedback shift register

Abstract

The invention relates to a chirp digital signal generation method based on a linear feedback shift register, and the method comprises the steps: firstly configuring a start-stop frequency control word and a signal change rate control word of each chirp signal in an effective period according to a target configuration signal; the method comprises the following steps of: firstly, sequentially performing successive accumulation on a frequency control word FCW and a phase control word PCW along with time steps aiming at each time period in a single period, synchronously superposing the phase control word PCW by combining a phase jitter pseudo-random value of a linear feedback shift register, and finally performing table look-up and complement operations to obtain amplitude signals which are successively output to form time period signals. A single-cycle target chirp digital signal is efficiently formed by the signals in each time period; meanwhile, a corresponding system is designed, the design scheme provides higher frequency spectrum performance, generation of complex multi-segment linear frequency modulation signals is achieved under the condition that hardware resources are not obviously increased, and the flexible configuration capacity of the direct frequency synthesizer is enhanced.

Description

Technical Field

[0001] The invention relates to a chirped digital signal generation method and system based on a linear feedback shift register, and belongs to the technical field of frequency synthesis. Background Art

[0002] Direct digital synthesizer (DDS) is an important method in frequency synthesis technology. Traditional DDS systems usually require complex external control logic and large-capacity lookup tables when generating linear frequency modulation (chirp) signals, resulting in large hardware resource usage and poor flexibility. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a chirped digital signal generation method based on a linear feedback shift register, adopting a new design strategy to efficiently and accurately achieve the acquisition of chirped digital signals.

[0004] In order to solve the above technical problems, the present invention adopts the following technical solution: the present invention designs a chirped digital signal generation method based on a linear feedback shift register, and according to a target configuration signal, performs the following steps to obtain a corresponding single-cycle target chirped digital signal, and then obtains a corresponding target chirped digital periodic signal;

[0005] Step A. According to the target configuration signal, configure the starting frequency control word, the ending frequency control word of each chirp signal valid period in sequence in a single cycle, and the signal change rate control word of each chirp signal valid period, and then enter step B;

[0006] Step B. According to the delay time control word and the pause time control word in the target configuration signal, each delay period, each pause period, and each chirp signal effective period in a single cycle are considered, and each period in the single cycle is sequentially and sequentially accumulated with the time step according to the signal change rate control word corresponding to the period, and the frequency control word FCW is updated, and the phase shift control word is synchronously used as the initial value, and the frequency control word FCW is accumulated with the time step, and the phase control word PCW is updated, and then the corresponding amplitude value is obtained for each phase control word PCW in synchronization, combined with the phase jitter pseudo-random value of the linear feedback shift register, and the corresponding amplitude signal is output to construct the period signal; and then the single-cycle target chirp digital signal is sequentially constituted by the period signals.

[0007] As a preferred technical solution of the present invention: in the step A, according to the starting frequency control word and the ending frequency control word of each chirp signal segment in the target configuration signal, in combination with the linear frequency modulation signal configuration enable signal used to configure each chirp signal segment to be in an effective state or an ineffective state, starting from the preset starting frequency control word, the starting frequency control word and the ending frequency control word of each chirp signal effective time period in a single cycle are sequentially configured;

[0008] At the same time, according to the target signal change rate control word in the target configuration signal, combined with the linear frequency modulation signal configuration enable signal, the signal change rate control word of each chirp signal effective period in a single cycle is configured with the target signal change rate control word.

[0009] As a preferred technical solution of the present invention: in the step B, based on the signal change rate control word corresponding to the preset delay period and the signal change rate control word corresponding to the preset pause period being 0, the following steps B1 to B2 are performed sequentially for each period in the single cycle;

[0010] Step B1. If the time period is a delay time period, the frequency control word FCW is updated with the starting frequency control word of the next time period in its order, and the process proceeds to step B2;

[0011] If the time period is a pause period, the frequency control word FCW is updated with the ending frequency control word of the previous time period, and the process goes to step B2;

[0012] If the time period is a chirp signal valid time period, the frequency control word FCW is updated with the starting frequency control word of the chirp signal valid time period, and the process goes to step B2;

[0013] Step B2. With the time step, for the period, execute the following steps B2-1 to B2-3 to construct a period signal;

[0014] Step B2-1. For the frequency control word FCW, the signal change rate control word corresponding to the time period is incrementally updated with the current time step, and then proceeds to step B2-2;

[0015] Step B2-2. Determine whether the time period is the first time period in a single cycle. If so, the phase control word PCW is formed by the phase shift control word in the target configuration signal, and the frequency control word FCW is incrementally updated with the current time step for the phase control word PCW, and then proceed to step B4; otherwise, the frequency control word FCW is incrementally updated with the current time step for the phase control word PCW, and then proceed to step B2-3;

[0016] Step B2-3. For the phase control word PCW, the phase jitter pseudo-random value generated by the linear feedback shift register, which is equal to the number of bits in the low-order area of ​​the frequency control word FCW, is superimposed and updated with the current time step, and the amplitude value corresponding to the frequency control word FCW is obtained by combining the phase amplitude conversion table of the preset address and amplitude mapping relationship, and the corresponding amplitude signal is output, and then step B2-4 is entered;

[0017] Step B2-4. If the time period is a delay period or a pause period, determine whether the accumulated time step is equal to the delay time control word or the pause time control word in the standard configuration signal. If so, the processing for the time period ends; otherwise, enter the next time step and return to step B2-1;

[0018] If the time period is a valid time period of the chirp signal, determine whether the frequency control word FCW is equal to the end frequency control word of the valid time period of the chirp signal. If so, the processing for the time period ends; otherwise, enter the next time step and return to step B2-1.

[0019] As a preferred technical solution of the present invention, step B2-3 includes the following steps:

[0020] Step B2-3-1. Generate a phase jitter pseudo-random value with a number of bits equal to the number of bits in the low-order area of ​​the phase control word PCW by a linear feedback shift register, and superimpose it with the phase control word PCW, update the phase control word PCW, and then enter step B2-3-2;

[0021] Step B2-3-2. Obtain the high-order area data of the phase control word PCW, and according to the remaining data in the high-order area except the first 2 bits of data, search in the phase-amplitude conversion table of the preset address and amplitude mapping relationship to obtain the amplitude value corresponding to the remaining data, and then enter step B2-3-3;

[0022] Step B2-3-3. Use the first 2 bits of data in the high-order area to perform complement code update on the amplitude values ​​corresponding to the remaining data, and output the corresponding amplitude signal.

[0023] Corresponding to the above, the technical problem to be solved by the present invention is to provide a system for a chirped digital signal generation method based on a linear feedback shift register, so as to accurately obtain the chirped digital signal with efficient and flexible hardware configuration.

[0024] In order to solve the above technical problems, the present invention adopts the following technical solutions: the present invention designs a system of a chirped digital signal generation method based on a linear feedback shift register, comprising a configuration signal receiving and processing module, a chirped signal control module, a chirped signal phase control word accumulation module, and a phase amplitude conversion module, wherein the configuration signal receiving and processing module is connected and communicated with the chirped signal phase control word accumulation module, the chirped signal control module is connected and communicated with the configuration signal receiving and processing module and the chirped signal phase control word accumulation module respectively, the configuration signal receiving and processing module receives the target configuration signal to execute step A, and sends the result obtained in step A to the chirped signal phase control word accumulation module, and at the same time the configuration signal receiving and processing module converts the target configuration signal into the chirped signal phase control word accumulation module. The phase shift enable signal, phase shift control word, delay time control word and pause time control word in the chirp signal control module are sent to the chirp signal control module; based on the control of the chirp signal control module on the chirp signal phase control word accumulation module according to the partial signal in the target configuration signal received by the chirp signal control module, the chirp signal phase control word accumulation module executes step B to accumulate and update the phase control word PCW; the linear feedback shift register is located in the phase-amplitude conversion module, the chirp signal phase control word accumulation module is connected and communicated with the phase-amplitude conversion module, the chirp signal phase control word accumulation module sends the obtained phase control word PCW to the phase-amplitude conversion module, and the phase-amplitude conversion module executes step B according to the phase control word PCW to construct a time period signal.

[0025] As a preferred technical solution of the present invention: the configuration signal receiving and processing module includes two multiplexers, one of which is used to receive the linear frequency modulation signal configuration enable signal in the target configuration signal, and the start frequency control word and the end frequency control word of each chirp signal segment, and configure the start frequency control word and the end frequency control word of each chirp signal valid time period in sequence in a single cycle;

[0026] Another multiplexer is used to receive the linear frequency modulation signal configuration enable signal and the target signal change rate control word in the target configuration signal, and configure the signal change rate control word of each chirp signal valid period in a single cycle.

[0027] As a preferred technical solution of the present invention: the configuration signal receiving and processing module also includes a serial peripheral interface SPI, the input end of the serial peripheral interface SPI is used to receive a target configuration signal from the outside, the output end of the serial peripheral interface SPI is connected to the input ends of two multiplexers in the configuration signal receiving and processing module, and the serial peripheral interface SPI sends part of the data in the target configuration signal processed by it to each multiplexer respectively, and at the same time, the output end of the serial peripheral interface SPI is connected to the chirp signal control module, and the serial peripheral interface SPI sends part of the data in the target configuration signal processed by it to the chirp signal control module.

[0028] As a preferred technical solution of the present invention: the chirp signal phase control word accumulation module includes a multiplexer, a frequency control word accumulator, and a phase control word accumulator; wherein the chirp signal control module is connected to and communicates with the multiplexer, the frequency control word accumulator, and the phase control word accumulator respectively, the multiplexer is connected to and communicates with the frequency control word accumulator, the frequency control word accumulator is simultaneously connected to and communicates with the phase control word accumulator, the frequency control word accumulator receives the signal change rate control word of each chirp signal valid time period output by the configuration signal receiving processing module executing step A, the multiplexer receives the start frequency control word and the end frequency control word of each chirp signal valid time period sequentially output by the configuration signal receiving processing module executing step A, and in the chirp signal control module The block controls the multiplexer and the frequency control word accumulator according to the delay time control word and the pause time control word in the target configuration signal, and the frequency control word accumulator is linked to the multiplexer to execute the frequency control word FCW in step B to be accumulated successively with the time step, and the frequency control word FCW updated successively is sent to the phase control word accumulator. Under the control of the frequency control word accumulator and the phase control word accumulator by the chirp signal control module according to the phase shift enable signal and the phase shift control word in the target configuration signal, the phase control word accumulator is linked to the frequency control word accumulator to execute the phase control word PCW in step B to be accumulated successively with the time step, and the successively updated phase control word PCW constitutes the successive output of the chirp signal phase control word accumulation module with the time step.

[0029] As a preferred technical solution of the present invention: the phase amplitude conversion module also includes a superposition module, a phase address converter, a table lookup module, and a complement module, wherein one of the input ends of the superposition module constitutes the input end of the phase amplitude conversion module, the other input end of the superposition module is connected to the linear feedback shift register, and the output end of the superposition module is connected to the input end of the phase address converter. The superposition module performs superposition and update on the phase control word PCW outputted successively from the chirp signal phase control word accumulation module in combination with the phase jitter pseudo-random value generated by the linear feedback shift register, and outputs the phase control word PCW to the phase address converter; one of the output ends of the phase address converter is connected to the input end of the table lookup module, and the phase The other output end of the address converter is connected to the output end of the table lookup module and the input end of the complement module. The phase address converter obtains the high-order area data of the frequency control word FCW, and sends the remaining data in the high-order area data except the first 2 bits to the table lookup module. At the same time, the phase address converter sends the first 2 bits of the high-order area data to the complement module; the table lookup module searches the phase amplitude conversion table of the preset address and amplitude mapping relationship according to the remaining data in the high-order area data except the first 2 bits, obtains the amplitude value corresponding to the remaining data, and sends it to the complement module, and the complement module uses the first 2 bits of the high-order area data to complement the amplitude value corresponding to the remaining data and update, and outputs the corresponding amplitude signal.

[0030] The chirped digital signal generation method and system based on the linear feedback shift register of the present invention adopts the above technical solution and has the following technical effects compared with the prior art:

[0031] (1) The chirped digital signal generation method based on the linear feedback shift register designed by the present invention first configures the start and end frequency control words of each chirp signal effective period and the signal change rate control word according to the target configuration signal; then considers each delay period, each pause period, and each chirp signal effective period in a single cycle, and sequentially accumulates the frequency control word FCW and the phase control word PCW in sequence with the time step for each period, and combines the phase jitter pseudo-random value of the linear feedback shift register to synchronously superimpose the phase control word PCW, and finally performs table lookup and complement operations. , obtain the amplitude signals output successively, form the time period signals, and then efficiently form the single-cycle target chirp digital signal by the signals of each time period; and design the corresponding system, which jointly realizes the execution of the design method by configuring the signal receiving and processing module, the chirp signal control module, the chirp signal phase control word accumulation module, and the phase amplitude conversion module. The overall design scheme provides higher spectral performance, especially in terms of spurious free dynamic range (SFDR), and realizes the generation of complex multi-segment linear frequency modulation signals without significantly increasing hardware resources, thereby enhancing the flexible configuration capability of the direct frequency synthesizer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a system structure block diagram of the chirp digital signal generation method designed by the present invention;

[0033] Figure 2 It is a state transition diagram of a state machine included in a chirp signal control module in the design system of the present invention;

[0034] Figure 3 It is a schematic diagram of the frequency-time of the output signal matching the state transition of the chirp signal control module in the system designed by the present invention;

[0035] Figure 4 It is a schematic diagram of the improvement of spurious-free dynamic range performance achieved by using a linear feedback shift register to perform phase jitter in the chirp signal phase control word accumulation module designed in the present invention. DETAILED DESCRIPTION

[0036] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0037] The chirp digital signal generation method based on linear feedback shift register designed by the present invention is based on the target configuration signal and the unified system clock. Figure 1 As shown, the following steps A to B are performed to obtain a corresponding single-cycle target chirped digital signal, and then obtain a corresponding target chirped digital periodic signal.

[0038] Step A. Press Figure 2 and Figure 3 As shown, according to the starting frequency control word and the ending frequency control word of each chirp signal segment in the target configuration signal, combined with the linear frequency modulation signal configuration enable signal used to configure each chirp signal segment to be in a valid state or an invalid state, starting from the preset starting frequency control word, the starting frequency control word and the ending frequency control word of each chirp signal valid time period in a single cycle are sequentially configured; at the same time, according to the target signal change rate control word in the target configuration signal, combined with the linear frequency modulation signal configuration enable signal, the signal change rate control word of each chirp signal valid time period in a single cycle is configured with the target signal change rate control word; then enter step B.

[0039] Step B. Press Figure 1As shown, according to the delay time control word and the pause time control word in the target configuration signal, each delay period, each pause period, and each chirp signal effective period in a single cycle are considered, and the signal change rate control word corresponding to the period is successively accumulated with the time step for each period in the single cycle, and the frequency control word FCW is updated, and the phase shift control word is synchronously used as the initial value, and the frequency control word FCW is successively accumulated with the time step to update the phase control word PCW, and then the phase control word PCW is synchronously successively targeted at each phase control word PCW, combined with the phase jitter pseudo-random value of the linear feedback shift register, The corresponding amplitude value is obtained, the corresponding amplitude signal is output, and the time period signal is constructed; then the single-cycle target chirp digital signal is sequentially constructed by the time period signals. In practical applications, the linear feedback shift register specifically adopts a left-shift feedback shift register (LFSR). The left-shift feedback shift register (LFSR) can generate pseudo-random numbers with certain statistical characteristics. Specifically, the feedback polynomial selection of the LFSR is optimized to achieve lower noise characteristics and higher randomness, increase the randomness of the output signal, thereby reducing the distortion caused by phase truncation and improving the spurious-free dynamic range (SFDR).

[0040] In practical applications, the above step B, according to the delay time control word and the pause time control word in the target configuration signal, considers each delay period, each pause period, and each chirp signal effective period in a single cycle, based on the signal change rate control word corresponding to the preset delay period and the signal change rate control word corresponding to the preset pause period are both 0, and sequentially for each period in the single cycle, according to Figure 1 As shown, perform the following steps B1 to B2.

[0041] Step B1. If the time period is a delay time period, the frequency control word FCW is updated with the starting frequency control word of the next time period in its order, and the process proceeds to step B2;

[0042] If the time period is a pause period, the frequency control word FCW is updated with the ending frequency control word of the previous time period, and the process goes to step B2;

[0043] If the time period is a chirp signal valid time period, the frequency control word FCW is updated with the starting frequency control word of the chirp signal valid time period, and the process goes to step B2.

[0044] Make necessary adjustments and preparations as described above to ensure the continuity and stability of signal output, and the module supports reserved delays to adapt to the response time of external devices.

[0045] Step B2. With the time step, for the period, execute the following steps B2-1 to B2-3 to construct a period signal.

[0046] Step B2-1. For the frequency control word FCW, the signal change rate control word corresponding to the time period is incrementally updated along with the current time step, and then proceed to step B2-2.

[0047] Step B2-2. Determine whether the time period is the first time period in a single cycle. If so, use the phase shift control word in the target configuration signal to form a phase control word PCW, and incrementally update the phase control word PCW with the frequency control word FCW along with the current time step, and then enter step B4; otherwise, directly use the phase control word PCW with the frequency control word FCW to incrementally update the current time step, and then enter step B2-3.

[0048] Step B2-3. For the phase control word PCW, the phase jitter pseudo-random value generated by the linear feedback shift register, which is equal to the number of bits in the low-order area of ​​the frequency control word FCW, is superimposed and updated with the current time step, and combined with the phase-amplitude conversion table of the preset address and amplitude mapping relationship, the amplitude value corresponding to the frequency control word FCW is obtained, the corresponding amplitude signal is output, and then step B2-4 is entered.

[0049] In actual application, the above steps B2-3 are Figure 1 As shown, the following steps B2-3-1 to B2-3-3 are actually performed.

[0050] Step B2-3-1. A phase jitter pseudo-random value whose bit number is equal to the bit number in the low-order area of ​​the phase control word PCW is generated by a linear feedback shift register, and is superimposed with the phase control word PCW. The phase control word PCW is updated, and then step B2-3-2 is entered.

[0051] Step B2-3-2. Obtain the high-order area data of the phase control word PCW, and based on the remaining data in the high-order area data except the first 2 bits of data, search in the phase-amplitude conversion table with a preset address and amplitude mapping relationship to obtain the amplitude value corresponding to the remaining data, and then enter step B2-3-3; the remaining data in the high-order area data except the first 2 bits of data is the actual table address quantity.

[0052] Step B2-3-3. Use the first 2 bits of data in the high-order area to perform complement code update on the amplitude values ​​corresponding to the remaining data, and output the corresponding amplitude signal.

[0053] Step B2-4. If the time period is a delay period or a pause period, determine whether the accumulated time step is equal to the delay time control word or the pause time control word in the standard configuration signal. If so, the processing for the time period ends; otherwise, enter the next time step and return to step B2-1;

[0054] If the time period is a valid time period of the chirp signal, determine whether the frequency control word FCW is equal to the end frequency control word of the valid time period of the chirp signal. If so, the processing for the time period ends; otherwise, enter the next time step and return to step B2-1.

[0055] In practical application, a specific system is further designed to implement the chirped digital signal generation method based on linear feedback shift register. Figure 1 As shown, the system includes a configuration signal receiving and processing module, a chirp signal control module, a chirp signal phase control word accumulation module, and a phase amplitude conversion module, wherein the configuration signal receiving and processing module is connected and communicated with the chirp signal phase control word accumulation module, and the chirp signal control module is connected and communicated with the configuration signal receiving and processing module and the chirp signal phase control word accumulation module respectively, the configuration signal receiving and processing module receives the target configuration signal to execute step A, and sends the result obtained in step A to the chirp signal phase control word accumulation module, and at the same time, the configuration signal receiving and processing module converts the phase shift enable signal, phase shift control word, delay time length control word, and pause in the target configuration signal into a phase amplitude conversion module. The duration control word is sent to the chirp signal control module; based on the chirp signal control module controlling the chirp signal phase control word accumulation module according to the partial signal in the received target configuration signal, the chirp signal phase control word accumulation module executes step B to accumulate and update the phase control word PCW; the linear feedback shift register is located in the phase-amplitude conversion module, the chirp signal phase control word accumulation module is connected and communicated with the phase-amplitude conversion module, the chirp signal phase control word accumulation module sends the executed phase control word PCW to the phase-amplitude conversion module, and the phase-amplitude conversion module executes step B according to the phase control word PCW to construct a time period signal.

[0056] In a specific design application, the configuration signal receiving and processing module includes two multiplexers, one of which is used to receive the linear frequency modulation signal configuration enable signal in the target configuration signal, and the start frequency control word and the end frequency control word of each chirp signal segment, and configure the start frequency control word and the end frequency control word of each chirp signal valid time period in sequence in a single cycle; the other multiplexer is used to receive the linear frequency modulation signal configuration enable signal and the target signal change rate control word in the target configuration signal, and configure the signal change rate control word of each chirp signal valid time period in a single cycle.

[0057] The designed configuration signal receiving and processing module also includes a serial peripheral interface SPI. The input end of the serial peripheral interface SPI is used to receive a target configuration signal from the outside. The output end of the serial peripheral interface SPI is connected to the input ends of two multiplexers in the configuration signal receiving and processing module. The serial peripheral interface SPI sends part of the data in the target configuration signal processed by it to each multiplexer respectively. At the same time, the output end of the serial peripheral interface SPI is connected to the chirp signal control module, and the serial peripheral interface SPI sends part of the data in the target configuration signal processed by it to the chirp signal control module.

[0058] The chirp signal phase control word accumulation module is designed to include a multiplexer, a frequency control word accumulator, and a phase control word accumulator; wherein the chirp signal control module is connected to and communicated with the multiplexer, the frequency control word accumulator, and the phase control word accumulator respectively, the multiplexer is connected to and communicated with the frequency control word accumulator, the frequency control word accumulator is connected to and communicated with the phase control word accumulator at the same time, the frequency control word accumulator receives the signal change rate control word of each chirp signal valid time period output by the configuration signal receiving processing module executing step A, the multiplexer receives the start frequency control word and the end frequency control word of each chirp signal valid time period in sequence in a single cycle output by the configuration signal receiving processing module executing step A, and the chirp signal control module receives the start frequency control word and the end frequency control word of each chirp signal valid time period in sequence in the single cycle output by the configuration signal receiving processing module executing step A, and the chirp signal control module receives the start frequency control word and the end frequency control word of each chirp signal valid time period in sequence in accordance with the target configuration. Under the control of the delay time control word and the pause time control word in the signal on the multiplexer and the frequency control word accumulator, the frequency control word accumulator contacts the multiplexer to execute the frequency control word FCW in step B to be accumulated successively with the time step, and the frequency control word FCW updated successively is sent to the phase control word accumulator. Under the control of the frequency control word accumulator and the phase control word accumulator by the chirp signal control module according to the phase shift enable signal and the phase shift control word in the target configuration signal, the phase control word accumulator contacts the frequency control word accumulator to execute the phase control word PCW in step B to be accumulated successively with the time step, and the successively updated phase control word PCW constitutes the successive output of the chirp signal phase control word accumulation module with the time step.

[0059] The designed phase amplitude conversion module also includes a superposition module, a phase address converter, a table lookup module, and a complement module, wherein one of the input ends of the superposition module constitutes the input end of the phase amplitude conversion module, the other input end of the superposition module is connected to the linear feedback shift register, and the output end of the superposition module is connected to the input end of the phase address converter. The superposition module performs superposition and update on the phase control word PCW outputted successively from the chirp signal phase control word accumulation module in combination with the phase jitter pseudo-random value generated by the linear feedback shift register, and outputs the phase control word PCW to the phase address converter; one of the output ends of the phase address converter is connected to the input end of the table lookup module, and the other output end of the phase address converter is connected to the output end of the table lookup module. The input end of the complementary code module is connected, and the phase address converter obtains the high-order area data of the frequency control word FCW, and sends the remaining data in the high-order area data except the first 2 bits to the table lookup module. At the same time, the phase address converter sends the first 2 bits of the high-order area data to the complementary code module, and the remaining data in the high-order area data except the first 2 bits are the actual table address quantity; the table lookup module searches the phase amplitude conversion table of the preset address and amplitude mapping relationship according to the remaining data in the high-order area data except the first 2 bits, obtains the amplitude value corresponding to the remaining data, and sends it to the complementary code module, and the complementary code module uses the first 2 bits of the high-order area data to complement the amplitude value corresponding to the remaining data and update, and outputs the corresponding amplitude signal.

[0060] The design of the present invention is used in practical applications, such as Figure 4 The schematic diagram of the improvement in spurious-free dynamic range performance achieved after the chirp signal phase control word accumulation module uses a linear feedback shift register to perform phase jitter is shown. It is obvious that the present invention can minimize the impact of clock jitter on the signal, ensure that the amplitude adjustment of the signal is highly accurate, and maintain the quality of the output signal.

[0061] The chirped digital signal generation method based on the linear feedback shift register designed in the above technical scheme first configures the start and end frequency control words and the signal change rate control word of each chirp signal effective period according to the target configuration signal; then considers each delay period, each pause period, and each chirp signal effective period in a single cycle, and sequentially accumulates the frequency control word FCW and the phase control word PCW in sequence for each period with the time step, and combines the phase jitter pseudo-random value of the linear feedback shift register to synchronously superimpose the phase control word PCW, and finally performs table lookup and complement operations to obtain the amplitude signals output successively to form a period signal, and then the single-cycle target chirp digital signal is efficiently constituted by each period signal.

[0062] The above design improves the spurious free dynamic range (SFDR), ensures better signal quality at specific frequency points, reduces spurious components in the spectrum, improves the clarity and reliability of the overall signal, and minimizes the impact of clock jitter on the signal through precise clock management and synchronization mechanisms, ensures high accuracy of signal amplitude adjustment, and maintains the quality of the output signal. The lookup table is designed using a high-precision amplitude quantization method to better restore the signal waveform.

[0063] The present invention also designs a corresponding system, which is configured by a signal receiving and processing module, a chirp signal control module, a chirp signal phase control word accumulation module, and a phase amplitude conversion module to jointly implement the execution of the design method, dynamically adjust the frequency control word and the phase control word, and realize the flexible generation of multi-segment linear frequency modulation signals, so that the system can quickly respond to external changes and provide more abundant spectrum output options. Users can set different frequency modulation rates and phase adjustment strategies according to actual application scenarios. In addition, the chirp signal control module introduces a state machine unit, and complex spectrum configuration is achieved by adding a state machine unit, so that the system can flexibly configure a variety of spectrum output modes without significantly increasing hardware resources to meet the needs of different application scenarios. The state machine design supports multi-state transfer and can quickly switch different signal segment configurations.

[0064] The design provides a stronger chirp signal configuration capability by adding a state machine unit without significantly increasing the overall hardware resources of the lookup table structure direct frequency synthesizer, and combines the phase control word to judge the phase jitter amount, so that it has better spurious-free dynamic range (SFDR) spectrum performance at some special frequency points.

[0065] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A chirped digital signal generation method based on a linear feedback shift register, characterized in that: According to the target configuration signal, the following steps are performed to obtain a corresponding single-cycle target chirped digital signal, and then obtain a corresponding target chirped digital periodic signal; Step A. According to the target configuration signal, configure the starting frequency control word, the ending frequency control word of each chirp signal valid period in sequence in a single cycle, and the signal change rate control word of each chirp signal valid period, and then enter step B; Step B. According to the delay time control word and the pause time control word in the target configuration signal, each delay period, each pause period, and each chirp signal effective period in a single cycle are considered, and each period in the single cycle is sequentially and sequentially accumulated with the time step according to the signal change rate control word corresponding to the period, and the frequency control word FCW is updated, and the phase shift control word is synchronously used as the initial value, and the frequency control word FCW is accumulated with the time step, and the phase control word PCW is updated, and then the corresponding amplitude value is obtained for each phase control word PCW in synchronization, combined with the phase jitter pseudo-random value of the linear feedback shift register, and the corresponding amplitude signal is output to construct the period signal; and then the single-cycle target chirp digital signal is sequentially constituted by the period signals.

2. The chirped digital signal generation method based on a linear feedback shift register according to claim 1, characterized in that: In the step A, according to the starting frequency control word and the ending frequency control word of each chirp signal segment in the target configuration signal, in combination with the linear frequency modulation signal configuration enable signal used to configure each chirp signal segment to be in an effective state or an ineffective state, starting from the preset starting frequency control word, the starting frequency control word and the ending frequency control word of each chirp signal effective time period in a single cycle are sequentially configured; At the same time, according to the target signal change rate control word in the target configuration signal, combined with the linear frequency modulation signal configuration enable signal, the signal change rate control word of each chirp signal effective period in a single cycle is configured with the target signal change rate control word.

3. The chirped digital signal generation method based on a linear feedback shift register according to claim 1 or 2, characterized in that: In the step B, based on the signal change rate control word corresponding to the preset delay period and the signal change rate control word corresponding to the preset pause period being 0, the following steps B1 to B2 are performed sequentially for each period in the single cycle; Step B1. If the time period is a delay time period, the frequency control word FCW is updated with the starting frequency control word of the next time period in its order, and the process proceeds to step B2; If the time period is a pause period, the frequency control word FCW is updated with the ending frequency control word of the previous time period, and the process goes to step B2; If the time period is a chirp signal valid time period, the frequency control word FCW is updated with the starting frequency control word of the chirp signal valid time period, and the process goes to step B2; Step B2. With the time step, for the period, execute the following steps B2-1 to B2-3 to construct a period signal; Step B2-1. For the frequency control word FCW, the signal change rate control word corresponding to the time period is incrementally updated with the current time step, and then proceeds to step B2-2; Step B2-2 determines whether the time period is the first time period in a single cycle, if so, the phase control word PCW is formed by the phase shift control word in the target configuration signal, and the frequency control word FCW is incrementally updated with the current time step for the phase control word PCW, and then proceeds to step B4; Otherwise, directly update the phase control word PCW with the frequency control word FCW according to the current time step, and then go to step B2-3; Step B2-3. For the phase control word PCW, the phase jitter pseudo-random value generated by the linear feedback shift register, which is equal to the number of bits in the low-order area of ​​the frequency control word FCW, is superimposed and updated with the current time step, and the amplitude value corresponding to the frequency control word FCW is obtained by combining the phase amplitude conversion table of the preset address and amplitude mapping relationship, and the corresponding amplitude signal is output, and then step B2-4 is entered; Step B2-4. If the time period is a delay period or a pause period, it is determined whether the accumulated time step is equal to the delay duration control word or the pause duration control word in the standard configuration signal, and if so, the processing for the time period ends; Otherwise, proceed to the next time step and return to step B2-1; If the time period is a valid time period of the chirp signal, determine whether the frequency control word FCW is equal to the end frequency control word of the valid time period of the chirp signal. If so, the processing for the time period ends; otherwise, enter the next time step and return to step B2-1.

4. The chirped digital signal generation method based on a linear feedback shift register according to claim 3, characterized in that , the step B2-3 comprises the following steps: Step B2-3-1. Generate a phase jitter pseudo-random value with a number of bits equal to the number of bits in the low-order area of ​​the phase control word PCW by a linear feedback shift register, and superimpose it with the phase control word PCW, update the phase control word PCW, and then enter step B2-3-2; Step B2-3-2. Obtain the high-order area data of the phase control word PCW, and according to the remaining data in the high-order area except the first 2 bits of data, search in the phase-amplitude conversion table of the preset address and amplitude mapping relationship to obtain the amplitude value corresponding to the remaining data, and then enter step B2-3-3; Step B2-3-3. Use the first 2 bits of data in the high-order area to perform complement code update on the amplitude values ​​corresponding to the remaining data, and output the corresponding amplitude signal.

5. A system for implementing the chirped digital signal generation method based on a linear feedback shift register as claimed in any one of claims 1 to 4, characterized in that: The invention comprises a configuration signal receiving and processing module, a chirp signal control module, a chirp signal phase control word accumulation module, and a phase amplitude conversion module, wherein the configuration signal receiving and processing module is connected and communicated with the chirp signal phase control word accumulation module, and the chirp signal control module is connected and communicated with the configuration signal receiving and processing module and the chirp signal phase control word accumulation module respectively, the configuration signal receiving and processing module receives the target configuration signal to execute step A, and sends the result obtained in step A to the chirp signal phase control word accumulation module, and at the same time, the configuration signal receiving and processing module converts the phase shift enable signal, the phase shift control word, the delay time length control word, and the pause time length in the target configuration signal into the phase shift enable signal, the phase shift control word, the delay time length control word, and the pause time length in the target configuration signal into the phase amplitude conversion module. The control word is sent to the chirp signal control module; based on the chirp signal control module controlling the chirp signal phase control word accumulation module according to the partial signal in the target configuration signal received, the chirp signal phase control word accumulation module executes step B to accumulate and update the phase control word PCW; the linear feedback shift register is located in the phase-amplitude conversion module, the chirp signal phase control word accumulation module is connected and communicated with the phase-amplitude conversion module, the chirp signal phase control word accumulation module sends the executed phase control word PCW to the phase-amplitude conversion module, and the phase-amplitude conversion module executes step B according to the phase control word PCW to construct a time period signal.

6. The system of the chirped digital signal generation method based on the linear feedback shift register according to claim 5, characterized in that: The configuration signal receiving and processing module includes two multiplexers, one of which is used to receive the linear frequency modulation signal configuration enable signal in the target configuration signal, and the start frequency control word and the end frequency control word of each chirp signal segment, and configure the start frequency control word and the end frequency control word of each chirp signal valid time period in sequence in a single cycle; Another multiplexer is used to receive the linear frequency modulation signal configuration enable signal and the target signal change rate control word in the target configuration signal, and configure the signal change rate control word of each chirp signal valid period in a single cycle.

7. The system of the chirped digital signal generation method based on the linear feedback shift register according to claim 6, characterized in that: The configuration signal receiving and processing module also includes a serial peripheral interface SPI, the input end of the serial peripheral interface SPI is used to receive a target configuration signal from the outside, the output end of the serial peripheral interface SPI is connected to the input ends of two multiplexers in the configuration signal receiving and processing module, and the serial peripheral interface SPI sends part of the data in the target configuration signal processed by it to each multiplexer respectively, and at the same time, the output end of the serial peripheral interface SPI is connected to the chirp signal control module, and the serial peripheral interface SPI sends part of the data in the target configuration signal processed by it to the chirp signal control module.

8. The system of the chirped digital signal generation method based on the linear feedback shift register according to claim 5, characterized in that: The chirp signal phase control word accumulation module comprises a multiplexer, a frequency control word accumulator, and a phase control word accumulator; wherein the chirp signal control module is connected to and communicated with the multiplexer, the frequency control word accumulator, and the phase control word accumulator respectively, the multiplexer is connected to and communicated with the frequency control word accumulator, the frequency control word accumulator is simultaneously connected to and communicated with the phase control word accumulator, the frequency control word accumulator receives the signal change rate control word of each chirp signal valid period output by the configuration signal receiving processing module executing step A, the multiplexer receives the start frequency control word and the end frequency control word of each chirp signal valid period in sequence in a single cycle output by the configuration signal receiving processing module executing step A, and the chirp signal control module receives the start frequency control word and the end frequency control word of each chirp signal valid period in sequence in a single cycle according to the target configuration. Under the control of the delay time control word and the pause time control word in the signal on the multiplexer and the frequency control word accumulator, the frequency control word accumulator contacts the multiplexer to execute the frequency control word FCW in step B to be accumulated successively with the time step, and the frequency control word FCW updated successively is sent to the phase control word accumulator. Under the control of the frequency control word accumulator and the phase control word accumulator by the chirp signal control module according to the phase shift enable signal and the phase shift control word in the target configuration signal, the phase control word accumulator contacts the frequency control word accumulator to execute the phase control word PCW in step B to be accumulated successively with the time step, and the successively updated phase control word PCW constitutes the successive output of the chirp signal phase control word accumulation module with the time step.

9. The system of the chirped digital signal generation method based on the linear feedback shift register according to claim 5, characterized in that: The phase amplitude conversion module also includes a superposition module, a phase address converter, a table lookup module, and a complement module, wherein one of the input ends of the superposition module constitutes the input end of the phase amplitude conversion module, the other input end of the superposition module is connected to the linear feedback shift register, and the output end of the superposition module is connected to the input end of the phase address converter. The superposition module performs superposition and update on the phase control word PCW outputted successively from the chirp signal phase control word accumulation module in combination with the phase jitter pseudo-random value generated by the linear feedback shift register, and outputs the phase control word PCW to the phase address converter; one of the output ends of the phase address converter is connected to the input end of the table lookup module, and the other input end of the phase address converter is connected to the input end of the table lookup module. An output end is connected to the output end of the table lookup module and the input end of the complement module. The phase address converter obtains the high-order area data of the frequency control word FCW, and sends the remaining data in the high-order area data except the first 2 bits to the table lookup module. At the same time, the phase address converter sends the first 2 bits of the high-order area data to the complement module; the table lookup module searches the phase amplitude conversion table of the preset address and amplitude mapping relationship according to the remaining data in the high-order area data except the first 2 bits, obtains the amplitude value corresponding to the remaining data, and sends it to the complement module. The complement module uses the first 2 bits of the high-order area data to complement the amplitude value corresponding to the remaining data and update it, and outputs the corresponding amplitude signal.

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