FPGA (Field Programmable Gate Array) chip data sorting method, FPGA chip and electronic equipment

Abstract

The invention relates to an FPGA (Field Programmable Gate Array) chip data sorting method, an FPGA chip and electronic equipment. The FPGA chip is in communication connection with an extended memory, and the method comprises the following steps: acquiring to-be-sorted data, and writing the to-be-sorted data into the memory; reading the to-be-sorted data in the memory; sorting the to-be-sorted data for a single time according to a preset sorting frequency; after each time of single-time sequencing is completed, sequenced ordered data in a specified range is output each time. According to the scheme provided by the invention, the FPGA chip can be combined with the memory, the memory is adopted to cache the to-be-sorted data, and the problem of insufficient cache resources on the FPGA chip is solved, so that a large amount of data can be quickly sorted in the FPGA chip, and the method is simple in FPGA implementation logic, less in sorting time consumption and high in sorting stability.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to an FPGA chip data sorting method, an FPGA chip, and an electronic device. Background Art

[0002] With the rapid development of information technology, data processing speed has become a key factor in system response time. Sorting algorithm is a basic and indispensable data processing operation in the computer field. Through sorting, data can be fully arranged in a certain order, thereby reducing the time complexity of subsequent operations.

[0003] FPGA (Field Programmable Gate Array) is a chip whose internal structure can be changed through programming. Due to its high flexibility and customizability, it plays an important role in many fields. Currently, most of the sorting algorithms implemented in FPGA use traditional sorting algorithms, such as insertion sorting algorithm, selection sorting algorithm, bubble sorting algorithm, etc. The above algorithms usually need to apply for storage space for the data to be sorted in the FPGA chip, which has a high time complexity and requires frequent comparison and exchange of the data to be sorted. When the amount of data to be sorted is large, there are two difficulties in the implementation of the sorting algorithm: on the one hand, the storage resources of the FPGA chip are limited and may not be enough to cache all the data to be sorted; on the other hand, frequent data comparison and exchange will greatly increase the total time consumption of sorting. Based on the above two difficulties, the sorting algorithm that can be implemented in the FPGA chip is only suitable for sorting a small amount of data. When the amount of data is large, the implementation of the sorting function is more difficult. Summary of the invention

[0004] In order to solve or partially solve the problems existing in the related art, the present application provides an FPGA chip data sorting method, an FPGA chip, and an electronic device, which can realize fast sorting of large amounts of data in the FPGA chip.

[0005] The first aspect of the present application provides a method for sorting data in an FPGA chip, wherein the FPGA chip is communicatively connected to an extended memory, and the method comprises: Acquire data to be sorted, and write the data to be sorted into the memory; Reading the data to be sorted in the memory; Sorting the data to be sorted once according to a preset number of sorting times; After each single sort is completed, the sorted and ordered data in the specified range is output each time.

[0006] Preferably, the step of performing a single sorting on the data to be sorted according to a preset number of sorting times comprises: For each single sorting, count the number of occurrences of each data in the data to be sorted, obtain the initial score of each data, and generate a score sequence according to the initial score; The storage value of each of the data is determined according to the fractional sequence, and the data to be sorted is sorted based on the storage value.

[0007] Preferably, determining the storage value of each of the data according to the fractional sequence, and sorting the data to be sorted based on the storage value comprises: Calculate the sum of the first n items of each initial score in the score sequence in sequence as the storage value of the data corresponding to the initial score; Read each of the data to be sorted, and output the storage value corresponding to the data; each time the data appears, the storage value corresponding to the data is reduced by one; After the reading of the data to be sorted is completed, the final stored value of the data to be sorted is obtained; The data to be sorted is sorted according to the final stored value.

[0008] Preferably, generating a score sequence according to the initial score comprises: Arrange the data in order of size, arrange the initial scores of the data according to the arrangement order of the data, and generate a score sequence corresponding to the initial scores.

[0009] Preferably, The preset sorting times are determined as follows: Determine the limit value of each output data of the FPGA chip; Determine the preset number of sorting times according to the amount of the data to be sorted and the limit of the data output by the FPGA chip each time; After each single sorting is completed, outputting the sorted ordered data in the specified range each time includes: After each single sort is completed, For the first output, output a preset number of sorted and ordered data ranked in the front or back columns, wherein the preset number does not exceed the limit of the FPGA chip outputting data each time; For non-first output, in addition to the ordered data output last time, a preset number of sorted ordered data ranked in the front or back column are output.

[0010] Preferably, the memory includes a dynamic random access memory DDR.

[0011] A second aspect of the present application provides an FPGA chip, wherein the FPGA chip is communicatively connected to an extended memory, and the chip comprises: A writing module, used for acquiring the data to be sorted, and writing the data to be sorted into the memory; A reading module, used for reading the data to be sorted in the memory; A sorting module, used to sort the data to be sorted once according to a preset sorting number; The output module is used to output the sorted ordered data in a specified range each time after each single sort is completed.

[0012] Preferably, the sorting module includes: A statistical submodule is used to count the number of occurrences of each data in the data to be sorted for each single sort, obtain an initial score for each data, and generate a score series according to the initial score; The sorting submodule is used to determine the storage value of each of the data according to the fractional sequence, and sort the data to be sorted based on the storage value.

[0013] Preferably, the chip further comprises: A limit value determination module, used to determine the limit value of the output data of the FPGA chip each time; A sorting times module, used to determine the preset sorting times according to the amount of the data to be sorted and the limit of the data output by the FPGA chip each time; The output module is also used for: after each single sorting is completed, for the first output, outputting a preset number of sorted ordered data ranked in the front or back column, wherein the preset number does not exceed the limit of the data output by the FPGA chip each time; for non-first output, in addition to the ordered data output last time, outputting a preset number of sorted ordered data ranked in the front or back column.

[0014] A third aspect of the present application provides an electronic device, including: Processor; and The memory stores executable codes thereon, and when the executable codes are executed by the processor, the processor is caused to execute the method as described above.

[0015] The technical solution provided by the present application may include the following beneficial effects: The embodiment of the present application provides a method for sorting data in an FPGA chip, wherein the FPGA chip is connected to an extended memory for communication, and the method obtains the data to be sorted and writes the sorted data into the memory; reads the data to be sorted in the memory; sorts the data to be sorted, and groups them after the sorting is completed; and sequentially outputs the ordered data of each group to obtain the final sorting result. The solution of the present application can combine the FPGA chip with the extended memory, use the memory to cache the data to be sorted, solve the problem of insufficient cache resources on the FPGA chip, split the sorting of a large amount of data into a processing flow of multiple single sortings, and realize fast sorting of a large amount of data in the FPGA chip. The FPGA implementation logic of this method is simple, the sorting takes less time, and the sorting stability is high.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present application will become more apparent by describing in more detail the exemplary embodiments of the present application in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the present application.

[0018] Figure 1 It is a flowchart of the FPGA chip data sorting method shown in the embodiment of the present application; Figure 2 It is another flowchart of the FPGA chip data sorting method shown in the embodiment of the present application; Figure 3a is a schematic diagram of data to be sorted shown in an embodiment of the present application; Figure 3b is a schematic diagram of a fractional sequence shown in an embodiment of the present application; Figure 3c is a schematic diagram of a fractional series accumulation deformation shown in an embodiment of the present application; Figure 3d is another schematic diagram of a fractional sequence shown in an embodiment of the present application; Figure 3e is another schematic diagram of a fractional sequence shown in an embodiment of the present application; Figure 3f is another schematic diagram of a fractional sequence shown in an embodiment of the present application; Figure 3g is another schematic diagram of a fractional sequence shown in an embodiment of the present application; Figure 4 It is a schematic diagram of the structure of the FPGA chip shown in the embodiment of the present application; Figure 5is another structural schematic diagram of the FPGA chip shown in the embodiment of the present application; Figure 6 It is a schematic diagram of the structure of an electronic device shown in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0020] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0021] It should be understood that although the terms "first", "second", "third", etc. may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0022] When the amount of data to be sorted is large, there are two difficulties in implementing the sorting algorithm: on the one hand, the storage resources of the FPGA chip are limited and may not be enough to cache all the data to be sorted; on the other hand, frequent data comparison and exchange will greatly increase the total time consumed in sorting. Based on the above two difficulties, the sorting algorithm that can be implemented in the FPGA chip is only suitable for sorting a small amount of data. When the amount of data is large, the implementation of the sorting function is more difficult.

[0023] In response to the above problems, an embodiment of the present application provides an FPGA chip data sorting method, which can combine the FPGA chip with a memory, use the memory to cache the data to be sorted, solve the problem of insufficient cache resources on the FPGA chip, and split the sorting of a large amount of data into multiple single sorting processing flows, so as to realize fast sorting of a large amount of data in the FPGA chip. The FPGA implementation logic of this method is simple, the sorting takes less time, and the sorting stability is high.

[0024] The technical solution of the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0025] Figure 1 It is a flow chart of the FPGA chip data sorting method shown in the embodiment of the present application.

[0026] See also Figure 1 , the method comprising: Step 101, obtaining the data to be sorted, and writing the data to be sorted into a memory.

[0027] In the embodiment of the present application, the FPGA chip is connected to the extended memory for data exchange. FPGA is a chip whose internal structure can be changed by programming, and can be used to sort data.

[0028] The FPGA chip obtains the data to be sorted through the bus, and after receiving the data to be sorted, it sends a write request signal to the memory, thereby caching the data to be sorted in the extended memory. Using the memory to cache the data to be sorted can solve the problem of insufficient cache resources on the FPGA chip.

[0029] The memory may be a dynamic random access memory DDR (Double Data Rate Synchronous Dynamic Random Access Memory). Equipped with DDR memory on the FPGA chip, data read and write access is more efficient.

[0030] Step 102, read the data to be sorted in the memory.

[0031] The FPGA chip reads the data to be sorted in the memory for initialization.

[0032] Step 103, sorting the data to be sorted individually according to a preset sorting number.

[0033] FPGA chips can use counting sorting to sort all the data in the sorted data in the order of data value size. The main idea of ​​counting sorting is to calculate the position of each element in the sorted array by counting the number of occurrences of each element, thereby achieving sorting.

[0034] Since the on-chip resources of FPGA are limited, when the amount of data to be sorted is large, all the data to be sorted cannot be output at the same time after sorting. Therefore, the data to be sorted can be sorted individually according to a preset number of sorting times.

[0035] Among them, sorting the data to be sorted separately according to the preset sorting times includes: for each single sorting, counting the number of times each data in the data to be sorted appears, obtaining the initial score of each data, and generating a score series according to the initial score; determining the storage value of each data according to the score series; and sorting the data to be sorted based on the storage value.

[0036] The preset number of sorting times is determined in the following manner: determining a limit value for each data output by the FPGA chip; and determining the preset number of sorting times according to the amount of the data to be sorted and the limit value for each data output by the FPGA chip.

[0037] Since the RAM (Random Access Memory) storage resources on the FPGA chip are limited, when the amount of data to be sorted is large, all sorted data cannot be output at the same time. Therefore, the sorted data can be output in multiple times. The limit of the data output by the FPGA chip each time can be determined first. In one example, the limit of the data output by the FPGA chip each time is 2^15=32768.

[0038] The preset number of sorting times can be determined according to the number of data to be sorted and the limit of the FPGA chip outputting data each time. For example, if 130,000 data to be sorted need to be sorted from large to small, due to the on-chip resource limitation of the FPGA chip, the limit of the FPGA chip outputting data each time is 32768, and all the data to be sorted can be sorted four times.

[0039] Step 104: after each single sorting is completed, output the sorted ordered data in the specified range each time.

[0040] After each single sorting of the data to be sorted, the sorted ordered data of the specified range can be output each time. For example, when the limit of the output data of the FPGA chip each time is 32768, 130,000 data to be sorted can be sorted 4 times, and the ordered data of the specified range can be output after each single sorting. After the first sorting, the largest first 32768 data can be output. After the second sorting, the largest first 32768 data of the remaining data except the first output data are output. After the third sorting, the largest first 32768 data of the remaining data except the first two output data are output. After the fourth sorting, the remaining data except the first three output data are output. Then determine whether all the data are output. If all are output, the sorting is completed, thereby obtaining the final sorting result.

[0041] The solution of the embodiment of the present application can be applied to deep learning scenarios such as visual acceleration scenarios, image processing scenarios, data analysis scenarios, neural networks, etc. based on FPGA chip processing. Within 5ms, FPGA can complete the sorting of 100,000 data to be sorted, with high sorting efficiency and low time consumption.

[0042] The embodiment of the present application provides a method for sorting data in an FPGA chip, wherein the FPGA chip is connected to an extended memory for communication, and the method obtains data to be sorted, writes the sorted data into the memory; reads the data to be sorted in the memory; sorts the data to be sorted once according to a preset number of sorting times; and outputs sorted ordered data of a specified range each time after each single sorting is completed. The solution of the present application can combine the FPGA chip with the memory, use the memory to cache the data to be sorted, solve the problem of insufficient cache resources on the FPGA chip, split the sorting of a large amount of data into a processing flow of multiple single sortings, and realize fast sorting of a large amount of data in the FPGA chip. The FPGA implementation logic of this method is simple, the sorting takes less time, and the sorting stability is high.

[0043] Figure 2 It is another flow chart of the FPGA chip data sorting method shown in the embodiment of the present application.

[0044] In the embodiment of the present application, the FPGA chip is communicatively connected to the extended DDR memory to perform data exchange.

[0045] See also Figure 2 , the method comprising: Step 201, obtaining the data to be sorted, and writing the data to be sorted into the DDR memory.

[0046] Step 202, read the data to be sorted in the DDR memory.

[0047] Step 201 and step 202 are similar to step 101 and step 102 , and the description of step 101 and step 102 may be referred to, and will not be repeated here.

[0048] Step 203, for each single sorting, count the number of times each data in the data to be sorted appears, obtain the initial score of each data, and generate a score sequence according to the initial score.

[0049] For each single sorting, the embodiment of the present application adopts a counting sorting method to implement the sorting of the data to be sorted. For all the data to be sorted, the number of times each data in the data to be sorted appears can be counted first, and the number of times each data appears is used as the initial score of the data, recorded as score. Take the data to be sorted {1, 1, 3, 3} as an example, where: the number of times data 0 appears is 0, and its score is 0; the number of times data 1 appears is 2, and its score is 2; the number of times data 1 appears is 0, and its score is 0; the number of times data 3 appears is 2, and its score is 2, and then a fractional sequence is generated according to the initial score.

[0050] In an optional embodiment of the present application, step 203 includes: Arrange the data in order of size, arrange the initial scores of the data according to the arrangement order of the data, and generate a score sequence corresponding to the initial scores.

[0051] Arrange the data in order of size, and arrange the initial scores corresponding to the data in order according to the arrangement order of the data, so as to generate a score sequence corresponding to the initial scores. Taking the data to be sorted {1, 1, 3, 3} as an example, the data to be sorted can be stored in the RAM resources on the FPGA chip, such as Figure 3a As shown in the figure, in the data to be sorted {1, 1, 3, 3}, two data 1s are stored in address addr1, and two data 3s are stored in address addr3. The number of occurrences of data 0 is 0, and its score is 0; the number of occurrences of data 1 is 2, and its score is 2; the number of occurrences of data 1 is 0, and its score is 0; the number of occurrences of data 3 is 2, and its score is 2. The corresponding fraction sequence is {0, 2, 0, 2}. The fraction sequence is stored in the RAM resources on the FPGA chip, such as Figure 3b As shown, the score sequence of the data to be sorted {1, 1, 3, 3} is {0, 2, 0, 2}, the first score 0 in the score sequence is stored in address addr0, the second score 2 is stored in address addr1, the third score 0 is stored in address addr2, and the fourth score 2 is stored in address addr3.

[0052] Step 204, determining the storage value of each data according to the fractional sequence, and sorting the data to be sorted based on the storage value.

[0053] Perform cumulative deformation processing on the fractional series, calculate the storage value of each data in the data to be sorted, and sort the data to be sorted according to the size of the storage value.

[0054] In an optional embodiment of the present application, step 204 includes: Sub-step S11, sequentially calculating the sum of the first n items of each initial score in the score series as the storage value of the data corresponding to the initial score.

[0055] Accumulate each score in the score sequence in turn, and calculate the sum of the first n terms of each score as the storage value of the data corresponding to the score. Take the data to be sorted {1, 1, 3, 3} as an example, its score sequence is {0, 2, 0, 2}, accumulate each initial score, for the first score 0, the accumulation is 0, then the storage value of the data 0 corresponding to the first score 0 is 0; for the second score 2, the accumulation is 2, then the storage value of the data 1 corresponding to the second score 2 is 2; for the third score 0, the accumulation is 2, then the storage value of the data 2 corresponding to the third score is 2; for the fourth score 2, the accumulation is 4, then the storage value of the data 3 corresponding to the fourth score 2 is 4, and the new score sequence {0, 2, 2, 4} is obtained. Figure 3c As shown, the first fraction 0 in the fraction sequence is stored in address addr0, the second fraction 2 is stored in address addr1, the third fraction 2 is stored in address addr2, and the fourth fraction 4 is stored in address addr3.

[0056] Sub-step S12, read each data in the data to be sorted, and output the storage value corresponding to the data; each time the data appears, the storage value corresponding to the data is reduced by one.

[0057] Re-traverse the data to be sorted, read each data in the data to be sorted, and output the storage value corresponding to the data. Taking the data to be sorted {1, 1, 3, 3} as an example, the first data read is the first data 1, output the storage value 2 corresponding to data 1, and subtract 1 from the storage value 2 corresponding to data 1 to get 1, such as Figure 3d As shown, the storage value in address addr1 becomes 1; continue to read the data to be sorted, the second data read is the second data 1, output the storage value 1 corresponding to data 1, and subtract 1 from the storage value 1 corresponding to data 1 to get 0, as shown Figure 3e As shown, the storage value in address addr1 becomes 0; continue to read the data to be sorted, the third data read is the third data 3, output the storage value 4 corresponding to data 3, and subtract 1 from the storage value 4 corresponding to data 3 to get 3, as shown Figure 3f As shown, the storage value in address addr3 becomes 3; continue to read the data to be sorted, the fourth data read is the fourth data 3, output the storage value 3 corresponding to data 3, and subtract 1 from the storage value 3 corresponding to data 3 to get 2, as shown Figure 3g As shown, the storage value in address addr3 becomes 2.

[0058] Sub-step S13, after the reading of the data to be sorted is completed, the final storage value of the data to be sorted is obtained.

[0059] After all the data to be sorted are read, the final storage value of the data to be sorted can be obtained. For example, the data to be sorted {1, 1, 3, 3} is taken as an example. After all the data to be sorted are read, the final storage value is {2, 1, 4, 3}, where the final storage value of the first data 1 is 2; the final storage value of the second data 1 is 1; the final storage value of the third data 3 is 4; and the final storage value of the fourth data 3 is 3. By default, the final storage value of the data at the same position is higher.

[0060] Sub-step S14, sorting the data to be sorted according to the final stored value.

[0061] Take the data to be sorted {1, 1, 3, 3} as an example. After all the data to be sorted are read, the final storage value is {2, 1, 4, 3}, where the final storage value of the first data 1 is 2; the final storage value of the second data 1 is 1; the final storage value of the third data 3 is 4; the final storage value of the fourth data 3 is 3. The data to be sorted are sorted according to the size of the final storage value, and the sorted data {3, 3, 1, 1} is obtained.

[0062] Step 205, after each single sorting is completed, for the first output, a preset number of sorted ordered data ranked in the front or back column is output, wherein the preset number does not exceed the limit of the data output by the FPGA chip each time; for non-first output, in addition to the ordered data output last time, a preset number of sorted ordered data ranked in the front or back column is output.

[0063] After each single sorting is completed, the ordered data that does not exceed the limit of the data output by the FPGA chip each time can be output. In order to output all data faster, the preset number can be the same as the limit of the data output by the FPGA chip each time. The order of output can be in the order of ranking from large to small according to the score ranking or in the order of ranking from small to large according to the score ranking. In the case of the first output, that is, the data to be sorted is sorted for the first time. If the output is in the order of ranking from large to small according to the score ranking, the preset number of sorted ordered data ranked in the front column can be output; if the output is in the order of ranking from large to small according to the score ranking, the preset number of sorted ordered data ranked in the back column can be output. In one example, if 130,000 data to be sorted are sorted from large to small, due to the on-chip resource limitation of the FPGA chip, the limit of the data output by the FPGA chip each time is 32,768 data. According to the number of data to be sorted and the limit of the data output by the FPGA chip each time, it can be determined that the preset number of sorting times is 4 times, and the data are output in order from large to small according to the score ranking. During the first sorting, all the data to be sorted (130,000 data to be sorted) are sorted for the first time, and the output ranking range is 130,000 ~ 97,233 data.

[0064] In the case of non-first output, that is, the data to be sorted is sorted twice or more, then in addition to the sorted data output last time, a preset number of sorted ordered data ranked in the front or back column can be output. In one example, if 130,000 data to be sorted are sorted from large to small, due to the on-chip resource limitation of the FPGA chip, the limit of the FPGA chip to output data each time is 32,768 data, and the data are output in order of the score ranking from large to small. In the first sorting, all the data to be sorted (130,000 data to be sorted) are sorted for the first time, and the output ranking range is 130,000~97,233; in the second sorting, all the data to be sorted (130,000 data to be sorted) are sorted for the second time, and the data ranking range is 97,232~64,465 except the first output data; in the third sorting, all the data to be sorted (130,000 data to be sorted) are sorted for the third time, and the data ranking range is 64,464~31,697 except the first two output data; in the fourth sorting, all the data to be sorted (130,000 data to be sorted) are sorted for the fourth time, and the data ranking range is 31,696~1 except the first three output data.

[0065] Step 206, determine whether all data are output, if yes, go to step 207; if not, return to step 204.

[0066] Step 207: sorting is completed and the final sorting result is obtained.

[0067] If all the data are output, the sorting is completed and the final sorting result is obtained. If there is still data that has not been output, return to step 204 to re-sort the data.

[0068] The embodiment of the present application provides a method for sorting data in an FPGA chip. By combining a counting sorting algorithm with an extended DDR memory, the problem of insufficient cache resources on the FPGA chip is solved, and the sorting of a large amount of data is split into a processing flow of multiple single sortings, thereby realizing fast sorting of a large amount of data in the FPGA chip. In addition, a counting sorting algorithm is adopted, and the data sorting logic is simple, with the characteristics of stable sorting, low time complexity, low space complexity, etc. There is no need to frequently compare and exchange the data to be sorted, and the sorting takes less time.

[0069] Corresponding to the aforementioned application function implementation method embodiment, the present application also provides an FPGA chip, an electronic device and corresponding embodiments.

[0070] Figure 4 It is a schematic diagram of the structure of the FPGA chip shown in the embodiment of the present application.

[0071] In the embodiment of the present application, the FPGA chip is communicatively connected to the memory to enable data exchange.

[0072] See also Figure 4 , the chip includes: The writing module 410 is used to obtain the data to be sorted and write the data to be sorted into the memory; The FPGA chip obtains the data to be sorted through the bus, and initiates a write request signal to the memory after receiving the data to be sorted, thereby caching the data to be sorted in the memory.

[0073] A reading module 420 is used to read the data to be sorted in the memory; The FPGA chip reads the data to be sorted in the memory for initialization.

[0074] A sorting module 430, used to sort the data to be sorted once according to a preset sorting number; FPGA chips can use counting sorting to sort all the data to be sorted in the order of data value. Due to the limited on-chip resources of FPGA, when the amount of data to be sorted is large, it is not possible to output all the data to be sorted at the same time after sorting. Therefore, the data to be sorted can be sorted separately according to the preset sorting times.

[0075] The output module 440 is used to output the sorted ordered data in a specified range each time after each single sort is completed.

[0076] After the data to be sorted is sorted once each time, the sorted ordered data in the specified range can be output each time.

[0077] The sorting module 430 includes: The statistical submodule is used to count the number of times each data in the data to be sorted appears for each single sort, obtain the initial score of each data, and generate a score series based on the initial score.

[0078] The sorting submodule is used to determine the storage value of each data according to the fractional sequence, and sort the data to be sorted based on the storage value.

[0079] The chip also includes: A limit value determination module, used to determine the limit value of the output data of the FPGA chip each time; A sorting times module, used to determine the preset sorting times according to the amount of the data to be sorted and the limit of the data output by the FPGA chip each time; The output module is also used for: after each single sorting is completed, for the first output, outputting a preset number of sorted ordered data ranked in the front or back column, wherein the preset number does not exceed the limit of the data output by the FPGA chip each time; for non-first output, in addition to the ordered data output last time, outputting a preset number of sorted ordered data ranked in the front or back column.

[0080] Among them, the sorting submodule is also used to calculate the sum of the first n items of each score in the score series in turn as the storage value of the data corresponding to the score; read each data in the data to be sorted, and output the storage value corresponding to the data; each time the data appears, the storage value corresponding to the data is reduced by one; after the reading of the data to be sorted is completed, the final storage value of the data to be sorted is obtained, and the data to be sorted is sorted according to the final storage value.

[0081] The statistical submodule is also used to arrange the data in order of size, and generate a score series corresponding to the initial score according to the arrangement order of the data.

[0082] Figure 5 This is another structural diagram of the FPGA chip shown in the embodiment of the present application. The FPGA chip is divided into two parts: PL (Programmable Logic) and PS (Processing System). PL is connected to the HP (High-Performance) interface in PS. PL includes a sorting circuit, a read-write control circuit, a VDMA (Video Direct Memory Access), and an AXI-SmartConnect master-slave interconnection module. The FPGA chip is connected to the memory for communication.

[0083] The embodiment of the present application provides an FPGA chip, which is communicatively connected to an extended memory. By combining a counting sorting algorithm with the memory, the problem of insufficient cache resources on the FPGA chip is solved, and a large amount of data can be quickly sorted in the FPGA chip. In addition, a counting sorting algorithm is adopted, and the data sorting logic is simple, with stable sorting, low time complexity, low space complexity and other characteristics. There is no need to frequently compare and exchange the data to be sorted, and the sorting takes less time.

[0084] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated again here.

[0085] Figure 6 It is a schematic diagram of the structure of an electronic device shown in an embodiment of the present application.

[0086] See also Figure 6, the electronic device 600 includes a memory 610 and a processor 620 .

[0087] The processor 620 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0088] The memory 610 may include various types of storage units, such as system memory, read-only memory (ROM), and permanent storage devices. Among them, ROM can store static data or instructions required by the processor 620 or other modules of the computer. The permanent storage device may be a readable and writable storage device. The permanent storage device may be a non-volatile storage device that does not lose the stored instructions and data even after the computer is powered off. In some embodiments, the permanent storage device uses a large-capacity storage device (such as a magnetic or optical disk, flash memory) as a permanent storage device. In some other embodiments, the permanent storage device may be a removable storage device (such as a floppy disk, optical drive). The system memory may be a readable and writable storage device or a volatile readable and writable storage device, such as a dynamic random access memory. The system memory may store some or all instructions and data required by the processor at runtime. In addition, the memory 610 may include any combination of computer-readable storage media, including various types of semiconductor storage chips (such as DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), and disks and / or optical disks may also be used. In some embodiments, the memory 610 may include a readable and / or writable removable storage device, such as a laser disc (CD), a read-only digital versatile disc (such as a DVD-ROM, a double-layer DVD-ROM), a read-only Blu-ray disc, an ultra-density optical disc, a flash memory card (such as an SD card, a mini SD card, a Micro-SD card, etc.), a magnetic floppy disk, etc. Computer-readable storage media do not include carrier waves and transient electronic signals transmitted wirelessly or wired.

[0089] The memory 610 stores executable codes, and when the executable codes are processed by the processor 620 , the processor 620 can execute part or all of the above-mentioned methods.

[0090] In addition, the method according to the present application may also be implemented as a computer program or a computer program product, which includes computer program code instructions for executing some or all of the steps in the above method of the present application.

[0091] Alternatively, the present application can also be implemented as a computer-readable storage medium (or non-transitory machine-readable storage medium or machine-readable storage medium) on which executable code (or computer program or computer instruction code) is stored. When the executable code (or computer program or computer instruction code) is executed by a processor of an electronic device (or server, etc.), the processor executes part or all of the steps of the above-mentioned method according to the present application.

[0092] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for sorting data in an FPGA chip, characterized in that: The FPGA chip is communicatively connected with the extended memory, and the method comprises: Acquire data to be sorted, and write the data to be sorted into the memory; Reading the data to be sorted in the memory; Sorting the data to be sorted once according to a preset number of sorting times; After each single sort is completed, the sorted and ordered data in the specified range is output each time.

2. The method according to claim 1, characterized in that The step of performing a single sorting of the data to be sorted according to a preset number of sorting times comprises: For each single sorting, count the number of occurrences of each data in the data to be sorted, obtain the initial score of each data, and generate a score sequence according to the initial score; The storage value of each of the data is determined according to the fractional sequence, and the data to be sorted is sorted based on the storage value.

3. The method according to claim 2, characterized in that Determining the storage value of each of the data according to the fractional sequence, and sorting the data to be sorted based on the storage value comprises: Calculate the sum of the first n items of each initial score in the score sequence in sequence as the storage value of the data corresponding to the initial score; Read each of the data to be sorted, and output the storage value corresponding to the data; each time the data appears, the storage value corresponding to the data is reduced by one; After the reading of the data to be sorted is completed, the final stored value of the data to be sorted is obtained; The data to be sorted is sorted according to the final stored value.

4. The method according to claim 2, characterized in that Generating a score sequence according to the initial score comprises: Arrange the data in order of size, arrange the initial scores of the data according to the arrangement order of the data, and generate a score sequence corresponding to the initial scores.

5. The method according to claim 1, characterized in that The preset number of sorting times is determined in the following manner: Determine the limit value of each output data of the FPGA chip; Determine the preset number of sorting times according to the amount of the data to be sorted and the limit of the data output by the FPGA chip each time; After each single sorting is completed, outputting the sorted ordered data in the specified range each time includes: After each single sort is completed, For the first output, output a preset number of sorted and ordered data ranked in the front or back columns, wherein the preset number does not exceed the limit of the FPGA chip outputting data each time; For non-first output, in addition to the ordered data output last time, a preset number of sorted ordered data ranked in the front or back column are output.

6. The method according to claim 1, characterized in that The memory includes a dynamic random access memory DDR.

7. An FPGA chip, characterized in that: The FPGA chip is communicatively connected with the extended memory, and the chip includes: A writing module, used for acquiring the data to be sorted, and writing the data to be sorted into the memory; A reading module, used for reading the data to be sorted in the memory; A sorting module, used to sort the data to be sorted once according to a preset sorting number; The output module is used to output the sorted ordered data in a specified range each time after each single sort is completed.

8. The chip according to claim 7, characterized in that: The sorting module comprises: A statistical submodule is used to count the number of occurrences of each data in the data to be sorted for each single sort, obtain an initial score for each data, and generate a score series according to the initial score; The sorting submodule is used to determine the storage value of each of the data according to the fractional sequence, and sort the data to be sorted based on the storage value.

9. The chip according to claim 8, characterized in that: The chip further comprises: A limit value determination module, used to determine the limit value of the output data of the FPGA chip each time; A sorting times module, used to determine the preset sorting times according to the amount of the data to be sorted and the limit of the data output by the FPGA chip each time; The output module is also used to output a preset number of sorted ordered data ranked in the front or back column for the first output after each single sorting is completed, wherein the preset number does not exceed the limit of the data output by the FPGA chip each time; for non-first output, in addition to the ordered data output last time, output a preset number of sorted ordered data ranked in the front or back column.

10. An electronic device, characterized in that: include: processor; as well as A memory having executable codes stored thereon, which, when executed by the processor, causes the processor to execute the method according to any one of claims 1 to 6.

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