Data processing method and system for arithmetic unit, arithmetic unit, terminal equipment and medium
By setting two sets of register groups in the operator and managing data writing according to the priority and operation status of the interrupt function, the problem of missing operation results when calling interrupt function with different priority levels is solved, and the operation results of each interrupt function are retained.
Patent Information
- Application Number
- CN202411457800.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-03-25
AI Technical Summary
The problem of missing the operation result due to the call of interrupt functions of different priority levels.
By setting at least two sets of register groups in the operator, the data to be written is written into the first register group according to the data type of data to be written in the data writing instruction of the first interrupt function and/or the current operation execution status of the operator, ensuring that the data of the high-priority interrupt function is not overwritten by the low-priority interrupt function.
It is realized that when two interrupt function calls with different priority levels, the respective operation results can be retained, avoiding the situation where the operation results are overwritten.
Smart Images
Figure CN119690520A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data processing, and in particular to a data processing method, system, electronic device and medium of an operator. Background Art
[0002] Arithmetic units are used in various fields of modern electronic equipment such as communications, automobiles, and medical treatment. Arithmetic units include dividers, multipliers, trigonometric function units, etc. Arithmetic units are usually used to implement operations in hardware, but software may call the arithmetic unit in different interrupt functions. If a higher priority interrupt occurs and the arithmetic unit is called in the interrupt function for operation before the previous operation is completed, the result of the previous operation may be overwritten by the result of the operation in the higher priority interrupt function, and the operation result is lost.
[0003] Therefore, it is urgent to solve the above problems. Summary of the invention
[0004] Purpose of the invention: The first purpose of the present invention is to provide a method for processing data of an operator, aiming to solve the problem of loss of operation results caused by calls to the operator by interrupt functions of different priorities.
[0005] A second object of the present invention is to provide an operation processing system.
[0006] The third object of the present invention is to provide an operator.
[0007] A fourth object of the present invention is to provide a terminal device.
[0008] A fifth object of the present invention is to provide a computer storage medium.
[0009] To achieve the above objectives, the present invention discloses a method for processing data in an operator, wherein the operator includes at least two groups of registers, and the method includes:
[0010] A data write instruction of a first interrupt function sent by a receiving processor;
[0011] When data corresponding to the second interrupt function is written to the second register group of the at least two register groups, the data to be written is written into the first register group of the at least two register groups according to the data type of the data to be written in the data writing instruction of the first interrupt function and / or the current operation execution state of the operator; wherein,
[0012] The priority of the first interrupt function is higher than that of the second interrupt function, and data corresponding to the second interrupt function is not written into the first register group.
[0013] Optionally, each of the register groups includes at least one operand register, one operand register and one result register; and writing the data to be written into the first register group of the at least two register groups includes:
[0014] When the data type is an operand, the data to be written is written into an operand register in the first register group.
[0015] Optionally, writing the to-be-written data into a first register group of the at least two register groups further includes:
[0016] When the data type is an operand and the operation execution status is not executed, the data to be written is written into the operand register in the first register group.
[0017] Optionally, writing the to-be-written data into a first register group of the at least two register groups further includes:
[0018] When the data type is an operand and the operation execution state is execution, issuing a blocking instruction to the processor;
[0019] After the operation is completed, the operation result is saved in the result register in the second register group;
[0020] An unblocking instruction is issued to the processor, and the data to be written is written into an operand register in the first register group.
[0021] Optionally, the method further includes:
[0022] Execute data operation of the first interrupt function, and write the operation result into the result register in the first register group.
[0023] Optionally, writing the data to be written into a first register group of the at least two register groups includes:
[0024] The data to be written is written into a group of the register groups specified by the data writing instruction, wherein the data writing instruction includes input port information of the specified register group.
[0025] Based on the same inventive concept, the present invention discloses a method for processing data of an operator, the method comprising:
[0026] Obtain an interrupt instruction, and when the priority of a first interrupt function called by the interrupt instruction is higher than that of a second interrupt function currently called, jump out of the second interrupt function;
[0027] A data write instruction of a first interrupt function is sent to an operator so that when a second register group of the at least two register groups of the operator has data written thereto corresponding to the second interrupt function, the data to be written is written into a first register group of the at least two register groups according to the data type of the data to be written in the data write instruction of the first interrupt function and / or the current operation execution state of the operator, and the data corresponding to the second interrupt function is not written into the first register group.
[0028] Optionally, sending a data write instruction of the first interrupt function to the operator includes:
[0029] An operand write instruction is sent to the operator, so that the operator writes the operand into the operand register in the first register group.
[0030] Optionally, sending the data writing instruction of the first interrupt function to the operator further includes:
[0031] An operand write instruction is sent to the operator, so that the operator writes the operand into the operand register in the first register group when the operation execution status of the operator is not executed.
[0032] Optionally, sending the data writing instruction of the first interrupt function to the operator further includes:
[0033] Sending an operand write instruction to the operator, and accepting a blocking instruction issued by the operator when the operation execution state of the operator is execution;
[0034] After the operation is completed, the operator saves the operation result in the second register group, and then receives an unblocking instruction issued by the operator, so that the operator writes the operand into the operand register in the first register group.
[0035] Optionally, the method further includes:
[0036] Exit from the first interrupt function and continue to execute the second interrupt function.
[0037] Optionally, the data write instruction includes input port information of a specified set of the register groups.
[0038] Based on the same inventive concept, the present invention discloses an operation processing system, the system includes a processor and an operator, the operator includes at least two groups of register groups;
[0039] The processor obtains an interrupt instruction, and when the priority of a first interrupt function called by the interrupt instruction is higher than that of a second interrupt function currently called, jumps out of the second interrupt function;
[0040] The processor sends a data write instruction of the first interrupt function to the operator;
[0041] When data corresponding to a second interrupt function is written into a second register group of the at least two register groups in the operator, the operator writes the data to be written into a first register group of the at least two register groups according to the data type of the data to be written in a data write instruction of the first interrupt function and / or the current operation execution state of the operator; wherein the data corresponding to the second interrupt function is not written into the first register group.
[0042] Based on the same inventive concept, the present invention discloses an operator, which includes at least two groups of registers and executes the steps of the operator data processing method as described above.
[0043] Each of the register groups at least includes an operand register, an operand register and a result register, and each of the register groups corresponds to a group of input ports and output ports.
[0044] Based on the same inventive concept, the present invention discloses a terminal device, which includes a memory, a processor, and an operator calling program stored in the memory and executable on the processor, and the operator calling program implements the steps of the operator data processing method described above when executed by the processor.
[0045] Based on the same inventive concept, the present invention discloses a computer-readable storage medium, on which is stored an operator calling program, which implements the steps of the operator data processing method described above when executed by a processor.
[0046] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: when two interrupt functions of different priorities call the operator, the operation results in the two interrupt functions can be retained and the operation results will not be overwritten. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] Figure 1 is a flow chart of a method for processing data of an arithmetic unit applied to an arithmetic unit in the present invention;
[0048] Figure 2 It is a structural schematic diagram of the operator in the present invention;
[0049] Figure 3 It is a flowchart of a method for processing data of an arithmetic unit applied to a processor in the present invention;
[0050] Figure 4A data processing flow chart of the present invention in which the first interrupt write operation number occurs before the second interrupt write operation number;
[0051] Figure 5 A data processing flow chart of the present invention in which the first interrupt write operation occurs after the second interrupt write operation;
[0052] Figure 6 This is a structural block diagram of an electronic device in the present invention;
[0053] Figure 7 A schematic diagram of a computer-readable storage medium in the present invention. DETAILED DESCRIPTION
[0054] The technical solution of the present invention is further described below in conjunction with the accompanying drawings.
[0055] In one embodiment, a data processing method of an operator is disclosed, wherein the operator includes at least two register groups, such as Figure 1 FIG. 1 is a flow chart of a data processing method of an operator, and the method comprises the following steps:
[0056] Step 110: Receive a data write instruction of a first interrupt function sent by a processor.
[0057] In this embodiment, the operator may include a divider, a multiplier, a trigonometric operator, etc. The operator includes at least two register groups, each register group is used to write the data involved in the operation and the operation result of the same operation. The processor sends a data write instruction of the first interrupt function to the operator, and the operator receives the data write instruction, and the data write instruction includes the data involved in the operation in the first interrupt function. It should be noted that the interrupt function of the present invention can also refer to the main function, etc.
[0058] Step 120: When data corresponding to the second interrupt function is written to the second register group among the at least two register groups, the data to be written is written to the first register group among the at least two register groups according to the data type of the data to be written in the data write instruction of the first interrupt function and / or the current operation execution state of the operator.
[0059] The priority of the first interrupt function is higher than that of the second interrupt function, and data corresponding to the second interrupt function is not written into the first register group.
[0060] In this embodiment, before the processor sends the data write instruction of the first interrupt function, at least one group of registers in the operator has data corresponding to other interrupt functions written into it, wherein the second register group has data corresponding to the second interrupt function written into it, and the priority of the first interrupt function is higher than that of the second interrupt function. After the operator receives the data write instruction of the first interrupt function, the data to be written in the data write instruction is written into another group of first registers that have not data corresponding to the second interrupt function written into it. The operator will execute different steps of writing the data to be written into the first register group according to the data type of the data to be written and / or the current operation state of the operator. The data type may include operands and operands, etc. Whether the current operation state of the operator is executed or not is determined by whether the written data in the second register group or the register group with other function data written into it triggers the operation.
[0061] In this embodiment, by setting at least two groups of register groups in the operator, when the processor has interrupt functions that interrupt each other, the data of different interrupt functions can be written into different register groups respectively to avoid the data of the interrupt function written later overwriting the data of the interrupt function written earlier, thereby causing the loss of the calculation result of the interrupt function written earlier.
[0062] In one embodiment, each register group includes at least one operand register, one operand register and one result register. The step 120 of writing the data to be written into the first register group of at least two register groups includes the following steps: when the data type is operand, writing the data to be written into the operand register in the first register group.
[0063] The operand register and the operand register are used to write the data involved in the operation of the interrupt function, and the result register is used to save the corresponding operation execution result. Taking the divider as an example, the operand register of the divider is used to write the divisor, the operand register is used to write the dividend, and the result register is used to save the operation result quotient.
[0064] Generally, the processor calls the arithmetic unit through the AHB bus. When the AHB HREADY signal is high, the processor's read and write operations on the arithmetic unit registers will take effect immediately. If AHB HREADY is low, the processor will be blocked, and the processor's read and write operations on the arithmetic unit registers will wait until AHB HREADY is high before taking effect. After the operands and operands are written to a group of registers in the arithmetic unit, the arithmetic unit will be triggered to perform the operation, and the result of the operation will be saved in the result register of the register group.
[0065] When calling the operator to perform an operation, the operand must first be written to the operand register through the AHB bus, and then the operand must be written to the operand register; only when the operand is written will the operator start an operation. For example, a 32 / 32-bit operation requires 12 cycles to complete, during which reading the result register will pull down the AHB HREADY signal of the bus. Therefore, the processor's operation of reading the operation result does not take effect immediately, but waits for the operation calculation to be completed and AHB HREADY to become high before the processor's operation of reading the operation result is effective and the operation result can be read out. If the processor initiates the operation of writing the operand again during the operation of the operator, the AHB HREADY signal of the bus will be pulled low by the hardware, and the operator will complete the previous operation first. After the operator completes the previous operation, the AHB HREADY signal of the bus will be pulled high by the hardware, and the operand written by the processor during the operation will be stored in the operand register.
[0066] In this embodiment, the data type of the data to be written is an operand. Since writing the operand will not trigger the execution of the operation, the data to be written can be directly written into the operand register in the first register group without considering the current operation execution state of the operator.
[0067] In one embodiment, step 120 of writing the data to be written into the first register group of at least two register groups further includes the following steps: when the data type is operand and the operation execution status is not executed, writing the data to be written into the operand register in the first register group.
[0068] In this embodiment, the data type of the data to be written is an operand, and the operation execution state of the operator must be determined at this time. When the operation execution state is determined to be unexecuted, the operator receiving the write instruction of the operand again will not cause the AHB HREADY signal of the bus to be pulled low. Therefore, the data to be written can be directly written into the operand register in the first register group. In one embodiment, after step 120, the following steps are also included: the operator executes the data operation of the first interrupt function, and writes the operation result into the result register in the first register group.
[0069] In this embodiment, after the operator saves the operation result of the first interrupt function, it will continue to receive the operand write instruction of the second interrupt function sent by the processor, write the operand of the second interrupt function into the operand register of the second register group according to the operand write instruction, and perform the operation of the second interrupt function, and save its operation result into the result register of the second register.
[0070] In one embodiment, step 120 of writing the data to be written into the first register group of at least two register groups also includes the following steps: when the data type is an operand and the operation execution status is execution, issuing a blocking instruction to the processor; after the operation is executed, saving the operation result to the result register in the second register group; issuing an unblocking instruction to the processor, and writing the data to be written into the operand register in the first register group.
[0071] In this embodiment, the data type of the data to be written is an operand. At this time, the operation execution state of the operator must also be determined. When it is determined that the operation execution state is execution, that is, the operation of the second interrupt function is executed, the operator sends a blocking instruction to the processor, that is, the AHB HREADY signal of the bus is pulled down, resulting in the read and write instructions received by the operator being unable to take effect. At this time, the operator first executes the operation of the second interrupt function, and after the operation of the second interrupt function is completed, the operation result is saved in the result register in the second register group. The operator then sends an unblocking instruction to the processor, that is, the AHB HREADY signal of the bus is pulled high, and the read and write instructions received by the operator take effect, and the data to be written is written into the operand register in the first register group. In one embodiment, after step 120, the following steps are also included: the operator executes the data operation of the first interrupt function, and writes the operation result into the result register in the first register group.
[0072] In one embodiment, step 120 of writing the data to be written into the first register group of at least two register groups also includes the following steps: writing the data to be written into a group of register groups specified by a data write instruction, wherein the data write instruction includes input port information of the specified register group.
[0073] In this embodiment, the processor specifies which register group of the arithmetic unit the data of the interrupt function or main function of different priority levels is written into. Different register groups write information through their respective input ports and read information through output ports. The data write instruction carries the input port information of the specified register group. In other embodiments, priority information can also be added to the data write instruction. The arithmetic unit receives the data write instruction and automatically allocates the corresponding register group according to the priority information of the data.
[0074] In one embodiment, an operator is disclosed. The operator includes at least two groups of registers. The operator executes the steps of the operator data processing method as described above.
[0075] In one embodiment, each register group includes at least one operand register, one operand register and one result register, and each register group corresponds to a group of input ports and output ports.
[0076] like Figure 2 As shown, it is a schematic diagram of the structure of an operator, the operator includes two groups of input interfaces and two groups of output interfaces, namely the input interface and output interface of the first register group and the second register group, the first register group includes the operand register DSP0_DID, the operand register DSP0_DIS and the result register DSP0_QUO, and the second register group includes the operand register DSP0_DID1, the operand register DSP0_DIS1 and the result register DSP0_QUO1. If it is specified on the processor that the interrupt with high priority uses the first register group and the interrupt with low priority uses the second register group. Then the first interrupt function calls the operator to write the operand into the operand register DSP0_DID and the operand into the operand register DSP0_DIS, and the obtained operation result is stored in the result register DSP0_QUO, and the second interrupt function calls the operator to write the operand into the operand register DSP0_DID1 and the operand into the operand register DSP0_DIS1, and the obtained operation result is stored in the result register DSP0_QUO1. In this way, when two interrupt functions of different priorities call the operator, the operation results in the two interrupt functions can be retained and will not be overwritten. And because the high-priority interrupt function can interrupt the low-priority interrupt function, the operation in the high-priority interrupt can interrupt the operation of the low-priority interrupt.
[0077] In order not to increase the chip cost too much, only the hardware design of the arithmetic unit in the chip is modified, and no additional arithmetic unit module is added. In this embodiment, only one set of input interfaces DSP0_DID1, DSP0_DIS1 and one set of output interfaces DSP0_QUO1 are added. The above design can ensure that the calculation result will not be overwritten when two interrupt functions of different priorities or an interrupt function and the main function both call the arithmetic unit, and does not increase the chip cost too much. If you want to support the calling of multiple interrupt functions, you only need to expand the input and output interfaces of the arithmetic unit, that is, the register group.
[0078] The present invention also discloses a method for processing data of an operator, which is applied to a processor, such as Figure 3 FIG. 1 is a flow chart of a data processing method of an operator, and the method comprises the following steps:
[0079] Step 210: Obtain an interrupt instruction, and when the priority of the first interrupt function called by the interrupt instruction is higher than the second interrupt function currently called, jump out of the second interrupt function.
[0080] In this embodiment, the processor obtains an interrupt instruction, and determines the priority levels of the first interrupt function called by the obtained interrupt instruction and the second interrupt function currently called. When it is determined that the priority of the first interrupt function is higher than the priority of the second interrupt function, the processor jumps out of the second interrupt function and starts to call the first interrupt function. When it is determined that the priority of the first interrupt function is lower than the priority of the second interrupt function, the processor continues to call the current second interrupt function.
[0081] Step 220: Send a data write instruction of the first interrupt function to the operator, so that when a second register group among at least two register groups of the operator has data written corresponding to the second interrupt function, the data to be written is written into the first register group among the at least two register groups according to the data type of the data to be written in the data write instruction of the first interrupt function and / or the current operation execution state of the operator, and the data corresponding to the second interrupt function is not written into the first register group.
[0082] The processor sends a data write instruction of the first interrupt function to the operator, and the operator receives the data write instruction, wherein the data write instruction includes data involved in the operation in the first interrupt function. Before the processor sends the data write instruction of the first interrupt function, at least one group of registers in the operator has written data corresponding to other interrupt functions, wherein the second register group has written data corresponding to the second interrupt function, and the priority of the first interrupt function is higher than that of the second interrupt function. After the operator receives the data write instruction of the first interrupt function, the data to be written in the data write instruction is written into another group of first registers that have not been written with data corresponding to the second interrupt function. The operator will perform different steps of writing the data to be written into the first register group according to the data type of the data to be written and / or the current operation state of the operator. The data type may include operands and operands, etc. Whether the current operation state of the operator is executed or not is determined by whether the written data in the second register group or the register group with other function data written triggers the operation.
[0083] In this embodiment, by setting at least two groups of register groups in the operator, when the processor has interrupt functions that interrupt each other, the data of different interrupt functions can be written into different register groups of the operator respectively to avoid the data of the interrupt function written later overwriting the data of the interrupt function written earlier, thereby causing the loss of the calculation result of the interrupt function written earlier.
[0084] In one embodiment, the data write instruction includes input port information of a specified group of register groups.
[0085] In this embodiment, the processor specifies which register group of the arithmetic unit the data of the interrupt function or main function of different priority levels is written into. Different register groups write information through their respective input ports and read information through output ports. The data write instruction carries the input port information of the specified register group. In other embodiments, priority information can also be added to the data write instruction. The arithmetic unit receives the data write instruction and automatically allocates the corresponding register group according to the priority information of the data.
[0086] In one embodiment, step 220 may include: sending an operand write instruction to the operator, so that the operator writes the operand into an operand register in the first register group.
[0087] The processor sends an operand write instruction to the operator, and after receiving the operand write instruction, the operator writes the operand into the operand register in the first register group.
[0088] In one embodiment, step 220 may include: sending an operand write instruction to the operator, so that the operator writes the operand into the operand register in the first register group when the operation execution state of the operator is not executed.
[0089] The processor sends an operand write instruction to the operator. After receiving the operand write instruction, the operator determines the operation execution state of the operator. When it is determined that the operation execution state is not executed, the operand is written into the operand register in the first register group. After that, the operator executes the data operation of the first interrupt function and writes the operation result into the result register in the first register group.
[0090] In one embodiment, step 220 may include: sending an operand write instruction to the operator, and when the operation execution state of the operator is execution, accepting a blocking instruction issued by the operator; and after the operation is completed, the operator saves the operation result to the second register group, and then receives an unblocking instruction issued by the operator, so that the operator writes the operand to the operand register in the first register group.
[0091] The processor sends an operand write instruction to the operator. After receiving the operand write instruction, the operator determines the operation execution state of the operator. When it is determined that the operation execution state is execution, the processor receives a blocking instruction issued by the operator, that is, pulls down the AHB HREADY signal of the bus, causing the read and write instructions issued by the processor to be ineffective. At this time, the operator first executes the operation of the second interrupt function, and after the operation of the second interrupt function is completed, the operation result is saved in the result register in the second register group. The operator then sends an unblocking instruction to the processor, that is, pulls up the AHB HREADY signal of the bus, and the read and write instructions issued by the processor take effect, and write the data to be written into the operand register in the first register group. After that, the operator executes the data operation of the first interrupt function and writes the operation result into the result register in the first register group.
[0092] In one embodiment, step 220 further includes the following steps: exiting from the first interrupt function and continuing to execute the second interrupt function.
[0093] After the operation result of the first interrupt function is executed, the processor can read the operation result from the operator. The processor jumps out of the first interrupt function, and continues to execute the second interrupt function and continue to write the data of the second interrupt function to the operator.
[0094] The present invention also discloses an operation processing system, which includes a processor and an operator, and the operator includes at least two groups of register groups; the processor obtains an interrupt instruction, and when the priority of the first interrupt function called by the interrupt instruction is higher than the second interrupt function currently called, jumps out of the second interrupt function; the processor sends a data write instruction of the first interrupt function to the operator; when the second register group of at least two register groups in the operator has data corresponding to the second interrupt function written, the operator writes the data to be written into the first register group of at least two register groups according to the data type of the data to be written in the data write instruction of the first interrupt function and / or the current operation execution state of the operator, and the data corresponding to the second interrupt function is not written in the first register group. The specific implementation steps of the operation processing system can refer to the above embodiment, which will not be repeated here. The processor and the operator can be set together in a terminal system, and the operator can also be independent of the terminal where the processor is located and called by the processor.
[0095] The following describes the implementation steps from the example of a high-priority first interrupt function performing an operation to interrupt a low-priority second interrupt function performing an operation. Figure 4As shown, Div0 Operate in the figure corresponds to the operation of the operator triggered by the first interrupt function, Div1 Operate corresponds to the operation of the operator triggered by the second interrupt function, Interrupt0 refers to the first interrupt function, Interrupt1 refers to the second interrupt function, and the operator is called in both the high-priority first interrupt function and the low-priority second interrupt function.
[0096] When the second interrupt function occurs first, after the operand in the second interrupt function is written into the operand register DSP0_DID1, but the operand has not yet been written into the operand register DSP0_DIS1, the first interrupt function occurs, such as Figure 4 As shown, the data processing method includes the following steps:
[0097] When the second interrupt flag of the second interrupt function is generated, the processor enters the second interrupt function, writes the operand into the operand register DSP0_DID1 of the second register group, and then the first interrupt flag of the first interrupt function is generated before writing the operand DSP0_DIS1;
[0098] When the first interrupt flag is generated and the priority of the first interrupt flag is higher than the second interrupt flag, the processor jumps out of the second interrupt function corresponding to the second interrupt and enters the first interrupt function corresponding to the first interrupt. The processor first writes the operand into the operand register DSP0_DID of the first register group, and then writes the operand into the operand register DSP0_DIS of the first register group, triggering the operator to perform the operation of the first interrupt function, and after the operation is completed, the operator saves the result of the operation in the first interrupt function to the result register DSP0_QUO of the first register group. The processor jumps out of the first interrupt function corresponding to the first interrupt and re-enters the second interrupt function corresponding to the second interrupt to perform the remaining unexecuted operations, that is, the processor writes the operand into the operand register DSP0_DIS1 of the second register group, triggering the operator to perform the operation of the second interrupt function, and after the operation is completed, the operator saves the result of the operation in the second interrupt function to the result register DSP0_QUO1 of the second register group.
[0099] When the second interrupt function occurs first, the operand and operand of the second interrupt function are successively written into the operand register DSP0_DID1 and the operand register DSP0_DIS1, and then the first interrupt function occurs, such as Figure 5 As shown, the data processing method includes the following steps:
[0100] When the second interrupt flag of the second interrupt function is generated, the processor enters the second interrupt function corresponding to the second interrupt, writes the operand into the operand register DSP0_DID1 of the second register group, and then writes the operand into the operand register DSP0_DIS1 of the second register group, triggering the operator to perform the operation of the second interrupt function, and then the first interrupt flag is generated;
[0101] When the first interrupt flag is generated and the priority of the first interrupt flag is higher than the second interrupt flag, the processor jumps out of the second interrupt function corresponding to the second interrupt and enters the first interrupt function corresponding to the first interrupt. The processor first initiates the operation of writing the operand into the operand register DSP0_DID of the first register group. However, since the operator is performing operation at this time, the write operation initiated by the processor will cause the hardware to pull down the AHB_HREADY signal, and the processor's operation of writing the operand will be blocked. After the operator completes the operation of the second interrupt and saves the operation result to the result register DSP0_QUO1 of the second register group, the hardware will pull up the AHB_HREADY signal. At this time, the write operation of the operand initiated by the processor is valid, and the processor can write the operand into the operand register DSP0_DIS of the first register group. After the operand is written, the operator is triggered to execute the operation of the first interrupt function. After waiting for the operation to be completed, the operator saves the operation result of the first interrupt function to the result register DSP0_QUO of the first register group.
[0102] When the high-priority first interrupt function is being executed, the second interrupt function of the low-priority second interrupt request occurs. At this time, the processor will first execute the high-priority first interrupt function and call the operator to perform the operation. When the operator is performing the operation, even if the second interrupt function of the low-priority second interrupt request occurs, it cannot interrupt the operator to perform the operation. Instead, the operator will be occupied to perform the operation of the second interrupt function after the operation of the first interrupt function is completed.
[0103] When the first interrupt function is executed first and the operand of the first interrupt function has not been written into the operator, when the second interrupt request occurs again, the steps of the specific operator data processing method are as follows:
[0104] When the first interrupt flag is generated, the processor enters the first interrupt function corresponding to the first interrupt, and writes the operand into the operand register of the first register group; when the second interrupt flag is generated and the priority of the second interrupt flag is lower than the first interrupt flag, the operand of the first interrupt function is written into the operand register of the first register group, triggering the operator to perform the operation of the first interrupt function, and after the operation is completed, the operator saves the operation result to the result register of the first register group. The processor jumps out of the first interrupt function corresponding to the first interrupt, enters the second interrupt function corresponding to the second interrupt, first writes the operand into the operand register of the second register group, and then writes the operand into the operand register of the second register group, triggering the operator to perform the operation of the second interrupt function, and after the operation is completed, the operator saves the operation result to the result register of the second register group.
[0105] The first interrupt function is executed first, and when the operand of the first interrupt function is written into the operator, when the second interrupt request occurs again, the steps of the specific operator data processing method are as follows:
[0106] When the first interrupt flag is generated, the first interrupt function corresponding to the first interrupt is entered, the operand is written into the operand register of the first register group, and then the operand is written into the operand register of the first register group, triggering the operator to perform the operation of the first interrupt function; when the second interrupt flag is generated and the priority of the second interrupt flag is lower than the first interrupt flag, after waiting for the operation of the first interrupt to be completed, the operator saves its operation result to the result register of the first register group. Jump out from the first interrupt function corresponding to the first interrupt, enter the second interrupt function corresponding to the second interrupt, first write the operand into the operand register of the second register group, and then write the operand into the operand register of the second register group, triggering the operator to perform the operation of the second interrupt function, and after the operation is completed, the operator saves the operation result to the result register of the second register group.
[0107] The present invention also discloses a terminal device, which includes a memory, a processor, and an operator calling program stored in the memory and executable on the processor. When the operator calling program is executed by the processor, the steps of the operator data processing method described above are implemented.
[0108] like Figure 6 As shown, the terminal device 10 may include: a processor 100, a memory 101, a bus 102 and a communication interface 103, and the processor 100, the communication interface 103 and the memory 101 are connected via the bus 102; the memory 101 stores an operator calling program that can be run on the processor 100, and when the processor 100 runs the computer program, it executes an operator data processing method provided by any of the aforementioned embodiments of the present invention.
[0109] The memory 101 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk storage. The communication connection between the device network element and at least one other network element is realized through at least one communication interface 103 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used.
[0110] The bus 102 may be an AHB bus, an ISA bus, a PCI bus, or an EISA bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. The memory 101 is used to store programs, and the processor 100 executes the program after receiving an execution instruction. The arithmetic unit data processing disclosed in any implementation of the above-mentioned embodiment of the present invention may be applied to the processor 100, or implemented by the processor 100.
[0111] The processor 100 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the hardware integrated logic circuit in the processor 100 or the instruction in the form of software. The above processor 100 may be a general-purpose processor, which may include a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present invention may be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 101, and the processor 100 reads the information in the memory 101 and completes the steps of the above method in combination with its hardware.
[0112] The electronic device provided by the embodiment of the present invention and the method provided by the embodiment of the present invention are based on the same inventive concept and have the same beneficial effects as the method adopted, operated or implemented by them.
[0113] The present invention also discloses a computer-readable storage medium, on which is stored a computing unit calling program, which implements the steps of the computing unit data processing method as described above when the computing unit calling program is executed by a processor.
[0114] like Figure 7 As shown, the computer-readable storage medium shown is a CD 20 on which a computer program (ie, a program product) is stored. When the computer program is run by a processor, the method provided by any of the aforementioned embodiments will be executed.
[0115] It should be noted that examples of computer-readable storage media may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.
[0116] The computer-readable storage medium provided by the above-mentioned embodiment of the present invention and the method provided by the embodiment of the present invention are based on the same inventive concept and have the same beneficial effects as the method adopted, run or implemented by the application program stored therein.
[0117] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.
Claims
1. A method for processing data of an operator, characterized in that: The operator includes at least two groups of registers, and the method includes: A data write instruction of a first interrupt function sent by a receiving processor; When data corresponding to the second interrupt function is written to the second register group of the at least two register groups, the data to be written is written into the first register group of the at least two register groups according to the data type of the data to be written in the data writing instruction of the first interrupt function and / or the current operation execution state of the operator; wherein, The priority of the first interrupt function is higher than that of the second interrupt function, and data corresponding to the second interrupt function is not written into the first register group.
2. The method according to claim 1, characterized in that Each of the register groups includes at least one operand register, one operand register and one result register; the step of writing the data to be written into the first register group of the at least two register groups includes: When the data type is an operand, the data to be written is written into an operand register in the first register group.
3. The method according to claim 2, characterized in that Writing the data to be written into the first register group of the at least two register groups further comprises: When the data type is an operand and the operation execution status is not executed, the data to be written is written into the operand register in the first register group.
4. The method according to claim 2, characterized in that Writing the data to be written into the first register group of the at least two register groups further comprises: When the data type is an operand and the operation execution state is execution, issuing a blocking instruction to the processor; After the operation is completed, the operation result is saved in the result register in the second register group; An unblocking instruction is issued to the processor, and the data to be written is written into an operand register in the first register group.
5. The method according to claim 3 or 4, characterized in that The method further comprises: Execute data operation of the first interrupt function, and write the operation result into the result register in the first register group.
6. The method according to claim 1, characterized in that Writing the data to be written into a first register group of the at least two register groups comprises: The data to be written is written into a group of the register groups specified by the data writing instruction, wherein the data writing instruction includes input port information of the specified register group.
7. A method for processing data of an operator, characterized in that: The method comprises: Obtain an interrupt instruction, and when the priority of a first interrupt function called by the interrupt instruction is higher than that of a second interrupt function currently called, jump out of the second interrupt function; A data write instruction of a first interrupt function is sent to an operator so that when a second register group of the at least two register groups of the operator has data written thereto corresponding to the second interrupt function, the data to be written is written into a first register group of the at least two register groups according to the data type of the data to be written in the data write instruction of the first interrupt function and / or the current operation execution state of the operator, and the data corresponding to the second interrupt function is not written into the first register group.
8. The method according to claim 7, characterized in that The sending of the data writing instruction of the first interrupt function to the operator comprises: An operand write instruction is sent to the operator, so that the operator writes the operand into the operand register in the first register group.
9. The method according to claim 8, characterized in that The sending of the data writing instruction of the first interrupt function to the operator also includes: An operand write instruction is sent to the operator, so that the operator writes the operand into the operand register in the first register group when the operation execution status of the operator is not executed.
10. The method according to claim 8, characterized in that The sending of the data writing instruction of the first interrupt function to the operator also includes: Sending an operand write instruction to the operator, and accepting a blocking instruction issued by the operator when the operation execution state of the operator is execution; After the operation is completed, the operator saves the operation result in the second register group, and then receives an unblocking instruction issued by the operator, so that the operator writes the operand into the operand register in the first register group.
11. The method according to claim 9 or 10, characterized in that The method further comprises: Exit from the first interrupt function and continue to execute the second interrupt function.
12. The method according to claim 7, characterized in that The data write instruction includes input port information of a specified set of the register groups.
13. A computing system, comprising a processor and an operator, characterized in that: The operator comprises at least two groups of registers; The processor obtains an interrupt instruction, and when the priority of a first interrupt function called by the interrupt instruction is higher than that of a second interrupt function currently called, jumps out of the second interrupt function; The processor sends a data write instruction of the first interrupt function to the operator; When data corresponding to a second interrupt function is written into a second register group of the at least two register groups in the operator, the operator writes the data to be written into a first register group of the at least two register groups according to the data type of the data to be written in a data write instruction of the first interrupt function and / or the current operation execution state of the operator; wherein the data corresponding to the second interrupt function is not written into the first register group.
14. An operator, comprising at least two groups of registers, and executing the steps of the operator data processing method according to any one of claims 1 to 6.
15. The computing unit according to claim 14, characterized in that: Each of the register groups at least includes an operand register, an operand register and a result register, and each of the register groups corresponds to a group of input ports and output ports.
16. A terminal device, comprising a memory, a processor, and an operator calling program stored in the memory and executable on the processor, wherein the operator calling program, when executed by the processor, implements the steps of the operator data processing method as described in any one of claims 7 to 12.
17. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores an operator calling program, and when the operator calling program is executed by the processor, the steps of the operator data processing method according to any one of claims 7 to 12 are implemented.