Memory pooling system and server system

Abstract

The invention discloses a memory pooling system and a server system, and relates to the technical field of servers, the memory pooling system comprises a computing node, a memory exchange node and a memory pool node; the computing node is interconnected with the memory exchange node through a first bus, and is interconnected with the memory exchange node through a network; the memory pool node is interconnected with the memory exchange node through a first bus, and is interconnected with the memory exchange node through a second bus; the memory exchange node comprises a data center security control module; and the memory exchange node manages the memory pooling system through the data center security control module. According to the memory pooling system, the hardware cost can be reduced, and the maintainability of the whole server system is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to a memory pooling system and a server system. Background Art

[0002] In order to cope with the increasing demand of AI (Artificial Intelligence) for memory, bandwidth, etc., the current server system usually provides a pooling system with a large enough memory capacity, which is called a memory pooling system. The memory pooling system includes computing nodes, memory pool nodes, and memory exchange nodes. In the related technology, each node is equipped with a corresponding management module to maintain the normal operation of the memory pooling system. However, equipping each node with a management module will result in high hardware costs, and each node needs to be maintained separately in the later stage, and the maintainability of the server system is not high. Therefore, how to solve the above technical defects has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0003] The object of the present invention is to provide a memory pooling system and a server system, which can reduce hardware costs and improve the maintainability of the server system.

[0004] In order to solve the above technical problems, the present invention provides a memory pooling system, comprising:

[0005] A computing node, a memory exchange node and a memory pool node; the computing node is interconnected with the memory exchange node through a first bus, and is interconnected with the memory exchange node through a network; the memory pool node is interconnected with the memory exchange node through a first bus, and is interconnected with the memory exchange node through a second bus; the memory exchange node includes a data center security control module; the memory exchange node manages a memory pooling system through the data center security control module.

[0006] In some embodiments, the computing node comprises:

[0007] A central processing unit, a first management controller, a first Ethernet physical layer device, and a first connector; the central processing unit is connected to the first connector; the first management controller is connected to the first Ethernet physical layer device, and the first Ethernet physical layer device is connected to the first connector; the computing node is connected to the memory switching node via the first connector.

[0008] In some embodiments, the computing node includes at least two central processing units.

[0009] In some embodiments, the central processing units are connected via a third bus.

[0010] In some embodiments, the central processors are connected via a hyperpath interconnect bus.

[0011] In some embodiments, the target central processor in the computing node is connected to the first management controller via a fourth bus.

[0012] In some embodiments, the target central processor in the computing node is connected to the first management controller via an enhanced serial peripheral interface bus.

[0013] In some embodiments, the first management controller is connected to the first Ethernet physical layer device via a Reduced Gigabit Media Independent Interface.

[0014] In some embodiments, the first Ethernet physical layer device is connected to the first connector via a medium dependent interface.

[0015] In some embodiments, the computing node is interconnected with the memory switch node via a high-speed interconnect bus, and the memory pool node is interconnected with the memory switch node via a high-speed interconnect bus.

[0016] In some embodiments, the memory pool node is interconnected with the memory switch node via an integrated circuit bus.

[0017] In some embodiments, the memory switch node includes:

[0018] The data center security control module, the first switching device, the second switching device, the second connector, the third connector, and the fourth connector; the first switching device is connected to the second connector, the third connector, and the fourth connector respectively, the second switching device is connected to the second connector and the fourth connector respectively, the data center security control module is connected to the fourth connector, and the third connector is connected to the fourth connector; the memory switching node is connected to the computing node through the second connector, and is connected to the memory pool node through the third connector.

[0019] In some embodiments, the memory switch node includes at least two first switch devices.

[0020] In some embodiments, the memory switch node further includes: a multiplexer; the multiplexer is connected to the first switch device and the fourth connector.

[0021] In some embodiments, the multiplexer is connected to the fourth connector via a universal asynchronous receiver-transmitter interface.

[0022] In some embodiments, the memory switch node further includes: a third switch device; the third switch device is connected to the first switch device and the fourth connector respectively.

[0023] In some embodiments, the second switching device is connected to the fourth connector via a serial Gigabit Media Independent Interface.

[0024] In some embodiments, the memory switch node further includes: a network connector; the network connector is connected to the second switch device.

[0025] In some embodiments, the data center security control module includes:

[0026] A second management controller, a memory, a second Ethernet physical layer device, and a gold finger; the second management controller is connected to the memory, the second Ethernet physical layer device, and the gold finger respectively; the second Ethernet physical layer device is connected to the gold finger.

[0027] In some embodiments, the memory includes a double data rate synchronous dynamic random access memory, an embedded multimedia memory, and a first flash memory.

[0028] In some embodiments, the memory pool node includes:

[0029] A memory controller, a memory, a fifth connector and a second flash memory; the memory controller is connected to the fifth connector, the second flash memory and the memory respectively; the memory pool node is connected to the memory switch node via the fifth connector.

[0030] In some embodiments, the memory includes: a dual in-line memory module.

[0031] In order to solve the above technical problem, the present invention also provides a server system, including the memory pooling system as described above.

[0032] The memory pooling system provided by the present invention includes: a computing node, a memory exchange node and a memory pool node; the computing node is interconnected with the memory exchange node through a first bus, and is interconnected with the memory exchange node through a network; the memory pool node is interconnected with the memory exchange node through a first bus, and is interconnected with the memory exchange node through a second bus; the memory exchange node includes a data center security control module; the memory exchange node manages the memory pooling system through the data center security control module. It can be seen that the memory pooling system provided by the present invention sets a data center security control module in the memory exchange node, and the memory exchange node manages the memory pooling system through the data center security control module. The management functions such as memory resource allocation can be realized through the data center security control module. The management controller in the memory pool node in the related scheme, the management controller in the memory exchange node and the memory resource manager are replaced by the data center security control module, which can reduce hardware costs and improve the maintainability of the server system.

[0033] The server system provided by the present invention also has the above technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the prior art and the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 A schematic diagram of a memory pooling system provided in a related solution;

[0036] Figure 2 A schematic diagram of a memory pooling system provided by an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of the structure of a computing node provided by an embodiment of the present invention;

[0038] Figure 4 A schematic diagram of a specific structure of a computing node provided by an embodiment of the present invention;

[0039] Figure 5 A schematic diagram of the structure of a memory switch node provided by an embodiment of the present invention;

[0040] Figure 6 A schematic diagram of a specific structure of a memory switch node provided by an embodiment of the present invention;

[0041] Figure 7A schematic diagram of a data center security control module board provided by an embodiment of the present invention;

[0042] Figure 8 A schematic diagram of the structure of a memory pool node provided by an embodiment of the present invention;

[0043] Fig. 9 A schematic diagram of a specific structure of a memory pool node provided by an embodiment of the present invention;

[0044] Fig.10 A schematic diagram of the deployment of a whole machine system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The core of the present invention is to provide a memory pooling system and a server system, which can reduce hardware costs and improve the maintainability of the server system.

[0046] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] like Figure 1 As shown, the memory pooling system in the related scheme (i.e. Figure 1 The memory resource management system shown in the figure) in the computing node (i.e. Figure 1 The computing node module shown in the figure) is provided with a first baseboard management controller, a memory switching node (ie Figure 1 The high-speed interconnect switching chip module shown in the figure) is provided with a second baseboard management controller and a memory resource management controller, and the memory pool node (i.e. Figure 1 The memory resource module shown in the figure) is configured with a third baseboard management controller. The first baseboard management controller serves as the management module of the computing node, the second baseboard manager control and memory resource management controller serves as the management module of the memory exchange node, and the third baseboard management controller serves as the management module of the memory pool node. In this way, each node is configured with its own management module, which will result in high hardware costs. Each node needs to be maintained separately in the later stage, and the maintainability of the server system is not high. To this end, the present invention provides a memory pooling system, which aims to reduce hardware costs and improve the maintainability of the server system.

[0048] Please refer to Figure 2 , Figure 2 A schematic diagram of a memory pooling system provided by an embodiment of the present invention, referring to Figure 2 As shown, the memory pooling system includes:

[0049] A computing node 10, a memory exchange node 20 and a memory pool node 30; the computing node 10 is interconnected with the memory exchange node 20 via a first bus, and is interconnected with the memory exchange node 20 via a network; the memory pool node 30 is interconnected with the memory exchange node 20 via a first bus, and is interconnected with the memory exchange node 20 via a second bus; the memory exchange node 20 includes a data center security control module; the memory exchange node 20 manages the memory pooling system via the data center security control module 201.

[0050] The memory pooling system provided in this embodiment includes a plurality of computing nodes 10, a memory exchange node 20 and a memory pool node 30. The computing node 10 is used to perform computing tasks. The memory pool node 30 is used to provide memory resources. The memory exchange node 20 manages the memory pooling system through the data center security control module 201, which may include allocating and scheduling memory resources, managing memory pool nodes, and aggregating log information of the computing nodes 10.

[0051] The computing node 10 is interconnected with the memory switch node 20 through the first bus, and the memory pool node 30 is interconnected with the memory switch node 20 through the first bus, so that the computing node 10 can obtain memory resources through the first bus.

[0052] In some embodiments, the computing node 10 is interconnected with the memory switch node 20 via a high-speed interconnect bus, and the memory pool node 30 is interconnected with the memory switch node 20 via a high-speed interconnect bus.

[0053] In this embodiment, the computing node 10 and the memory switch node 20 are interconnected via a CXL (Compute Express Link) bus. The memory pool node 30 and the memory switch node 20 are interconnected via a CXL bus.

[0054] The computing node 10 is also interconnected with the memory switch node 20 through a network, so that the computing node 10 and the memory switch node 20 can perform data exchange through the network. For example, the computing node 10 can transmit log information to the memory switch node 20 for aggregation through the network.

[0055] The memory pool node 30 is also interconnected with the memory switch node 20 via the second bus, so that the memory switch node 20 can manage the memory pool node 30 via the second bus.

[0056] In some embodiments, the memory pool node 30 is interconnected with the memory switch node 20 via an integrated circuit bus.

[0057] In this embodiment, the memory pool nodes 30 are connected via an I2C (Inter-Integrated Circuit) bus. The memory switch node 20 can manage the memory pool nodes 30 via the I2C bus.

[0058] refer to Figure 3 As shown, in some embodiments, the computing node 10 includes:

[0059] A central processing unit 101, a first management controller 102, a first Ethernet physical layer device 103, and a first connector 104; the central processing unit 101 is connected to the first connector 104; the first management controller 102 is connected to the first Ethernet physical layer device 103, and the first Ethernet physical layer device 103 is connected to the first connector 104; the computing node is connected to the memory switching node via the first connector 104.

[0060] The first connector 104 is connected to the memory switch node 20. The central processor 101 in the computing node 10 is connected to the first connector 104 through the first bus to be interconnected with the memory switch node 20 through the first connector 104. In the case where the computing node 10 and the memory switch node 20 are interconnected through the CXL bus, the central processor 101 in the computing node 10 is connected to the first connector 104 through the CXL bus.

[0061] The first management controller 102 can be a device with server management and control functions such as a BMC (Baseboard Management Controller), a remote controller ILO (full name Integrated Lights-Out), etc. The first management controller 102 can be used to monitor the temperature, voltage, fan, power supply and other signals of the computing node 10, and make corresponding adjustments to ensure that the computing node 10 is in a healthy state. In addition, the first management controller 102 can also be used to record various hardware information and logs to prompt users and locate subsequent problems. The first management controller 102 is connected to the first Ethernet physical layer device 103, and the first Ethernet physical layer device 103 is connected to the first connector 104. Various log information can be transmitted to the data center security control module 201 of the memory switch node 20 through the first Ethernet physical layer device 103 for unified summary.

[0062] In some embodiments, the computing node includes at least two central processors 101 .

[0063] Exemplary, reference Figure 3 As shown, the computing node 10 includes two central processing units 101. The two central processing units 101 can form a dual-path system.

[0064] In some embodiments, the central processors 101 are connected via a third bus.

[0065] Exemplary, reference Figure 3 As shown, the computing node 10 includes two central processing units 101, and the two central processing units 101 are connected via a third bus to form a dual-channel system.

[0066] In some embodiments, the central processors 101 are connected via a hyperpath interconnect bus.

[0067] Exemplary, reference Figure 4 As shown, two central processors 101 (a first central processor and a second central processor) in the computing node 10 are connected via a UPI (Ultra Path Interconnect) bus.

[0068] In some embodiments, the target central processor in the computing node is connected to the first management controller 102 via a fourth bus.

[0069] A central processor 101 selected from the central processors 101 can be used as a target central processor. The target central processor is connected to the first management controller 102 via a fourth bus. The target central processor can transmit BIOS (Basic Input / Output System) boot log information to the first management controller 102 via the fourth bus.

[0070] In some embodiments, the target central processor in the computing node is connected to the first management controller 102 via an enhanced serial peripheral interface bus.

[0071] Exemplary, reference Figure 4 As shown, the first central processor is used as the target central processor, and the first management controller 102 is the BMC. The BMC monitors the temperature, voltage, fan, power supply and other signals of the computing node 10, and makes corresponding adjustments. In addition, the BMC records the information and logs of various hardware. The target central processor and the BMC are connected via an eSPI (Enhanced Serial Peripheral Interface) bus. The target central processor and the BMC communicate via the eSPI bus to transmit the log information of the BIOS startup.

[0072] In some embodiments, the first management controller 102 is connected to the first Ethernet physical layer device 103 via a Reduced Gigabit Media Independent Interface.

[0073] Exemplary, reference Figure 4As shown, the first management controller 102 is a BMC, and the BMC is connected to the first Ethernet physical layer device 103 via a Reduced Gigabit Media Independent Interface (RGMII).

[0074] In some embodiments, the first Ethernet physical layer device 103 is connected to the first connector 104 via a medium dependent interface.

[0075] refer to Figure 4 As shown, the first Ethernet physical layer device 103 is connected to the first connector 104 (which may be an MCIO connector) via an MDI (Medium Dependent Interface). The BMC is connected to the first Ethernet physical layer device 103 via an RGMII interface, and the first Ethernet physical layer device 103 converts the signal into an MDI signal and connects it to the memory switch node 20.

[0076] refer to Figure 5 As shown, in some embodiments, the memory switch node 20 includes:

[0077] The data center security control module 201, the first switching device 202, the second switching device 203, the second connector 204, the third connector 205, and the fourth connector 206; the first switching device 202 is connected to the second connector 204, the third connector 205 and the fourth connector 206 respectively, the second switching device 203 is connected to the second connector 204 and the fourth connector 206 respectively, the data center security control module 201 is connected to the fourth connector 206, and the third connector 205 is connected to the fourth connector 206; the memory switching node 20 is connected to the computing node 10 through the second connector 204, and is connected to the memory pool node 30 through the third connector 205.

[0078] The data center security control module 201 serves as the management center of the memory pooling system. It can monitor the operating status of each computing node 10, monitor the memory resources of the memory pool node 30, allocate memory resources, and configure the port type, mapping method, bandwidth, and rate of the first switching device 202.

[0079] In some embodiments, the memory switch node 20 includes at least two first switch devices 202 .

[0080] In some embodiments, the memory switch node 20 includes two first switch devices 202. When the first bus is a CXL bus, the corresponding first switch device 202 is a CXL switch device.

[0081] In some embodiments, the memory switch node 20 further includes: a multiplexer 207 ; the multiplexer 207 is connected to the first switch device 202 and the fourth connector 206 .

[0082] In the case where the memory switch node 20 includes two or more first switch devices 202, the memory switch node 20 further includes a multiplexer 207. Each first switch device 202 is connected to the multiplexer 207, and the multiplexer 207 is also connected to the fourth connector. Multiple input signals can be selectively transmitted to one output channel through the multiplexer 207.

[0083] In some embodiments, the multiplexer 207 is connected to the fourth connector 206 via a universal asynchronous receiver / transmitter interface.

[0084] refer to Figure 6 As shown, the multiplexer 207 is connected to the fourth connector 206 (which may be a 4C+ connector) via a UART (Universal Asynchronous Receiver / Transmitter) interface.

[0085] In some embodiments, the memory switch node 20 further includes: a third switch device 208; the third switch device 208 is connected to the first switch device 202 and the fourth connector 206 respectively.

[0086] The third switching device 208 is a PCIe (Peripheral Component Interconnect express) switching device. This embodiment aims to extend the PCIe in-band control signal through the third switching device 208, so as to control the corresponding first switching device 202 through each group of PCIe in-band control signals.

[0087] In some embodiments, the second switching device 203 is connected to the fourth connector 206 via a serial Gigabit Media Independent Interface.

[0088] The second switching device 203 is a network switching device. The second switching device 203 is connected to the fourth connector 206 via an SGMII (Serial Gigabit Media Independent Interface) interface. The second switching device 203 can be connected to the second connector 206 via an MDI interface.

[0089] In some embodiments, the memory switch node 20 further includes: a network connector 209 ; the network connector 209 is connected to the second switch device 203 .

[0090] The network connector 209 may be connected to the second switching device 203 via an MDI interface. A user may obtain the operation status of each node through the network connector 209, and may also manage the memory pooling system through the network connector 209.

[0091] Exemplary, reference Figure 6 As shown, the network switching device and the second connector 206 ( Figure 6 The second switching device 203 is connected to the network connector 209 through a group of MID interfaces, so that the operation status of each node can be obtained through the network connector 209, and the memory pooling system can be managed through the network connector 209. In the case where the second bus is an I2C bus, the third connector 205 ( Figure 6 The downstream MCIO connector shown in FIG. 2 is connected to the fourth connector 206 via an I2C bus.

[0092] Exemplary, reference Figure 6As shown, the memory switch node 20 is equipped with two independent CXL switch devices, namely, the first high-speed interconnect bus switch device (denoted as CXL switch0) and the second high-speed interconnect bus switch device (denoted as CXLswitch1). CXL switch0 and CXL switch1 are connected to the second connector 204 and the third connector 205 through the CXL bus. Among them, the second connector 204 is connected to the computing node 10, and the third connector 205 is connected to the memory pool node 30. The third switch device 208 is a PCIe switch device (denoted as PCIe switch). Two sets of PCIe in-band management signals are extended through the PCIe switch to manage the two CXL switches respectively. The PICe port of all the downstream devices on each CXL switch is configured as DSP (Down Stream Port), and the PCIe port connected to the data center security control module 201 is configured as USP (Upper Stream Port). The data center security control module 201 can identify each device and can enumerate and access the CXL devices in the entire memory pool. The data center security control module 201 needs to reserve enough area in the address space for allocation to CXL devices, supporting 32-bit memory space and 16-bit I / O space. The data center security control module 201 can also configure the port type of the CXL switch and check the link rate through the out-of-band UART.

[0093] In some embodiments, the data center security control module includes:

[0094] A second management controller, a memory, a second Ethernet physical layer device, and a gold finger; the second management controller is connected to the memory, the second Ethernet physical layer device, and the gold finger respectively; the second Ethernet physical layer device is connected to the gold finger.

[0095] The second management controller can be a device with server management and control functions such as BMC, remote controller ILO, etc. In addition, the Form Factor of the data center security control module 201 can be a vertical plug-in method, and the interface signal of the data center security control module 201 is connected to the fourth connector 206 through a gold finger, supporting the transmission of PCIe, I2C, UART, and SGMII signals.

[0096] In some embodiments, the memory includes a double data rate synchronous dynamic random access memory, an embedded multimedia memory, and a first flash memory.

[0097] Exemplary, reference Figure 6As shown, the second management controller is the BMC. The BMC is connected to DDR4 (Double Data Rate 4th Generation Synchronous Dynamic Random Access Memory), EMMC (Embedded Multi Media Card), FLASH, and the second Ethernet physical layer device ( Figure 6 The PHY shown in FIG. 20 is a PHY shown in FIG. 20 . The EMMC can be used to store log information of each node, which is not lost when the power is off. The FLASH stores the firmware. The BMC is connected to the second Ethernet physical layer device, and the RGMII signal can be converted into an SGMII signal through the second Ethernet physical layer device and connected to the second conversion device 203 to communicate with each computing node 10.

[0098] refer to Figure 7 As shown, in some embodiments, the size of the board of the data center security control module 201 can be 89*31.85mm, which meets the design space of 1U height. The BMC can select AST2600.

[0099] In some embodiments, the memory pool node includes:

[0100] Memory controller 301, memory 302, fifth connector 303 and second flash memory 304; the memory controller 301 is connected to the fifth connector 303, the second flash memory 304 and the memory 302 respectively; the memory pool node 30 is connected to the memory switch node 20 via the fifth connector 303.

[0101] refer to Figure 8 As shown, each memory controller 301 is configured with a corresponding FLASH. The FLASH stores firmware. The memory controller 301 reads the firmware information to complete initialization. The memory controller 301 is connected to the memory switch node 20 via the CXL bus uplink and is connected to the memory 302 downlink. The data center security control module 201 can monitor the operating status of the memory controller 301 through the I2C signal.

[0102] In some embodiments, the memory 302 includes: a dual in-line memory 302 module.

[0103] refer to Fig. 9 As shown, each memory controller 301 is configured with a corresponding FLASH. The FLASH stores firmware. The memory controller 301 reads the firmware information to complete initialization. The memory controller 301 is connected to the memory switch node 20 via the CXL bus in the upstream and connected to the DIMM (Dual-Inline-Memory-Modules) in the downstream.

[0104] The number of computing nodes 10 deployed in the memory pooling system can be set differently, and the present invention does not limit this.

[0105] Exemplary, reference Fig.10 As shown, eight computing nodes 10 can be deployed. In order to balance the length of the CXL wiring, four computing nodes 10 can be deployed above and below the cabinet, respectively, and a memory switch node 20 and a memory pool node 30 can be deployed in the middle. The computing nodes and the memory switch nodes are interconnected through the CXL bus and the network, and the memory switch nodes and the memory pool nodes are interconnected through the CXL bus and the I2C bus.

[0106] Each computing node 10 may include two central processors, a BMC, a PHY chip, and an MCIO connector; the central processors are connected via a UPI bus, and the central processor and the MCIO connector are connected via a CXL bus. One of the central processors is connected to the BMC via an eSPI bus, the BMC is connected to the PHY chip via an RGMII interface, and the PHY chip and the MCIO connector are connected via an MDI interface.

[0107] The BMC in the computing node 10 can be used to monitor the temperature, voltage, fan, power supply and other signals of the computing node, and make corresponding adjustments to ensure that the computing node 10 is in a healthy state. In addition, the BMC in the computing node 10 can also be used to record various hardware information and logs to prompt users and locate subsequent problems. The central processing unit can pass the BIOS boot log information to the BMC through the eSPI bus. The BMC can pass various log information to the data center security control module 201 of the memory switch node 20 through the PHY chip for unified summary.

[0108] The memory exchange node 20 may include two CXL switches, an Eth switch, a PCIe switch, a multiplexer, a data center security control module 201, an upstream MCIO connector, a downstream MCIO connector, a 4C+ connector, and a network connector. The CXL switch is connected to the upstream MCIO connector and the downstream MCIO connector via a CXL bus. The Eth switch is connected to the upstream MCIO connector via an MDI interface. The Eth switch is connected to the 4C+ connector via an SGMII interface. The multiplexer is connected to the 4C+ connector via a UART bus. The 4C+ connector is connected to the downstream MCIO connector via an I2C bus.

[0109] Two sets of PCIe in-band management signals can be extended through the PCIe switch to manage two CXL switches respectively. The PICe port of all the downstream devices on each CXL switch is configured as DSP, and the PCIe port connected to the data center security control module 201 is configured as USP. The data center security control module 201 can identify each device and can enumerate and access the CXL devices in the entire memory pool. Among them, the data center security control module 201 needs to reserve enough area in the address space for allocation to CXL devices, supporting 32-bit memory space and 16-bit I / O space.

[0110] The data center security control module 201 may include BMC, DDR4, eMMC, FLASH, PHY chip and gold finger. BMC is connected to DDR4, eMMC, FLASH, PHY chip and gold finger. PHY chip is connected to gold finger.

[0111] In addition, the Form Factor of the data center security control module 201 can be vertically plugged in. The interface signal of the data center security control module 201 is connected to the 4C+ connector through a gold finger, supporting the transmission of PCIe, I2C, UART, and SGMII signals.

[0112] The memory pool node 30 may include: an MCIO connector, an MC (Memory Controller), and each MC has corresponding FLASH and DIMM.

[0113] FLASH stores firmware. MC reads firmware information to complete initialization. MC is connected to the memory switch node 20 via the CXL bus uplink and to the DIMM downlink. The data center security control module 201 can monitor the operating status of the MC via the I2C signal.

[0114] To sum up, the memory pooling system provided by the present invention sets a data center security control module in the memory switch node. The memory switch node manages the memory pooling system through the data center security control module. The management functions such as memory resource allocation can be realized through the data center security control module. The management controller in the memory pool node in the related scheme and the management controller and memory resource manager in the memory switch node are replaced by the data center security control module, which can reduce hardware costs and improve the maintainability of the server system.

[0115] The present invention also provides a server system, the server system includes a memory pooling system, the memory pooling system includes:

[0116] A computing node, a memory exchange node and a memory pool node; the computing node is interconnected with the memory exchange node through a first bus, and is interconnected with the memory exchange node through a network; the memory pool node is interconnected with the memory exchange node through a first bus, and is interconnected with the memory exchange node through a second bus; the memory exchange node includes a data center security control module; the memory exchange node manages a memory pooling system through the data center security control module.

[0117] Based on the above embodiment, as a specific implementation method, the computing node includes:

[0118] A central processing unit, a first management controller, a first Ethernet physical layer device, and a first connector; the central processing unit is connected to the first connector; the first management controller is connected to the first Ethernet physical layer device, and the first Ethernet physical layer device is connected to the first connector; the computing node is connected to the memory switching node via the first connector.

[0119] Based on the above embodiment, as a specific implementation method, the computing node includes at least two central processing units.

[0120] Based on the above embodiment, as a specific implementation mode, the central processing units are connected via a third bus.

[0121] Based on the above embodiment, as a specific implementation mode, each central processing unit is connected via a hyperpath interconnect bus.

[0122] Based on the above embodiment, as a specific implementation manner, the target central processor in the computing node is connected to the first management controller via a fourth bus.

[0123] Based on the above embodiment, as a specific implementation mode, the target central processing unit in the computing node is connected to the first management controller via an enhanced serial peripheral interface bus.

[0124] Based on the above embodiment, as a specific implementation manner, the first management controller is connected to the first Ethernet physical layer device through a reduced gigabit media independent interface.

[0125] Based on the above embodiment, as a specific implementation manner, the first Ethernet physical layer device is connected to the first connector via a medium dependent interface.

[0126] Based on the above embodiment, as a specific implementation method, the computing node is interconnected with the memory switch node through a high-speed interconnect bus, and the memory pool node is interconnected with the memory switch node through a high-speed interconnect bus.

[0127] Based on the above embodiment, as a specific implementation manner, the memory pool node is interconnected with the memory switch node through an integrated circuit bus.

[0128] Based on the above embodiment, as a specific implementation manner, the memory switch node includes:

[0129] The data center security control module, the first switching device, the second switching device, the second connector, the third connector, and the fourth connector; the first switching device is connected to the second connector, the third connector, and the fourth connector respectively, the second switching device is connected to the second connector and the fourth connector respectively, the data center security control module is connected to the fourth connector, and the third connector is connected to the fourth connector; the memory switching node is connected to the computing node through the second connector, and is connected to the memory pool node through the third connector.

[0130] Based on the above embodiment, as a specific implementation manner, the memory switch node includes at least two first switch devices.

[0131] Based on the above embodiment, as a specific implementation manner, the memory switch node further includes: a multiplexer; the multiplexer is connected to the first switch device and the fourth connector.

[0132] Based on the above embodiment, as a specific implementation manner, the multiplexer is connected to the fourth connector via a universal asynchronous receiver-transmitter interface.

[0133] Based on the above embodiment, as a specific implementation manner, the memory switch node further includes: a third switch device; the third switch device is connected to the first switch device and the fourth connector respectively.

[0134] Based on the above embodiment, as a specific implementation manner, the second switching device is connected to the fourth connector via a serial gigabit media independent interface.

[0135] Based on the above embodiment, as a specific implementation manner, the memory switch node further includes: a network connector; and the network connector is connected to the second switch device.

[0136] Based on the above embodiment, as a specific implementation method, the data center security control module includes:

[0137] A second management controller, a memory, a second Ethernet physical layer device, and a gold finger; the second management controller is connected to the memory, the second Ethernet physical layer device, and the gold finger respectively; the second Ethernet physical layer device is connected to the gold finger.

[0138] Based on the above embodiment, as a specific implementation mode, the memory includes a double data rate synchronous dynamic random access memory, an embedded multimedia memory and a first flash memory.

[0139] Based on the above embodiment, as a specific implementation method, the memory pool node includes:

[0140] A memory controller, a memory, a fifth connector and a second flash memory; the memory controller is connected to the fifth connector, the second flash memory and the memory respectively; the memory pool node is connected to the memory switch node via the fifth connector.

[0141] Based on the above embodiment, as a specific implementation mode, the memory includes: a dual in-line memory module.

[0142] For the server system provided by the present invention, reference may be made to the above-mentioned embodiment of the memory pooling system, which will not be described in detail here.

[0143] Because the situation is complicated, it is impossible to list them one by one for explanation. Those skilled in the art should be aware that there may be multiple examples based on the basic principles of the embodiments provided by the present invention and in combination with actual conditions, and all of them should be within the scope of the present invention without paying enough creative work.

[0144] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0145] The technical solution provided by the present invention is described in detail above. Specific examples are used herein to illustrate the principle and implementation of the present invention, and the description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

[0146] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

Claims

1. A memory pooling system, characterized in that: include: Compute nodes, memory exchange nodes, and memory pool nodes; The computing node is interconnected with the memory switch node via a first bus and is interconnected with the memory switch node via a network; The memory pool node is interconnected with the memory switch node through a first bus, and is interconnected with the memory switch node through a second bus; the memory switch node includes a data center security control module; the memory switch node manages the memory pooling system through the data center security control module.

2. The memory pooling system according to claim 1, characterized in that: The computing node comprises: A central processing unit, a first management controller, a first Ethernet physical layer device, and a first connector; the central processing unit is connected to the first connector; the first management controller is connected to the first Ethernet physical layer device, and the first Ethernet physical layer device is connected to the first connector; the computing node is connected to the memory switching node via the first connector.

3. The memory pooling system according to claim 2, characterized in that: The computing node includes at least two central processing units.

4. The memory pooling system according to claim 3, characterized in that: The central processing units are connected via a third bus.

5. The memory pooling system according to claim 4, characterized in that: The central processing units are connected via a hyperpath interconnect bus.

6. The memory pooling system according to claim 2, characterized in that: The target central processing unit in the computing node is connected to the first management controller via a fourth bus.

7. The memory pooling system according to claim 6, characterized in that: The target central processing unit in the computing node is connected to the first management controller via an enhanced serial peripheral interface bus.

8. The memory pooling system according to claim 2, characterized in that: The first management controller is connected to the first Ethernet physical layer device via a reduced gigabit media independent interface.

9. The memory pooling system according to claim 2, characterized in that: The first Ethernet physical layer device is connected to the first connector via a medium dependent interface.

10. The memory pooling system according to claim 1, characterized in that: The computing node is interconnected with the memory switch node through a high-speed interconnect bus, and the memory pool node is interconnected with the memory switch node through a high-speed interconnect bus.

11. The memory pooling system according to claim 1, characterized in that: The memory pool node is interconnected with the memory switch node via an integrated circuit bus.

12. The memory pooling system according to claim 1, characterized in that: The memory exchange node comprises: The data center security control module, the first switching device, the second switching device, the second connector, the third connector, and the fourth connector; the first switching device is connected to the second connector, the third connector, and the fourth connector respectively, the second switching device is connected to the second connector and the fourth connector respectively, the data center security control module is connected to the fourth connector, and the third connector is connected to the fourth connector; the memory switching node is connected to the computing node through the second connector, and is connected to the memory pool node through the third connector.

13. The memory pooling system according to claim 12, characterized in that: The memory switch node includes at least two first switch devices.

14. The memory pooling system according to claim 12, characterized in that: The memory switching node further includes: a multiplexer; the multiplexer is connected to the first switching device and the fourth connector.

15. The memory pooling system according to claim 14, characterized in that: The multiplexer is connected to the fourth connector via a universal asynchronous receiver-transmitter interface.

16. The memory pooling system according to claim 12, characterized in that: The memory switching node further includes: a third switching device; the third switching device is connected to the first switching device and the fourth connector respectively.

17. The memory pooling system according to claim 12, characterized in that: The second switching device is connected to the fourth connector via a serial Gigabit Media Independent Interface.

18. The memory pooling system according to claim 12, characterized in that: The memory switching node further includes: a network connector; the network connector is connected to the second switching device.

19. The memory pooling system according to claim 1, characterized in that: The data center security control module includes: A second management controller, a memory, a second Ethernet physical layer device, and a gold finger; the second management controller is connected to the memory, the second Ethernet physical layer device, and the gold finger respectively; the second Ethernet physical layer device is connected to the gold finger.

20. The memory pooling system according to claim 19, characterized in that: The memory includes a double data rate synchronous dynamic random access memory, an embedded multimedia memory and a first flash memory.

21. The memory pooling system according to claim 1, characterized in that: The memory pool node includes: A memory controller, a memory, a fifth connector and a second flash memory; the memory controller is connected to the fifth connector, the second flash memory and the memory respectively; the memory pool node is connected to the memory switch node via the fifth connector.

22. The memory pooling system according to claim 21, characterized in that: The memory includes: a dual in-line memory module.

23. A server system, characterized in that: Comprising a memory pooling system as described in any one of claims 1 to 22.

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