DSP Multi-Core Computing Power Partitioning Method, Device, Equipment and Storage Medium

Abstract

The present invention discloses a method, device, equipment and storage medium for multi-core computing power division of DSP, which relates to the technical field of data processing. The method includes creating a single RTOS system for the DSP, and only one RTOS, one set of audio frameworks and one set of audio topologies are included in the single RTOS system; performing audio topology definition and identification to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores; defining an inter-core data interface to achieve inter-core communication and data sharing, and performing consistency maintenance operations on the inter-core data. Through the design of a single RTOS system, the present application reduces the occupied code space, reduces the complexity of code maintenance, and reduces the complexity of deployment and operation.

Description

Technical Field

[0001] This application relates to the technical field of data processing, and in particular, to a method, device, equipment and storage medium for dividing the computing power of multiple DSP cores. Background Art

[0002] In the design of digital signal processing chips, especially in audio DSP (Digital Signal Processor), multiple cores are usually designed to provide computing power expansion. Such embedded processor cores are often designed into multiple instances in practice, that is, the design of one core is repeated multiple times, and communication is carried out through inter-core interrupts. Multiple cores store shared data through non-hardware consistent storage.

[0003] See Figure 1 As shown, in the current audio DSP solution based on the above design, an independent RTOS (Real Time Operate System) runs on each DSP core, and each algorithm is statically distributed on different cores. The establishment of the entire data stream of the algorithm depends on the division and coordination based on the application data stream, and the relevant data exchange also varies according to the application scenario. A significant drawback of this design is that one RTOS needs to compile multiple RTOS instances and load and execute them according to the memory distribution. Based on the above limitations, each core needs to run an audio framework instance and provide a pre-divided audio topology map to ensure that each core completes a complete function.

[0004] It can be seen that for the existing audio DSP design solutions, the following problems exist: (1) Multiple independent RTOS instances will cause the code running space to increase exponentially with the number of cores; (2) Multiple independent RTOS instances will cause the overall address space to be statically divided into multiple blocks, resulting in different link scripts for each instance, introducing maintenance complexity; (3) Multiple independent RTOS instances need to cooperate with the deployment and operation of multiple audio framework instances; (4) Multiple independent ROTS instances also require static division of the topology; (5) The static division of the audio topology requires that the interaction between multiple cores must penetrate into the interaction format and content between components in the topology, and the interaction information of different components is different. Summary of the Invention

[0005] This application provides a method, device, equipment and storage medium for dividing the computing power of multiple DSP cores, which reduces the occupied code space, reduces the complexity of code maintenance, and reduces the complexity of deployment and operation through a single RTOS system design.

[0006] In a first aspect, an embodiment of this application provides a method for dividing the computing power of multiple DSP cores. The method for dividing the computing power of multiple DSP cores includes:

[0007] Create a single RTOS system for the DSP, and the single RTOS system only includes one RTOS, one set of audio frameworks, and one set of audio topologies;

[0008] Perform audio topology definition and identification to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores;

[0009] Define the inter-core data interface to achieve inter-core communication and data sharing, and perform consistency maintenance operations on inter-core data.

[0010] Combined with the first aspect, in an implementation manner,

[0011] The RTOS is used to implement task scheduling on multiple cores of the DSP;

[0012] The audio framework is used to implement the operation and scheduling of audio components in the audio topology on multiple cores of the DSP.

[0013] Combined with the first aspect, in an implementation manner, the performing audio topology definition and identification to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores specifically includes:

[0014] Perform the definition of the audio topology and identify the audio components in the audio topology, so as to identify the I / O tasks in the audio topology as executable on one of the cores of the DSP, and the algorithm tasks as executable on another core of the DSP.

[0015] Combined with the first aspect, in an implementation manner, the defining the inter-core data interface to achieve inter-core communication and data sharing specifically includes:

[0016] Define the inter-core data interface to converge all input and output data and input and output dependent data of the core into a standard data structure definition;

[0017] Implement inter-core communication and data sharing through inter-core interrupts and shared memory.

[0018] Combined with the first aspect, in an implementation manner, the performing consistency maintenance operations on inter-core data specifically includes:

[0019] Configure the code and data in the DSP to be cacheable;

[0020] Increase the consistency operations of RTOS shared resources and the consistency operations of inter-core data.

[0021] In a second aspect, an embodiment of the present application provides a DSP multi-core computing power partitioning device, and the DSP multi-core computing power partitioning device includes:

[0022] A creation module, which is used to create a single RTOS system for the DSP, and only one RTOS, a set of audio frameworks, and a set of audio topologies are included in the single RTOS system;

[0023] An identification module, which is used to perform audio topology definition and identification to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores;

[0024] An execution module, which is used to define an inter-core data interface to implement inter-core communication and data sharing, and perform consistency maintenance operations on inter-core data.

[0025] Combined with the second aspect, in an implementation manner,

[0026] The RTOS is used to implement task scheduling on multiple cores of the DSP;

[0027] The audio framework is used to implement the operation and scheduling of audio components in the audio topology on multiple cores of the DSP.

[0028] Combined with the second aspect, in an implementation manner, the performing of audio topology definition and identification to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores specifically includes:

[0029] Performing the definition of the audio topology, and identifying the audio components in the audio topology, so as to identify the I / O tasks in the audio topology as runnable on one of the cores of the DSP, and the algorithm tasks as runnable on another core of the DSP.

[0030] In a third aspect, an embodiment of the present application provides a DSP multi-core computing power partitioning device, and the DSP multi-core computing power partitioning device includes a processor, a memory, and a DSP multi-core computing power partitioning program stored on the memory and executable by the processor. When the DSP multi-core computing power partitioning program is executed by the processor, the steps of the above-mentioned DSP multi-core computing power partitioning method are implemented.

[0031] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, and a DSP multi-core computing power partitioning program is stored on the computer-readable storage medium. When the DSP multi-core computing power partitioning program is executed by a processor, the steps of the above-mentioned DSP multi-core computing power partitioning method are implemented.

[0032] The beneficial effects brought by the technical solutions provided by the embodiments of the present application include:

[0033] Through a single RTOS system design, the code space occupancy is reduced, and the complexity of code maintenance is decreased. On this basis, a shared data structure processing part for a multi-core operating system and cache coherence operation extension are provided. By providing a unique audio framework, the complexity of deployment and operation is reduced. At the same time, based on the unique audio topology, and the division of the audio topology on multiple cores adopts a simple and unified data format and content, and information interaction is achieved through simple data encapsulation between two cores. Description of the Drawings

[0034] Figure 1 Schematic structural diagram designed for multiple independent RTOSs;

[0035] Figure 2 Flow schematic diagram of the DSP multi-core computing power division method of this application;

[0036] Figure 3 Schematic diagram of the single RTOS system design of this application;

[0037] Figure 4 Functional module schematic diagram of the DSP multi-core computing power division device of this application;

[0038] Figure 5 Hardware structural schematic diagram of the DSP multi-core computing power division device of this application. Detailed Embodiments

[0039] In order to enable those skilled in the art to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

[0040] To make the purpose, technical solutions, and advantages of this application clearer, the embodiments of this application will be further described in detail below in conjunction with the drawings.

[0041] In a first aspect, an embodiment of the present application provides a method for partitioning the computing power of a DSP multi-core to solve problems such as the lack of local consistent storage, the code and data being in external memory far from the CPU (Central Processing Unit) core, and the reduction in the efficiency of shared data access after adopting a single RTOS system. A local cache is adopted and cache consistency maintenance operations are added, and independent multi-core requirements are adopted. According to the audio service, application partitioning and computing power allocation are performed. The audio I / O (Input / Output) and audio algorithms are placed on different cores, and a simple and standard data encapsulation interface is provided as the data interaction method between CPU cores.

[0042] In one embodiment, referring to Figure 2 , Figure 2 is a schematic flowchart of the method for partitioning the computing power of the DSP multi-core of the present application. As Figure 2 shown, the method for partitioning the computing power of the DSP multi-core includes:

[0043] S1: Create a single RTOS system for the DSP, and the single RTOS system only includes one RTOS, one set of audio frameworks, and one set of audio topologies;

[0044] Specifically, for the design of the single RTOS system of the present application, refer to Figure 3 shown. It only includes one RTOS, one set of audio frameworks, and one set of audio topologies. In the figure, Core 0 represents one of the cores of the DSP, Core 1 represents another core of the DSP, IPI represents inter-processor interrupt, and Shared Memory represents shared memory.

[0045] For the RTOS in the design of the single RTOS system, the RTOS is used to implement task scheduling on the multi-cores of the DSP. For tasks, it includes DMA (Direct Memory Access) transfer, algorithm operation, parameter adjustment, etc.; the audio framework is used to implement the operation and scheduling of audio components in the audio topology on the multi-cores of the DSP. The audio framework refers to a set of software frameworks that establish an audio topology, transfer audio data streams, and schedule audio data streams according to application requirements. Specifically, for the design of the single RTOS system, in the software part, it includes one RTOS, one set of audio frameworks, one set of audio topologies, multi-core partitioning configuration, inter-core data interface definition, and inter-core communication mechanism. For the audio topology and multi-core partitioning configuration, it is a representation of the partitioning of audio components and the construction of data streams on multi-cores, as well as software partitioning configuration. For example, the I / O task is placed on core Core 0, and the algorithm task is placed on core Core 1.

[0046] S2: Perform audio topology definition and identification to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores;

[0047] Further, in one embodiment, performing audio topology definition and identification to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores specifically includes: defining the audio topology and identifying the audio components in the audio topology to identify the I / O tasks in the audio topology as runnable on one of the cores of the DSP and the algorithm tasks as runnable on another core of the DSP. The audio topology refers to connecting audio components through input-output relationships to provide a network topology, and the audio data stream transfers data according to this topology.

[0048] Specifically, perform the division of computing power on multiple cores, define the audio topology, and at the same time identify the audio components in the audio topology. For example, identify the I / O tasks in the audio topology as runnable on core Core 0 and the algorithm tasks in the audio topology as runnable on core Core 1.

[0049] S3: Define an inter-core data interface to enable inter-core communication and data sharing, and perform consistency maintenance operations on inter-core data.

[0050] Further, in one embodiment, defining an inter-core data interface to enable inter-core communication and data sharing specifically includes: defining an inter-core data interface to converge all input-output data and input-output dependent data of the core into a standard data structure definition; implementing inter-core communication and data sharing through inter-core interrupts and shared memory.

[0051] Specifically, perform inter-core data sharing settings. By defining an inter-core data interface, converge all input-output and input-output dependent data into a standard data structure definition. At the same time, implement inter-core communication and data sharing through inter-core interrupts and shared memory.

[0052] Further, in one embodiment, performing consistency maintenance operations on inter-core data specifically includes: configuring the code and data in the DSP as cacheable; increasing the consistency operations of RTOS shared resources and the consistency operations of inter-core data.

[0053] Specifically, perform consistency maintenance, configure the code and data in the DSP as cacheable, and increase the consistency operations of RTOS shared resources and the consistency operations of inter-core application shared data, i.e., inter-core data.

[0054] This application is designed based on the RTOS system, with an addition of the processing part for the shared data structure of the multi-core operating system and the extension of cache coherence operations. Based on a static partitioning of computing power for a set of audio topologies and a simplified design of inter-core communication, the data transfer boundaries between different cores are clearly defined. A simple input / output data sharing and handshaking mechanism is defined between two cores, and the two cores perform cache coherence maintenance operations to solve the problem of multi-core shared data.

[0055] The DSP multi-core computing power partitioning method of the embodiments of this application, through a single RTOS system design, reduces the occupied code space and the complexity of code maintenance. On this basis, it provides the processing part for the shared data structure of the multi-core operating system and the extension of cache coherence operations, and by providing a unique audio framework, reduces the complexity of deployment and operation. At the same time, based on a unique audio topology, and the partitioning of the audio topology on multi-cores adopts a simple and unified data format and content, and information interaction is achieved through simple data encapsulation between two cores.

[0056] In a second aspect, the embodiments of this application also provide a DSP multi-core computing power partitioning device.

[0057] In one embodiment, referring to Figure 4 , Figure 4 is a schematic diagram of the functional modules of the DSP multi-core computing power partitioning device of this application. As Figure 4 shown, the DSP multi-core computing power partitioning device includes: a creation module, an identification module, and an execution module.

[0058] The creation module is used to create a single RTOS system for the DSP, and the single RTOS system only includes one RTOS, one set of audio frameworks, and one set of audio topologies; the identification module is used to perform audio topology definition and identification to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores; the execution module is used to define an inter-core data interface to achieve inter-core communication and data sharing, and perform consistency maintenance operations on inter-core data.

[0059] For the RTOS in the design of a single RTOS system, the RTOS is used to implement task scheduling on the multiple cores of the DSP. For tasks, they include DMA (Direct Memory Access) transfers, algorithm operations, parameter adjustments, etc.; the audio framework is used to implement the operation and scheduling of audio components in the audio topology on the multiple cores of the DSP. The audio framework refers to a set of software frameworks that establish an audio topology, transfer audio data streams, and schedule audio data streams according to application requirements. Specifically, for the design of a single RTOS system, in the software part, it includes an RTOS, a set of audio frameworks, a set of audio topologies, multi-core partitioning configuration, inter-core data interface definition, and inter-core communication mechanism. For the audio topology and multi-core partitioning configuration, it is a representation for the partitioning of audio components and the construction of data streams on multiple cores, as well as the software partitioning configuration. For example, place I / O tasks on core Core 0 and algorithm tasks on core Core 1.

[0060] In this application, the RTOS is used to implement task scheduling on the multiple cores of the DSP; the audio framework is used to implement the operation and scheduling of audio components in the audio topology on the multiple cores of the DSP.

[0061] In this application, audio topology definition and identification are performed to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores. Specifically, it includes:

[0062] Perform the definition of the audio topology and identify the audio components in the audio topology, so as to identify the I / O tasks in the audio topology as executable on one of the cores of the DSP, and the algorithm tasks as executable on another core of the DSP.

[0063] In this application, an inter-core data interface is defined to achieve inter-core communication and data sharing. Specifically, it includes:

[0064] Define an inter-core data interface to converge all input / output data and input / output dependent data of the core into a standard data structure definition;

[0065] Through inter-core interrupts and shared memory, achieve inter-core communication and data sharing.

[0066] In this application, operations for maintaining the consistency of inter-core data are performed. Specifically, it includes:

[0067] Configure the code and data in the DSP as cacheable;

[0068] Increase the consistency operations of RTOS shared resources and the consistency operations of inter-core data.

[0069] This application designs a single RTOS system to reduce code space occupancy and the complexity of code maintenance. On this basis, it provides a multi-core operating system shared data structure processing part and cache coherence operation extension. By providing a unique audio framework, it reduces the complexity of deployment and operation. At the same time, based on the unique audio topology, and the division of the audio topology on multiple cores adopts a simple and unified data format and content, and information interaction is realized through simple data encapsulation between two cores.

[0070] In a third aspect, an embodiment of this application provides a DSP multi-core computing power division device. The DSP multi-core computing power division device can be a device with data processing functions such as a personal computer (PC), a laptop, or a server.

[0071] Refer to Figure 5 , Figure 5 which is a schematic diagram of the hardware structure of the DSP multi-core computing power division device involved in the solution of the embodiment of this application. In the embodiment of this application, the DSP multi-core computing power division device may include a processor, a memory, a communication interface, and a communication bus.

[0072] Among them, the communication bus can be of any type and is used to interconnect the processor, the memory, and the communication interface.

[0073] The communication interface includes interfaces such as input / output (I / O) interfaces, physical interfaces, and logical interfaces for realizing the interconnection of internal devices of the DSP multi-core computing power division device, and interfaces for realizing the interconnection of the DSP multi-core computing power division device with other devices (such as other computing devices or user devices). This interface is usually an internal interface of the chip, such as AXI, AHB, APB, etc.

[0074] The memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical memory, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0075] The processor may be a general-purpose processor, which can call the DSP multi-core computing power partitioning program stored in the memory and execute the DSP multi-core computing power partitioning method provided in the embodiments of the present application. For example, the general-purpose processor may be a central processing unit (CPU), or may be a dedicated processor for digital signal processing. Among them, the method executed when the DSP multi-core computing power partitioning program is called may refer to the various embodiments of the DSP multi-core computing power partitioning method of the present application, which will not be elaborated here.

[0076] Those skilled in the art can understand that Figure 5 the hardware structure shown in does not constitute a limitation to the present application, and may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0077] Fourthly, the embodiments of the present application further provide a computer-readable storage medium.

[0078] The DSP multi-core computing power partitioning program is stored on the computer-readable storage medium of the present application. When the DSP multi-core computing power partitioning program is executed by a processor, the steps of the DSP multi-core computing power partitioning method as described above are implemented.

[0079] Among them, the method implemented when the DSP multi-core computing power partitioning program is executed may refer to the various embodiments of the DSP multi-core computing power partitioning method of the present application, which will not be elaborated here.

[0080] The terms "including" and "having" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include unlisted steps or units, or may optionally further include other steps or units inherent to these processes, methods, products or devices. The descriptions of terms such as "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit that "first", "second" and "third" are of different types.

[0081] In the description of the embodiments of the present application, terms such as "exemplary", "for example" or "for instance" are used to indicate examples, illustrations or explanations. Any embodiment or design solution described as "exemplary", "for example" or "for instance" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of terms such as "exemplary", "for example" or "for instance" is intended to present relevant concepts in a specific manner.

[0082] In the description of the embodiments of the present application, unless otherwise specified, " / " means "or". For example, A / B may mean A or B. The "and / or" in the text is merely an association relationship describing associated objects, indicating that there can be three relationships. For example, A and / or B may mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present application, "a plurality of" means two or more than two.

[0083] In some processes described in the embodiments of the present application, there are a plurality of operations or steps that appear in a specific order. However, it should be understood that these operations or steps may not be executed in the order in which they appear in the embodiments of the present application or may be executed in parallel. The serial numbers of the operations are only used to distinguish different operations, and the serial numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed in sequence or in parallel, and these operations or steps may be combined.

[0084] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described embodiment methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium as described above (such as ROM / RAM, magnetic disk, optical disc), and includes several instructions to enable a terminal device to execute the methods described in various embodiments of the present application.

[0085] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structural or equivalent process transformation made by using the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A DSP multi-core computing power partitioning method, characterized in that: The DSP multi-core computing power division method includes: Creating a single RTOS system for the DSP, wherein the single RTOS system includes only one RTOS, one audio framework, and one audio topology; Define and identify the audio topology to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores; Define inter-core data interfaces to achieve inter-core communication and data sharing, and perform inter-core data consistency maintenance operations; The audio topology definition and identification is performed to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores, specifically including: An audio topology is defined and audio components in the audio topology are identified, so that an I / O task in the audio topology is identified as executable on one core of the DSP and an algorithm task is identified as executable on another core of the DSP.

2. A DSP multi-core computing power partitioning method as claimed in claim 1, characterized in that: The RTOS is used to implement task scheduling on multiple cores of DSP; The audio framework is used to implement the operation and scheduling of audio components in the audio topology on the multi-core of DSP.

3. A DSP multi-core computing power division method as claimed in claim 1, characterized in that: Defining the inter-core data interface to achieve inter-core communication and data sharing specifically includes: Define the inter-core data interface to aggregate all the core input and output data and input and output dependent data into a standard data structure definition; Inter-core communication and data sharing are achieved through inter-core interrupts and shared memory.

4. A DSP multi-core computing power partitioning method as claimed in claim 1, characterized in that: The operation of maintaining consistency of inter-core data specifically includes: Configure the code and data in the DSP to be cacheable; Increase the consistency of RTOS shared resources and inter-core data.

5. A DSP multi-core computing power division device, characterized in that: The DSP multi-core computing power division device comprises: A creation module, which is used to create a single RTOS system for the DSP, wherein the single RTOS system only includes one RTOS, a set of audio frameworks, and a set of audio topologies; An identification module, which is used to define and identify the audio topology, so as to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores; An execution module, which is used to define an inter-core data interface to achieve inter-core communication and data sharing, and to perform consistency maintenance operations on inter-core data; The step of defining and identifying the audio topology to identify the I / O tasks and algorithm tasks of the audio topology as running on different cores specifically includes: An audio topology is defined and audio components in the audio topology are identified, so that an I / O task in the audio topology is identified as executable on one core of the DSP and an algorithm task is identified as executable on another core of the DSP.

6. A DSP multi-core computing power division device as claimed in claim 5, characterized in that: The RTOS is used to implement task scheduling on multiple cores of DSP; The audio framework is used to implement the operation and scheduling of audio components in the audio topology on the multi-core of DSP.

7. A DSP multi-core computing power partitioning device, characterized in that: The DSP multi-core computing power partitioning device includes a processor, a memory, and a DSP multi-core computing power partitioning program stored in the memory and executable by the processor. When the DSP multi-core computing power partitioning program is executed by the processor, the steps of the DSP multi-core computing power partitioning method as described in any one of claims 1 to 4 are implemented.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a DSP multi-core computing power partitioning program, wherein when the DSP multi-core computing power partitioning program is executed by a processor, the steps of the DSP multi-core computing power partitioning method according to any one of claims 1 to 4 are implemented.

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