A debugging method, electronic device and storage medium for ATPG test vectors

Abstract

The present invention relates to the field of chips, and particularly to a debugging method for ATPG test vectors, an electronic device, and a storage medium. The ATPG parses and loads a first type of simulation database generated by a Verilog simulator. The ATPG performs simulation according to test vectors to generate a second type of simulation database, obtains a set of mismatched test vectors, the instances corresponding to each mismatched test vector, and the mismatched output pins. The test vectors in the set of mismatched test vectors are the test vectors for which the first type of output response data signal observed at the output pins of the chip model does not match the expected response in the test vectors. When the user designates a test vector in the set of mismatched test vectors as the target test vector, the source of the mismatch of the target test vector can be obtained, and the tracing efficiency is high.

Description

Technical Field

[0001] The present invention relates to the field of chips, and particularly to a debugging method for ATPG test vectors, an electronic device, and a storage medium. Background Art

[0002] Automatic Test Pattern Generation (ATPG) is a method for generating test vectors that can detect faults in digital circuits. Testing a chip involves applying a defined input stimulus to a device under test (DUT) in a known state and comparing the resulting output response with the "ideal" expected response. Based on whether the comparison results match, it is determined whether there is a fault in the DUT. The input stimulus applied to the DUT and the "ideal" expected response together form the test vector, which is automatically generated by an ATPG algorithm program. However, if the test vectors generated by ATPG do not meet expectations, the true faults in the DUT cannot be detected, and the test vectors cannot be used to test the DUT.

[0003] To verify the correctness of the test vectors, a Verilog simulation tool is typically used for verification. It applies the stimuli in the test vectors to the chip model for simulation and recalculates the output results based on the input stimuli. The output results obtained from the Verilog simulation tool are compared with the "ideal" expected responses in the test vectors. If the comparison results match, it is considered that the test vectors generated by ATPG are correct; otherwise, the test vectors generated by ATPG are incorrect, which is also referred to as test vector mismatch.

[0004] Typically, the debugger in the Verilog simulation tool is used to debug and find the root cause of test vector mismatch. However, the main drawback of Verilog is that there are only waveform data signals from the Verilog simulation database, that is, only the Verilog simulation view, without the ATPG simulation view. Users need to open the Verilog simulation view and the ATPG simulation view through two different tools respectively. When tracing through each tool, the selected signals need to be manually added to the waveform viewer to view their values, and the source of the mismatch is found by comparing the values in the waveform viewers of the two tools. For modern large-scale designs with hundreds of millions of elements, this method is very difficult, not only complex to operate but also error-prone, with low traceability efficiency. Therefore, how to efficiently debug and trace mismatched test vectors has become an urgent technical problem to be solved. Summary of the Invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a debugging method for ATPG test vector mismatch. The method includes the following steps:

[0007] S100, ATPG parses and loads a first type of simulation database generated by a Verilog simulator. The first type of simulation database stores first type of simulation data signals obtained by the Verilog simulator through simulating by applying stimuli to the inputs of a chip model according to test vectors. The first type of simulation data signals include test vectors and first type of output response data signals; the test vectors include stimuli and expected responses.

[0008] S200, ATPG performs simulation according to test vectors to generate a second type of simulation database. The second type of simulation database stores second type of simulation data signals. The second type of simulation data signals include test vectors and second type of output response data signals output from output pins.

[0009] S300, obtain a set of mismatched test vectors, instances corresponding to each mismatched test vector, and mismatched output pins. The test vectors in the set of mismatched test vectors are those for which it is observed that the first type of output response data signals output from the output pins of the chip model do not match the expected responses in the test vectors.

[0010] S400, when a user designates a test vector in the set of mismatched test vectors as a target test vector, obtain the source of the mismatch of the target test vector, including:

[0011] S410, add the instance of the test vector for which mismatch is observed, and use the added instance of the mismatched test vector as the target instance.

[0012] S420, extract the first type of simulation data signals of all pins of all instances from the first type of simulation database.

[0013] S430, extract the second type of simulation data signals of all pins of all instances from the second type of simulation database.

[0014] S440, when the first type of simulation data signals and the second type of simulation data signals of the same pin are compared and the same result is obtained, display a data signal on the corresponding pin in the instance circuit diagram in the visualization window; otherwise, display the two types of mismatched data signals in a specified display format.

[0015] S450, trace forward from the mismatched output pin of the target instance to obtain the source of the mismatch.

[0016] The present invention has at least the following beneficial effects:

[0017] The method provided by the present invention can combine Verilog simulation data signals and ATPG simulation data signals into one tool and display the two types of simulation signals in the same visualization window. The mismatches between the two types of simulation signals can be displayed in the visualization window in a specified format, and the root cause instances of the mismatches can be found by tracing the highlighted signal paths. This method significantly improves the traceability efficiency and realizes efficient positioning. Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 It is a flowchart of a debugging method for ATPG test vector mismatches provided by an embodiment of the present invention;

[0020] Figure 2 It is a schematic diagram of circuit display in a visualization window implemented by the method provided by an embodiment of the present invention. Detailed Embodiments

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0022] Please refer to Figure 1 , which shows a flowchart of a debugging method for ATPG test vector mismatches. The method includes the following steps:

[0023] S100, the ATPG parses and loads the first type of simulation database generated by the Verilog simulator. The first type of simulation database stores the first type of simulation data signals obtained by the Verilog simulator simulating by applying incentives to the inputs of the chip model according to the test vectors. The first type of simulation data signals include test vectors and the first type of output response data signals; the test vectors include incentives and expected responses.

[0024] Among them, the stimulus in the test vector is the input signal applied to the input pins of the chip model, the expected response is the ideal output signal generated according to the ATPG algorithm, and the first type of output response data signal is the output signal actually generated after the stimulus is applied, observed at the output pins of the chip model. The test vector is automatically generated according to the ATPG algorithm. After applying the stimulus of the test vector to the chip model, the chip model generates an actual output response signal. By comparing the output response signal with the expected response signal, it can be detected whether the chip is faulty, making the output response signals of the faulty circuit module and the correct circuit module different. Among them, the ATPG algorithm generates corresponding test vectors according to various fault models. However, if the test vector itself has problems, it is impossible to correctly verify whether the chip has faults. Therefore, before using the test vector for chip verification, it is also necessary to verify the correctness of the test vector through simulation.

[0025] Among them, the Verilog simulator is used to verify the correctness of the test vector. The first type of simulation database generated by the Verilog simulator also includes the input signal of the input pins and the data signals on each port inside the chip model. It should be noted that since the data signals on the input pins and output pins of the chip model correspond to the stimulus and expected response in the test vector respectively, there are no corresponding stimulus and response for the data signals on each port inside the chip model in the test vector.

[0026] Among them, the ATPG parses the data in the first type of simulation database into simulation data signals that the ATPG can recognize. All the methods in the prior art that can parse the first type of simulation database generated by Verilog simulation into simulation data signals that the ATPG can recognize fall within the protection scope of the present invention.

[0027] It should be noted that for the convenience of understanding, the first type and the second type in the present invention are only used to distinguish between Verilog simulation data signals and ATPG simulation data signals, and do not represent the importance level or order of the data signals, etc.

[0028] S200, the ATPG performs simulation according to the test vector to generate a second type of simulation database. The second type of simulation database stores the second type of simulation data signals. The second type of simulation data signals includes the test vector and the second type of output response data signal output from the output pins.

[0029] It should be noted that the ATPG can not only generate test vectors, but also perform simulation debugging according to the test vectors to verify the correctness of the test vectors. The data signals generated by the simulation are stored in the memory. That is to say, the second type of simulation database refers to the memory that stores the simulation data signals.

[0030] Among them, the second type of simulation data signal further includes the input signal of the input pin of the chip model and the data signals on each port inside the chip model.

[0031] Among them, the test vectors simulated in ATPG are the same as the test vectors simulated in Verilog in S100.

[0032] S300, obtain a set of mismatched test vectors, the instances corresponding to each mismatched test vector, and the mismatched output pins. The test vectors in the set of mismatched test vectors are the test vectors for which it is observed that the first type of output response data signal output by the output pin of the chip model does not match the expected response in the test vector.

[0033] Optionally, the mismatched test vectors, the instances corresponding to the mismatched test vectors, and the mismatched output pins are generated by a Verilog simulator or generated after ATPG parses the first type of simulation database.

[0034] Preferably, the mismatched test vectors, the instances corresponding to the mismatched test vectors, and the mismatched output pins are generated by a Verilog simulator.

[0035] It should be noted that the mismatched test vectors are obtained based on the fact that the first type of output response data signal output by the output pin does not match the expected response in the test vector, and do not include the data signals on each port inside the chip model, nor the second type of output response data signal. Among them, the mismatch means not equal.

[0036] Among them, an instance is a device obtained after instantiating the standard cell library, such as an AND gate circuit model, a buffer, etc.

[0037] S400, when the user designates a test vector in the set of mismatched test vectors as a target test vector, obtain the source of the mismatch of the target test vector.

[0038] Among them, S400 includes:

[0039] S410, add the instance of the test vector for which a mismatch is observed, and use the added instance of the mismatched test vector as the target instance.

[0040] It should be noted that the correspondence between the mismatched target test vectors and the instances has been obtained in S300. Therefore, when the user designates a mismatched test vector, the corresponding instance can be obtained. In order to trace back to the root cause of the mismatched test vector, it is necessary to trace forward. Therefore, the instance of the mismatched test vector is added to ATPG. Adding the instance to ATPG can display all the mismatched data signals in the entire chip model in a specified format in the visualization window. The implementation process is as in S420 - S440.

[0041] S420, extract the first - type simulation data signals of all pins of all instances from the first - type simulation database.

[0042] It should be noted that in the chip model, there are a large number of instances, and each instance has input and output pins. The Verilog simulator can monitor the data signals on each input and output pin.

[0043] S430, extract the second - type simulation data signals of all pins of all instances from the second - type simulation database.

[0044] S440, when the first - type simulation data signal and the second - type simulation data signal of the same pin are compared and the same result is obtained, display a data signal on the corresponding pin in the instance circuit diagram in the visualization window; otherwise, display the two types of mismatched data signals in the specified display format.

[0045] As a preferred embodiment, when comparing the first - type simulation data signal and the second - type simulation data signal of the same pin, the data signals for comparison include the input signals of the input pins of the chip model, the output signals of the output pins, and the data signals of each port inside the chip model.

[0046] It should be noted that if they match, display a data signal; if they don't match, display them in the specified format and display all different data signals for easy viewing.

[0047] Optionally, the specified display format is red font, highlighted background color, or bold and highlighted font. Other specified formats in the prior art for distinguishing between matching and mismatching data formats all fall within the protection scope of the present invention.

[0048] S450, trace forward according to the mismatched output pins of the target instance to obtain the source of the mismatch. The source of the mismatch is the instance where all input signals match. It should be noted that the purpose of debugging is to find the source of the mismatch.

[0049] The method provided by the present invention can combine Verilog simulation data signals and ATPG simulation data signals into one tool and display the two types of simulation signals in the same visualization window. The mismatch between the two types of simulation signals can be displayed in the visualization window in the specified format, and the root instance of the mismatch can be found by tracing the highlighted signal path. This method significantly improves the tracing efficiency and realizes efficient positioning.

[0050] As a preferred embodiment, S450 further includes:

[0051] S451. Trace back forward from the input pin with two types of mismatched data signals in the double-click example to obtain the driver instance connected to the input pin. The mismatched input pins of the driver instance are displayed in a specified format. Double-click the mismatched input pin in the driver instance again, and so on, until the root instance with all input signals matching is obtained. The root instance is the source of the mismatch. This method can clearly display all mismatched instances and their pins. The user can trace the source by double-clicking the mismatched input pin, enabling fast tracing. It is more convenient and faster than the method of cross-comparing with two software in the prior art, with high tracing efficiency and not prone to errors.

[0052] Please refer to Figure 2 , which shows the circuit displayed in the visualization window. Part of the circuit structure is omitted in the circuit. Instance C4 in the circuit is an instance of the added mismatched test vector. Two types of values of all mismatched pins are displayed and highlighted in the visualization window. One signal value is the first type of simulation data signal generated by the Verilog simulator, and the other signal value is the second type of simulation data signal generated by ATPG simulation. The two types of values S100 / S110 of the input pin and the two types of values S111 / S101 of the output pin are highlighted in C4. Continuously trace back forward in the manner of S451. When tracing back to instance C3, when double-clicking the first highlighted input S011 / S111 of C3, the driver instance of C3 is obtained as C1, and all inputs of C1 are matching, without mismatched input pins. At this time, C1 is obtained as the source of the mismatch.

[0053] As a preferred embodiment, S451 is the step for the user to manually trace the source. To improve the tracing efficiency, the embodiment of the present invention also provides the step for automatic tracing. S450 further includes the following steps:

[0054] S452. Add all observed instances of mismatched test vectors to the queue, and pop the first instance in the queue as the tracking instance. Pop the instances in the queue in order, and process each instance of the mismatched test vector in the queue to obtain the source of each mismatched test vector.

[0055] S453. Execute steps S410 - S440 on the tracking instance. When the first type of simulation data signal and the second type of simulation data signal of the input pin of the tracking instance are different, if the driver instance of the tracking instance is not in the mismatched tracking list, put the driver instance into the queue.

[0056] Among them, all driver instances on the backtracking path of the tracking instance during forward backtracking are saved in the tracking list. It should be noted that a driver instance is an instance connected to the input pin of the current instance.

[0057] Among them, S453 also includes:

[0058] S4531, mark the instance added to the queue as a tracked instance and add it to the unmatched tracking list.

[0059] S4532, if for the i-th driver instance instance i the first type of simulation data signals and the second type of simulation data signals of all inputs are the same and there is a different output data signal, then mark instance i as a mismatch source and add it to the mismatch source list.

[0060] S454, repeat the steps of S450 - S451 until the queue is empty.

[0061] S455, mark all instances in the mismatch source list in the visualization window.

[0062] According to the steps provided by S452 - 455, automatic traceability can be achieved, obtaining the source instances of all instances of unmatched test vectors, improving the efficiency of traceability.

[0063] As a preferred embodiment, based on the steps of S452 - 455, mark the paths between all instances in the unmatched tracking list in the visualization window. It can visually display each unmatched path for the user to view.

[0064] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one segment of program related to a method in the method embodiment. The at least one instruction or the at least one segment of program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0065] An embodiment of the present invention also provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0066] An embodiment of the present invention also provides a computer program product, which includes program code. When the program product runs on an electronic device, the program code is used to cause the electronic device to execute the steps in the method according to various exemplary embodiments of the present invention described above in this specification.

[0067] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of the present invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A debugging method for ATPG test vector mismatch, characterized in that, The method includes the following steps: S100, ATPG parses and loads the first type of simulation database generated by the Verilog simulator. The first type of simulation database stores the first type of simulation data signals obtained by the Verilog simulator through simulating the chip model with excitations applied according to test vectors. The first type of simulation data signals include test vectors and the first type of output response data signals; the test vectors include excitations and expected responses. S200, ATPG generates a second type of simulation database according to the test vectors. The second type of simulation database stores the second type of simulation data signals, and the second type of simulation data signals include test vectors and the second type of output response data signals output from output pins. S300, obtain a set of test vectors with mismatches, the instances corresponding to each test vector with a mismatch, and the output pins with mismatches. The test vectors in the set of test vectors with mismatches are the test vectors for which it is observed that the first type of output response data signals output from the output pins of the chip model do not match the expected responses in the test vectors. S400, when the user designates a test vector in the set of test vectors with mismatches as the target test vector, obtain the source of the mismatch of the target test vector, including: S410, add the instance of the test vector where the mismatch is observed, and use the added instance of the test vector with a mismatch as the target instance. S420, extract the first type of simulation data signals of all pins of all instances from the first type of simulation database. S430, extract the second type of simulation data signals of all pins of all instances from the second type of simulation database. S440, when the first type of simulation data signals and the second type of simulation data signals of the same pin are compared and the same result is obtained, display a data signal on the corresponding pin in the instance circuit diagram in the visualization window; otherwise, display the two types of mismatched data signals in the specified display format. S450, trace forward according to the output pin with a mismatch of the target instance to obtain the source of the mismatch.

2. The method according to claim 1, wherein S450 further includes: S451, double-click the input pin with two types of mismatched data signals in the instance to trace back forward to obtain the driver instance connected to the input pin. The input pins with mismatches of the driver instance are displayed in the specified format; double-click the input pin with a mismatch in the driver instance again, and so on, until the root instance with all input signals matching is obtained. The root instance is the source of the mismatch.

3. The method according to claim 1, characterized in that, S450 further includes: S452, add all instances of the observed test vectors with mismatches to the queue, and pop the first instance in the queue as the tracking instance. S453, perform steps S410 - S440 on the tracking instance. When the first type of simulation data signals and the second type of simulation data signals of the input pins of the tracking instance are different, if the driver instance of the tracking instance is not in the mismatch tracking list, then put the driver instance into the queue, including: S4531, mark the instance added to the queue as the tracked instance and add it to the mismatch tracking list. S4532, if for the i-th instance i the first type of simulation data signals and the second type of simulation data signals of all inputs are the same and there is a different output data signal, then mark the instance i as a mismatch source and add it to the mismatch source list; S454. Repeat the steps of S450 - S451 until the queue is empty; S455. Mark all instances in the mismatch source list in the visualization window.

4. The method according to claim 3, characterized in that, Mark the paths between all instances in the mismatched trace list in the visualization window.

5. The method according to claim 1, characterized in that, The first type of simulation database also includes the input signals of the input pins and the data signals on each port inside the chip model; The second type of simulation data signals also includes the input signals of the input pins of the chip model and the data signals on each port inside the chip model; In S440, when comparing the first type of simulation data signals and the second type of simulation data signals of the same pin, the data signals for comparison include the input signals of the input pins of the chip model, the output signals of the output pins, and the data signals on each port inside the chip model.

6. The method according to claim 1, wherein The mismatched test vectors, the instances corresponding to the mismatched test vectors, and the mismatched output pins in S300 are generated by the Verilog simulator.

7. The method according to claim 1, characterized in that, The sources of mismatch in S450 are the instances where all input signals match.

8. The method according to claim 1, wherein The specified display format in S440 is red font, highlighted background color, or bold and highlighted font.

9. A non - transitory computer - readable storage medium, in which at least one instruction or at least one program segment is stored, and the at least one instruction or the at least one program segment is loaded and executed by a processor to implement the method according to any one of claims 1 - 8.

10. An electronic device, characterized in that, It includes a processor and the non - transitory computer - readable storage medium according to claim 9.

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