A hidden PMU reverse engineering general framework based on differential analysis and simulation verification

Abstract

The application provides a hidden PMU reverse engineering general framework based on differential analysis and simulation verification. The framework can efficiently analyze the function and underlying micro-architecture behavior of Intel processor hidden PMU events. By observing the count change of the entire event space during the execution of a carefully designed instruction fragment, the underlying micro-architecture behavior related to these events is inferred. Based on these initial inferences, a logically equivalent simulator is implemented to model these events. Through the differential analysis between the simulator count and the real CPU count, the simulator is gradually optimized to be consistent with the real CPU behavior, enabling us to reveal the micro-architecture features behind the hidden PMU events. The application has wide application prospects in the fields of performance monitoring, micro-architecture research and security detection, not only improving the hardware resource utilization efficiency of performance counters, but also significantly expanding the ability range of processor performance analysis.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computers, and particularly to hidden PMU reverse engineering based on differential analysis and simulation verification in the field of processor hardware. BACKGROUND

[0002] Performance Monitoring Unit (PMU) is an indispensable hardware component in modern high-performance CPUs, whose core function is to monitor performance events of CPUs at runtime. This component has been widely used in the past few decades due to its fine monitoring capability, covering multiple key fields, including performance optimization, reverse engineering, malicious behavior detection, fuzz testing, etc. For example, in performance optimization, PMU can be used to capture bottlenecks and guide code optimization; in reverse engineering, it provides important basis for analyzing underlying hardware behavior; while in the security field, PMU is used to detect malicious attack patterns. In addition, the research on PMU also reveals its potential security risks, such as inferring encryption keys, building covert communication channels, and implementing side-channel attacks through performance data. These functions make PMU play an important role in computer architecture and information security research, and it is regarded as a "magnifying glass" for researchers to deeply understand the behavior of CPUs.

[0003] Intel CPUs usually have two types of PMU, one is Fixed Performance Counter, which is specifically used to record specific performance events. The other is programmable counter, which is generally composed of a pair of Event Select Register and Performance Counter. Developers can search for the required monitored events in the official documents of processor vendors, configure event codes in the event selection register according to their own needs, and then read event counts from the corresponding performance counter. This process can help developers monitor target code performance, identify performance bottlenecks and optimize them.

[0004] Intel's programmable PMU is composed of a pair of Model-Specific Registers (MSRs), namely event selection MSR (IA32_PERFEVTSELx) and performance count MSR (IA32_PMCx). The PMU event is mainly configured through the low 16 bits of the event selection register. The low 8 bits determine the basic type of the event, becoming EventSelect (or EventCode). The high 8 bits are the Unit Mask (UMask) field, which determines the selection condition of the event.

[0005] Existing researches show that the PMU event types officially disclosed by Intel only account for a small part of the entire event selection space. Although existing researches have proved the existence of these hidden events, the analysis of the specific micro-architecture behavior and the specific performance monitoring function of the hidden events is still very limited. This limitation significantly reduces the possibility of using these hidden events in actual scenarios, thereby limiting the further development and application potential of PMU. Therefore, how to excavate and utilize these hidden events has become one of the important directions of current research, which may bring breakthrough progress for CPU performance optimization and security research. SUMMARY

[0006] The application provides a hidden PMU reverse engineering general framework based on differential analysis and simulation verification. The method can automatically, efficiently, reliably and stably analyze the micro-architecture behavior behind the hidden PMU events in Intel CPU and its specific functions. The overall architecture diagram of the method is shown as Figure 1

[0007] The application provides a hidden PMU reverse engineering framework based on differential analysis and simulation verification, a reverse method for branch-related hidden PMU events on Intel CPU and a method for accelerating the reverse process by using UMask Combination mode on Intel CPU.

[0008] A hidden PMU reverse engineering general framework based on differential analysis and simulation verification. Since the main function of PMU is to monitor various architecture / micro-architecture behaviors of CPU during running, and the CPU behavior is often closely related to the instructions it executes. Therefore, the framework analyzes the specific behavior of the hidden PMU by taking the count of the CPU when executing different instructions as the feature of the hidden PMU. This process mainly includes three steps:

[0009] ​S1, Random instruction fragment generation: Some behaviors of CPU can not be triggered by a single instruction, but often need multiple instructions to trigger a specific behavior. Therefore, the main purpose of step S1 is to randomly generate instruction fragments that can trigger the target event. Obviously, the instruction fragments generated by step S1 are also different for different target events. Therefore, different meta-instructions need to be provided for step S1, and the meta-instruction refers to the basic instruction fragment containing a single target event count. That is, when the CPU only executes the meta-instruction, it will trigger a count of one or more target events. Thereafter, step S1 randomly combines according to the meta-instruction. This random combination includes two kinds of random instruction fragments. One is an instruction fragment containing a plurality of random number of meta-instructions, for this random instruction fragment, we can logically know the count value of the corresponding event that it can trigger (because the event that each meta-instruction can trigger is known). The second is an instruction fragment in which a random legal instruction is inserted in the above instruction fragment, and the purpose of this instruction fragment is to prevent missing any factors that can trigger hidden PMU events.

[0010] S2, Hidden event enumeration: The purpose of step S2 is to comprehensively and systematically explore and enumerate the 256 UMask space of the target event EvenctCode to search for hidden PMU events. Specifically, step S2 receives two types of random instruction fragments generated by step S1. For each instruction fragment, step S2 captures the PMU event count value of the target EventCode and its 256 possible UMask combinations when it is executed. Then, these random instruction fragments are taken as an independent feature of the event, and the corresponding event count value is taken as the value of the feature. That is, the final output result of step S2 is a feature matrix with a dimension of 256*N. 256 represents the PMU events (including hidden and public) combined by the entire UMask space and the target EventCode. N represents the number of instruction fragments generated by step S1.

[0011] S3, Simulation verification: The purpose of step S3 is to give a preliminary inference of the function of the hidden PMU event based on the feature matrix generated by step S2 through differential analysis. Based on the preliminary inference result, a logically equivalent model is realized. Then, the first type of random instruction fragment generated by step S1, that is, the instruction fragment that logically grasps the count value it can trigger, is input into the equivalent model to obtain the simulation count. By differentially analyzing the simulation count and the real CPU count, the implementation of the equivalent model is continuously adjusted to fit the real CPU, so that we can determine the specific behavior of the hidden PMU event.

[0012] A reverse method for branch-related hidden PMU events on Intel CPUs. The method is one of the specific implementation instances of the above reverse engineering framework. It mainly includes three modules:

[0013] Random Branch Generator, this module is responsible for generating random branch instruction snippets to trigger the counting of the hidden branch-related PMU events. It mainly includes normal meta-branch instructions and meta-branch instructions that can trigger various branch prediction errors, which are collectively referred to as meta-branches. By randomly combining meta-branches, this module can generate three types of random branch snippets, as shown in the following table: Figure 1 Single-type meta-branch snippet, including combinations of different numbers of meta-branch instructions of a single type; Random meta-branch snippet, including combinations of random numbers of meta-branches of random types; Random instruction snippet, composed of legal instructions inserted into the random meta-branch snippet. Single-type meta-branch snippet and random meta-branch snippet can produce controllable PMU count values. Random instruction snippet can prevent us from missing any factors that may trigger counting.

[0014] Branch Event Enumerator, the main function of this module is to enumerate the event space composed of 4 EventCodes (0x88, 0x89, 0xC4, 0xC5) related to branches on Intel CPUs and their 256 UMask combinations. At the same time, the enumerator receives three types of instruction snippets from the Random Branch Generator. For each instruction snippet, record the target EventCode and the event count value under its 256 UMask combinations. We consider each instruction snippet as a feature of the event, and the corresponding event count value as the feature value. Finally, for each EventCode, the event enumerator will output a feature matrix M:

[0015]

[0016] where each row represents the features of the event of the EventCode and its 256 UMask combinations, and each column represents the count value of different events under the instruction snippet. This matrix is the core input for subsequent analysis and provides sufficient basis for the inference of the hidden event function.

[0017] Event Simulator, the core function of the simulator is to confirm the specific behavior of the hidden PMU event through simulation verification and differential analysis method. This module receives the feature matrix from the enumerator, and makes preliminary speculation on the event behavior according to the features. Before making preliminary speculation, we need to remove redundant events. That is, according to the feature matrix, we analyze whether there are hidden PMU events with similar or identical features. Then use machine learning clustering method to remove redundant events. After that, I can make preliminary speculation, and then realize a logical equivalent model according to the speculation result. The model does not depend on the actual hardware, but outputs the simulation count by inputting the single type of meta-branch fragment generated by the random branch instruction generator and the random meta-branch fragment. Finally, by differentially analyzing the simulation count and the count value of the real CPU, the output of the simulator is constantly adjusted to fit the results of the real CPU, and the specific behavior of the hidden PMU is finally determined.

[0018] A reverse process acceleration method using UMask combination mode. According to the aforementioned reverse method for branch-related hidden PMU events on Intel CPU, we first completed the reverse engineering of the hidden PMU event with EventCode 0xC4 on Intel i7-7700 (Skylake). Because it has a small number of hidden PMU events in the process of event enumeration, the workload of reverse analysis is low. While other EventCodes (0xC5, 0x88, 0x89) have a large number of hidden events, which brings great challenges to our detailed reverse analysis and simulation verification for each event.

[0019] Fortunately, during the analysis process, we observed a specific UMask combination mode, that is, some PMU events can be obtained by combining other events, as shown in Figure 2 We define the events that cannot be obtained by combination as parent events (Parent Event), and the events that can be obtained by combination as child events (Child Event). Based on this rule, we designed a reverse process acceleration method using UMask combination mode. This method focuses all attention on the Parent Event, which makes us only need to perform detailed reverse engineering on the Parent Event. For Child Event, we only need to combine the implemented Parent Event equivalent model to obtain it, which greatly reduces the workload of reverse analysis. Table 1 below shows all Parent Events of 0xC4 on Intel i7-7700:

[0020] Table 1 All Parent Events of 0xC4 on Intel i7-7700

[0021]

[0022] Table 2 below shows the reverse engineering results of all the hidden PMU events on Intel i7-7700:

[0023] Table 2 Reverse engineering results of all the hidden PMU events on Intel i7-7700

[0024]

[0025]

[0026] With this UMask combination pattern based reverse engineering acceleration method, we quickly completed the reverse engineering of other EventCodes, Figure 4 shows the matching rate of all the PMU event equivalent models with the real CPU. At the same time, we extended the reverse engineering of branch-related hidden PMUs to other Intel CPUs, such as Haswell, and the latest Raptor Lake. Table 3 below shows the number of branch-related hidden PMUs on three different micro-architecture CPUs using our reverse engineering framework:

[0027] Table 3 Number of branch-related hidden PMU events on three different micro-architecture Intel CPUs

[0028]

[0029] The branch-related hidden PMU events on Haswell are basically consistent with the results on Skylake. On Raptor Lake, we only observed one hidden Parent Event on E-CORE. In addition, there are only 60 event codes 0xC4 and 0xC5 sub-events on P-CORE, while there are no EventCodes 0x88 and 0x89 events on Raptor Lake. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some drawings of the present application, and other drawings can also be obtained by those skilled in the art without creative labor under the premise of these drawings.

[0031] Figure 1 The hidden PMU reverse engineering framework based on differential analysis and simulation verification;

[0032] Figure 2Figure showing the UMask combination pattern for Child Event 0x03C4;

[0033] Figure 3 Figure showing the fitting results of the Parent Event equivalent model for partial branch correlations on Skylake and the real CPU;

[0034] Figure 4 Figure showing the matching rate of the hidden PMU equivalent model for all branch correlations on Skylake and the real CPU; DETAILED DESCRIPTION

[0035] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0036] Figure 2 Figure showing the UMask combination pattern for Child Event 0x03C4. For Child Event 0x03C4, we find that its count value is always equal to the sum of Parent Event 0x01C4 and Parent Event 0x02C4. At the same time, there is an OR operation relationship between their UMask. Therefore, we speculate that the Child Event can be obtained by OR operation of the UMask of the Parent Event.

[0037] Figure 3 Figure showing the fitting results of the Parent Event equivalent model for partial branch correlations on Skylake and the real CPU. This part of events mainly includes branch-related events recorded in the Haswell document but not recorded in the Skylake document. The x-axis is different random instruction fragments, a total of 1000. The y-axis is different PMU events. The color bar shows the difference between the count value output by the equivalent model of different events for different random instruction fragments and the count value output by the real CPU. The right y-axis shows the evaluation matching rate of each equivalent model and the real CPU.

[0038] Figure 4 Figure showing the matching rate of the hidden PMU equivalent model for all branch correlations on Skylake and the real CPU. For 0xC4, since it is not easy to be affected by transient execution and branch prediction error, we can well complete the simulation verification. For other events, more or less, will be affected by transient execution and branch prediction error, so the matching rate presents a certain degree of fluctuation.

[0039] Those skilled in the art will appreciate that various adaptations and modifications of the application can be configured without departing from the spirit and scope of the application. Therefore, it is to be understood that, within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A hidden PMU event reverse engineering framework based on differential analysis and simulation verification, characterized in that, The method comprises the following steps of: S1, generating an instruction segment containing a specific trigger feature randomly, wherein the instruction segment is composed of a single meta instruction or other legal x86 instructions inserted randomly; the meta instruction refers to a basic instruction segment containing a single target event count; S2, receiving two types of random instruction segments generated in S1; for each instruction segment, S2 captures the PMU event count of the target EventCode and 256 possible UMask combinations thereof when the instruction segment is executed; then, the random instruction segments are taken as an independent feature of an event, and the corresponding event count value is taken as the value of the feature; that is, the final output result of S2 is a feature matrix with a dimension of 256*N; 256 represents the PMU event composed of the entire UMask space and the target EventCode, including hidden and public events; and N represents the number of instruction segments generated in S1; and S3, the purpose of S3 is to give a preliminary inference on the function of the hidden PMU event by means of differential analysis based on the feature matrix generated in S2; based on the preliminary inference result, a logically equivalent model is realized; then, the first type of random instruction segment generated in S1, that is, the instruction segment whose possible triggered count value is logically mastered, is input into the equivalent model to obtain a simulation count; by means of differential analysis on the simulation count and the real CPU count, the equivalent model is adjusted constantly to fit the real CPU, so that the specific behavior of the hidden PMU event can be determined; in addition, by identifying the UMask combination mode in the hidden PMU event, the event analysis process is simplified, and specifically, a parent event is defined as an independent event that cannot be generated by other event combinations, and a child event is an event generated by multiple parent events through UMask combination; by modeling the parent events preferentially, and then quickly generating the child event model through logical combination of the parent event model, the workload of independently modeling the child events is reduced. By using the framework of claim 1, the specific function of a branch-related hidden PMU event on an Intel CPU is analyzed; the method comprises the following steps of: S1, generating a meta branch instruction according to different types of branch instructions, including conditional branches, indirect jumps, function calls and returns; then, a plurality of types of random branch instruction segments are generated by randomly combining the meta branch instructions, and random legal x86 instructions are added to cover potential trigger scenarios; a feature matrix of the branch-related event is constructed, the event trigger function of the branch instruction segment is verified through a simulator model, and the microarchitecture behavior of the branch-related hidden event is gradually determined by combining differential analysis and optimizing the model. By adjusting the basic instruction set and trigger conditions of the generator for different types of hidden events, the scope of application of reverse engineering is expanded by using the framework of claim 1; the method comprises the following steps of: ​ 2. A reverse engineering method for branch-dependent hidden PMU events, characterized in that, ​ ​ 3. A reverse engineering method that extends to other hidden PMU events, characterized in that, ​ The meta-instruction fragments are adjusted for different micro-architecture events to adapt to the trigger conditions of other hidden events; a feature matrix matching the characteristics of target events is constructed through an event enumerator; then, the UMask combination mode is used to group and simplify other hidden events, reducing workload and improving efficiency; finally, the analysis results of different types of events are optimized through a simulation verification process to provide support for performance monitoring and micro-architecture research.

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