Communication interface of unit array and working method thereof
By designing a unit array communication interface including ESI bus, data transceiver controller and other components, the problems of slow response speed, weak anti-interference ability, high power consumption and lack of automatic addressing function in the prior art are solved, and the communication effect of high efficiency, low power consumption and automatic addressing is achieved.
Patent Information
- Application Number
- CN202411675357.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-03-25
AI Technical Summary
The prior art lacks solutions in cell array communication with fast response speed, strong anti-interference capability, low power consumption and automatic addressing functions.
A communication interface of a unit array is designed, using ESI bus, data transceiver controller, wake-up monitor, clock synchronization controller, communication request controller, current encoding generator, automatic addressing arbitrator and other components to realize fast communication, strong anti-interference, low power consumption and automatic addressing functions.
It realizes high communication rate, strong anti-interference capability, low power consumption and automatic addressing functions, which are suitable for communication scenarios of sensor arrays, reducing the installation and use cost of equipment.
Smart Images
Figure CN119690884A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communication technology, and in particular to a communication interface of a unit array and a working method thereof. Background Art
[0002] In systems with many communication nodes, the widely used interfaces are CAN and RS485, which have strong communication speed and anti-interference ability. Among the low-cost solutions, there are LIN and single bus, which can meet the communication needs of general one-master-multiple-slave unit arrays. Although the conventional CAN and RS485 have advantages in speed, they do not have automatic addressing functions and have high hardware costs. The general LIN and single bus have slow communication speeds, weak anti-interference capabilities, and do not support automatic addressing. Some LIN interfaces with integrated automatic addressing are still relatively weak in terms of communication speed and anti-interference. Summary of the invention
[0003] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a communication interface of a cell array with fast response speed, strong anti-interference ability, low power consumption and automatic addressing function and a working method thereof.
[0004] The technical solution adopted by the communication interface of the cell array of the present invention is that the communication interface of the cell array includes An ESI bus, the ESI bus enabling communication between an ESI host and a plurality of ESI slaves; A data transceiver controller, the data transceiver controller is responsible for receiving data transmitted on the ESI bus and sending current-encoded data to the ESI bus; A wake-up monitor, which monitors the signal on the ESI bus at all times when the chip connected to the communication interface enters low power consumption, and sends a wake-up signal to the chip connected to the communication interface if a wake-up frame appears; A clock synchronization controller, wherein the clock synchronization controller constantly monitors the command frames sent by the ESI host on the ESI bus in the command transmission mode so as to maintain clock synchronization with the ESI host, or is configured in the clock synchronization mode of the clock synchronization frame, wherein the ESI host sends a specific clock synchronization frame so that all ESI slaves communicating with the ESI host synchronize their clocks; A communication request controller, when the data of the ESI slave is ready, the communication request controller actively sends a communication request signal to notify the ESI host, and the ESI host obtains the data of the ESI slave; A current encoding generator, which encodes the voltage signal sent by the ESI host into a current signal and sends it to the ESI bus for the ESI slave to respond; An automatic addressing arbitrator, after the ESI slave enters the automatic addressing mode, the ESI slave sends a current signal to the ESI bus, and the automatic addressing arbitrator arbitrates the ESI slave that currently obtains the address allocation right; RDATA, where RDATA is a data receiving register of the ESI slave, used for data buffering; and WDATA, where WDATA is a data sending register of the ESI slave and is used for data caching.
[0005] More specifically, the wake-up monitor includes a negative pulse detection unit and a pulse width comparator communicating with the negative pulse detection unit, the negative pulse detection unit receives the wake-up frame signal on the ESI bus, and receives the clock signal sent by the clock synchronization controller for clock synchronization, the negative pulse detection unit sends a pulse signal to the pulse width comparator, and the pulse width comparator receives a set pulse width threshold. When the pulse signal received by the pulse width comparator exceeds the set pulse width threshold, a wake-up signal is sent to the chip connected to the communication interface.
[0006] The clock synchronization controller includes a frequency meter that receives a signal on the ESI bus, an ESI rate register that receives an output signal from the frequency meter, and an ESI rate generator that receives a signal from the ESI rate register. The frequency meter receives a system clock signal, outputs the bus rate of the ESI bus to a chip connected to the communication interface, and the ESI rate register communicates with the chip.
[0007] The communication request controller includes a request register for receiving a communication request signal from an ESI slave, a current range controller for controlling the current size, and a first amplifier. The request register inputs a signal into the first amplifier, the current range controller controls the current size of the first amplifier, and the current encoding generator converts the voltage signal received from the first amplifier into a current signal and outputs it to the ESI bus.
[0008] The current encoding generator includes a current control unit and a current source for parsing data streams and performing digital-to-analog conversion. The current control unit receives a system clock signal and a data stream, and transmits them to the current source after parsing and digital-to-analog conversion. The current source sends the received signal to the data transceiver controller.
[0009] The automatic addressing arbitrator includes an addressing signal detector for detecting bus commands, an internal automatic addressing counter, and a current data generator for generating current data in a timely manner. The addressing signal detector receives a signal from the ESI bus. The addressing signal detector and the counter jointly send a signal to the current data generator, and the current data generator is communicatively connected with the current encoding generator.
[0010] The data transceiver controller includes an input voltage detector for detecting the logic level of the input signal of the ESI bus, a data collector for collecting data transmitted by the ESI bus, a current output enable register, a current output unit for outputting current, and a second amplifier for amplifying the enable signal input by the current output enable register and the signal input by the current encoding generator. The input end of the input voltage detector is connected to the ESI bus, the data collector is connected to the input voltage detector, the data collector transmits a signal to the RDATA, the output end of the second amplifier is connected to the current output unit, and the current output unit feeds the signal back to the ESI bus.
[0011] The above-mentioned working method of the communication interface of the cell array comprises the following steps: a. Command transmission mode: The ESI host reads and configures the ESI slave by sending command frames; b. Data transmission mode: The ESI host sends a set data transmission signal to notify all ESI slaves to upload data. In one data transmission cycle, each ESI slave is configured with an independent time interval to ensure that all ESI slaves respond without conflict; c. Low power mode: The ESI slave monitors the wake-up frame on the ESI bus to wake up the chip connected to the communication interface; d. Clock synchronization mode: The ESI slave synchronizes its own clock according to the signal of the ESI master to improve the robustness of the system; e. Automatic addressing mode: All ESI slaves are connected in a daisy chain and finally connected to the ESI host. In the automatic addressing mode, the ESI slaves continuously send changing current signals to the ESI bus, while the ESI host continuously monitors the current on the ESI bus. The ESI slaves and host use the automatic addressing arbitrator to determine which ESI slave has been successfully addressed.
[0012] Beneficial effects of the present invention: The communication interface of the unit array of the present invention has a high communication rate, and what is transmitted on the bus are voltage and current signals, and it has strong anti-interference ability. At the same time, it has automatic addressing function, clock synchronization function, active communication request function and support for low power consumption mode. It is particularly suitable for communication scenarios of sensor arrays and meets its design requirements of fast, anti-interference and low power consumption. At the same time, the automatic addressing function also reduces the installation and use cost of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 is a simplified structural diagram of the communication interface of the cell array; Figure 2 It is a simplified schematic diagram of the command transmission mode of the method of the present invention; Figure 3 This is a simplified schematic diagram of the layout of an ESI master and several ESI slaves on an ESI bus. The n in the figure is the serial number of the ESI slave. Figure 4 is a simplified schematic diagram of the wake-up monitor; Figure 5 is a simplified schematic diagram of the clock synchronization controller; Figure 6 is a simplified schematic diagram of the communication request controller; Figure 7 is a simplified schematic diagram of the current encoding generator; Figure 8 is a simplified schematic diagram of the automatic addressing arbitrator; Fig. 9 It is a simple schematic diagram of a data transceiver controller. DETAILED DESCRIPTION
[0014] like Figures 1 to 9 As shown, in the present invention, the communication interface of the unit array includes An ESI bus 1, which enables communication between an ESI host 11 and a plurality of ESI slaves 12; A data transceiver controller 2, which is responsible for receiving data transmitted on the ESI bus 1 and sending current-encoded data to the ESI bus 1; A wake-up monitor 3, which monitors the signal on the ESI bus 1 at all times when the chip connected to the communication interface enters low power consumption, and sends a wake-up signal to the chip connected to the communication interface if a wake-up frame appears; A clock synchronization controller 4, wherein the clock synchronization controller 4 constantly monitors the command frames sent by the ESI host on the ESI bus 1 in the command transmission mode so as to maintain clock synchronization with the ESI host, or is configured in a clock synchronization mode of a clock synchronization frame, wherein the ESI host sends a specific clock synchronization frame so that all ESI slaves communicating with the ESI host synchronize their clocks; The communication request controller 5, when the data of the ESI slave is ready, the communication request controller 5 actively sends a communication request signal to notify the ESI host, and the ESI host obtains the data of the ESI slave; A current encoding generator 6, which encodes the voltage signal sent by the ESI host into a current signal and sends it to the ESI bus 1 for the ESI slave to respond; Automatic addressing arbitrator 7, after the ESI slave enters the automatic addressing mode, the ESI slave sends a current signal to the ESI bus 1, and the automatic addressing arbitrator 7 arbitrates the ESI slave that currently obtains the address allocation right; RDATA8, where RDATA8 is a data receiving register of the ESI slave, used for data buffering; and WDATA9, described WDATA9 is the data transmission register of the ESI slave, and is used for data buffering.
[0015] Specifically, the wake-up monitor 3 includes a negative pulse detection unit 31 and a pulse width comparator 32 that communicates with the negative pulse detection unit 31. The negative pulse detection unit 31 receives the wake-up frame signal on the ESI bus 1, and receives the clock signal sent by the clock synchronization controller 4 for clock synchronization. The negative pulse detection unit 31 sends a pulse signal to the pulse width comparator 32, and the pulse width comparator receives a set pulse width threshold. When the pulse signal received by the pulse width comparator 32 exceeds the set pulse width threshold, a wake-up signal is sent to the chip connected to the communication interface.
[0016] The clock synchronization controller 4 includes a frequency meter 41 that receives the signal on the ESI bus 1, an ESI rate register 42 that receives the output signal of the frequency meter 41, and an ESI rate generator 43 that receives the signal from the ESI rate register 42. The frequency meter 41 receives the system clock signal SCLK, and the frequency meter 41 outputs the bus rate of the ESI bus 1 to the chip connected to the communication interface. The ESI rate register 42 communicates with the chip.
[0017] The communication request controller 5 includes a request register 51 for receiving a communication request signal from the ESI slave, a current level controller 52 for controlling the current size, and a first amplifier 53. The request register 51 inputs a signal into the first amplifier 53, the current level controller 52 controls the current size of the first amplifier 53, and the current encoding generator 6 converts the voltage signal received from the first amplifier 53 into a current signal and outputs it to the ESI bus 1.
[0018] The current encoding generator 6 includes a current control unit 61 and a current source 62 for parsing data streams and performing digital-to-analog conversion. The current control unit 61 receives a system clock signal SCLK and a data stream, and transmits them to the current source 62 after parsing and digital-to-analog conversion. The current source sends the received signal to the data transceiver controller 2.
[0019] The automatic addressing arbitrator 7 includes an addressing signal detector 71 for detecting bus commands, an internal automatic addressing counter 72, and a current data generator 73 for timing the generation of current data. The addressing signal detector 71 receives a signal from the ESI bus 1, and the addressing signal detector 71 and the counter 72 jointly send a signal to the current data generator 73, and the current data generator 73 is communicatively connected with the current encoding generator 6.
[0020] The data transceiver controller 2 includes an input voltage detector 21 for detecting the logic level of the input signal of the ESI bus 1, a data collector 22 for collecting data transmitted by the ESI bus, a current output enable register 23, a current output unit 24 for outputting current, and a second amplifier 25 for amplifying the enable signal input by the current output enable register 23 and the signal input by the current encoding generator 6. The input end of the input voltage detector 21 is connected to the ESI bus 1, the data collector 22 is connected to the input voltage detector 21, the data collector 22 transmits a signal to the RDATA8, and the output end of the second amplifier 25 is connected to the current output unit 24, and the current output unit 24 feeds the signal back to the ESI bus 1.
[0021] The above-mentioned working method of the communication interface of the cell array comprises the following steps: a. Command transmission mode: The ESI host reads and configures the ESI slave by sending command frames; b. Data transmission mode: The ESI host sends a set data transmission signal to notify all ESI slaves to upload data. In one data transmission cycle, each ESI slave is configured with an independent time interval to ensure that all ESI slaves respond without conflict; c. Low power mode: The ESI slave monitors the wake-up frame on the ESI bus 1 to wake up the chip connected to the communication interface; d. Clock synchronization mode: The ESI slave synchronizes its own clock according to the signal of the ESI master to improve the robustness of the system; e. Automatic addressing mode: All ESI slaves are connected in a daisy chain and finally connected to the ESI host. In the automatic addressing mode, the ESI slaves continuously send changing current signals to the ESI bus, while the ESI host continuously monitors the current on the ESI bus. The ESI slaves and host use the automatic addressing arbitrator to determine which ESI slave has been successfully addressed.
[0022] The communication interface of the unit array of the present invention has a high communication rate, and voltage and current signals are transmitted on the bus, with strong anti-interference ability. It also has automatic addressing function, clock synchronization function, active communication request function and support for low power consumption mode, and is particularly suitable for communication scenarios of sensor arrays.
[0023] Finally, it should be emphasized that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A communication interface for a cell array, characterized in that: It includes An ESI bus (1), the ESI bus (1) enabling communication between an ESI master (11) and a plurality of ESI slaves (12); A data transceiver controller (2), the data transceiver controller (2) being responsible for receiving data transmitted on the ESI bus (1) and sending current-encoded data to the ESI bus (1); A wake-up monitor (3), wherein when the chip connected to the communication interface enters low power consumption, the wake-up monitor (3) constantly monitors the signal on the ESI bus (1), and if a wake-up frame appears, sends a wake-up signal to the chip connected to the communication interface; A clock synchronization controller (4), wherein the clock synchronization controller (4) constantly monitors the command frames sent by the ESI host (11) on the ESI bus (1) in a command transmission mode so as to maintain clock synchronization with the ESI host (11), or is configured in a clock synchronization mode of a clock synchronization frame, wherein the ESI host (11) sends a specific clock synchronization frame so that all ESI slaves (12) communicating with the ESI host (11) synchronize their clocks; A communication request controller (5), when the data of the ESI slave (12) is ready, the communication request controller (5) actively sends a communication request signal to notify the ESI host (11), and the ESI host (11) obtains the data of the ESI slave (12); A current encoding generator (6), wherein the current encoding generator (6) encodes a voltage signal sent by the ESI host (11) into a current signal and sends the current signal to the ESI bus (1) for the ESI slave (12) to respond; An automatic addressing arbitrator (7), after the ESI slave (12) enters the automatic addressing mode, the ESI slave (12) sends a current signal to the ESI bus (1), and the automatic addressing arbitrator (7) arbitrates the ESI slave (12) that currently obtains the address allocation right; RDATA (8), wherein RDATA (8) is a data receiving register of the ESI slave (12) and is used for data caching; as well as WDATA (9), the WDATA (9) is a data sending register of the ESI slave (12), used for data buffering.
2. A communication interface for a cell array according to claim 1, characterized in that: The wake-up monitor (3) comprises a negative pulse detection unit (31) and a pulse width comparator (32) communicating with the negative pulse detection unit (31). The negative pulse detection unit (31) receives a wake-up frame signal on the ESI bus (1) and receives a clock signal sent by the clock synchronization controller (4) for clock synchronization. The negative pulse detection unit (31) sends a pulse signal to the pulse width comparator (32). The pulse width comparator receives a set pulse width threshold. When the pulse signal received by the pulse width comparator (32) exceeds the set pulse width threshold, a wake-up signal is sent to a chip connected to the communication interface.
3. A communication interface for a cell array according to claim 1, characterized in that: The clock synchronization controller (4) comprises a frequency meter (41) for receiving a signal on the ESI bus (1), an ESI rate register (42) for receiving an output signal of the frequency meter (41), and an ESI rate generator (43) for receiving a signal from the ESI rate register (42). The frequency meter (41) receives a system clock signal (SCLK). The frequency meter (41) outputs the bus rate of the ESI bus (1) to a chip connected to the communication interface. The ESI rate register (42) communicates with the chip.
4. A communication interface for a cell array according to claim 1, characterized in that: The communication request controller (5) comprises a request register (51) for receiving a communication request signal of the WDATA (9), a current range controller (52) for controlling the current size, and a first amplifier (53); the request register (51) inputs a signal into the first amplifier (53); the current range controller (52) controls the current size of the first amplifier (53); and the current encoding generator (6) converts a voltage signal received from the first amplifier (53) into a current signal and outputs the signal to the ESI bus (1).
5. A communication interface of a cell array according to claim 1 or 4, characterized in that: The current encoding generator (6) comprises a current control unit (61) and a current source (62) for parsing a data stream and performing digital-to-analog conversion. The current control unit (61) receives a system clock signal (SCLK) and a data stream, and transmits the received signal to the current source (62) after parsing and performing digital-to-analog conversion. The current source transmits the received signal to the data transceiver controller (2).
6. A communication interface for a cell array according to claim 1, characterized in that: The automatic addressing arbitrator (7) comprises an addressing signal detector (71) for detecting bus commands, an internal automatic addressing counter (72), and a current data generator (73) for generating current data in a timely manner. The addressing signal detector (71) receives a signal from the ESI bus (1). The addressing signal detector (71) and the counter (72) jointly send a signal to the current data generator (73). The current data generator (73) is in communication connection with the current encoding generator (6).
7. A communication interface for a cell array according to claim 1, characterized in that: The data transceiver controller (2) comprises an input voltage detector (21) for detecting the logic level of an input signal of the ESI bus (1), a data collector (22) for collecting data transmitted by the ESI bus, a current output enable register (23), a current output unit (24) for outputting current, and a second amplifier (25) for amplifying an enable signal input by the current output enable register (23) and a signal input by the current encoding generator (6). The input end of the input voltage detector (21) is connected to the ESI bus (1), the data collector (22) is connected to the input voltage detector (21), the data collector (22) transmits a signal to the RDATA (8), the output end of the second amplifier (25) is connected to the current output unit (24), and the current output unit (24) feeds back a signal to the ESI bus (1).
8. A method for operating a communication interface of a cell array as claimed in claim 1, characterized in that: The method comprises the following steps: a. Command transmission mode: The ESI master (11) reads and configures the ESI slave (12) by sending command frames; b. Data transmission mode: The ESI host (11) sends a set data transmission signal to notify all ESI slaves (12) to upload data. During a data transmission cycle, each ESI slave (12) is configured with an independent time interval to ensure that all ESI slaves (12) respond without conflict; c. Low power mode: The ESI slave (12) monitors the wake-up frame on the ESI bus (1) to wake up the chip connected to the communication interface; d. Clock synchronization mode: The ESI slave (12) synchronizes its own clock according to the signal of the ESI master (11), thereby improving the robustness of the system; e. Automatic addressing mode: All ESI slaves (12) are connected in a daisy chain and finally connected to the ESI host (11). In the automatic addressing mode, the ESI slave (12) continuously sends a changing current signal to the ESI bus, while the ESI host (11) continuously monitors the current on the ESI bus. The ESI slaves (12) and the host use the automatic addressing arbitrator to determine which ESI slave (12) has been successfully addressed.