Non-security-level trusted system based on FPGA (Field Programmable Gate Array) and use method thereof

Abstract

The invention discloses a non-security-level trusted system based on an FPGA and a using method thereof, and relates to the technical field of non-security-level trusted systems.The system comprises a first nonvolatile memory for storing starting data and a second nonvolatile memory for storing configuration data, the first nonvolatile memory and the second nonvolatile memory are respectively in communication connection with the CPU chip and the FPGA board card through the first analog electronic switch and the second analog electronic switch; the first analog electronic switch and the second analog electronic switch are controlled through the FPGA board card to obtain starting data and configuration data, hash value calculation, storage and hash value verification are conducted according to the starting data and the configuration data, and finally starting and resetting of the CPU chip are controlled according to the verification result. According to the scheme provided by the invention, main control and communication functions are realized by adopting a hardware architecture based on an FPGA (Field Programmable Gate Array) technology, and better protection is provided for network hostile attacks.

Description

Technical Field

[0001] The present application relates to the technical field of non-security-level trusted systems, and in particular to a non-security-level trusted system based on FPGA and a method for using the system. Background Art

[0002] With the rapid development of network technology, the importance of trusted systems in key fields including nuclear power, aerospace, and military has become increasingly prominent. When non-safety-level control systems in nuclear power plants exchange network data with external systems, some security-sensitive information may be involved. Once this information is attacked by a network virus, it may be at risk of leakage. Therefore, building a secure and reliable embedded software and hardware architecture system to prevent the execution of untrusted entity processes has become an area that urgently needs to be improved and strengthened in the field of nuclear power safety.

[0003] At present, the methods for achieving embedded system trustworthiness are mainly divided into the following two categories:

[0004] 1) Verify the embedded system through external trusted devices, including external USB trusted devices and external SD card trusted devices.

[0005] 2) Processor-based software programs are used to implement trusted computing. The main implementation method is to isolate the trusted module from the business module and use the trusted module to verify the business module.

[0006] However, the above methods have problems such as instability of introducing external devices, slow startup speed, and vulnerability of processor programs. Therefore, it is particularly necessary to develop a nuclear power non-safety-level trusted system that can effectively solve the defects of the existing technology and meet the safety and reliability requirements of the nuclear power safety field. Summary of the invention

[0007] The purpose of this application is to provide a non-safety-level trusted system based on FPGA and its use method, which can provide better protection against malicious network attacks and improve the sustainability and economy of nuclear power systems.

[0008] To achieve the above objectives, this application provides the following solutions:

[0009] In the first aspect, the present application provides a non-security-level trusted system based on FPGA, including: an FPGA board, a CPU chip, a first non-volatile memory, a first analog electronic switch, a second non-volatile memory, a second analog electronic switch and a trusted chip; the first non-volatile memory is used to store startup data, and the second non-volatile memory is used to store configuration data; the first non-volatile memory is respectively communicated with the CPU chip and the FPGA board through the first analog electronic switch, and the second non-volatile memory is respectively communicated with the CPU chip and the FPGA board through the second analog electronic switch; the FPGA board is connected to the CPU chip and the trusted chip respectively; the FPGA board is used to control the first analog electronic switch and the second analog electronic switch to obtain the startup data stored in the first non-volatile memory and the configuration data stored in the second non-volatile memory, and calculate, store and verify the hash value according to the startup data and the configuration data, and control the startup and reset of the CPU chip according to the verification result.

[0010] Optionally, the FPGA board is used to:

[0011] The first analog electronic switch and the second analog electronic switch are controlled to switch the interface of the first non-volatile memory and the interface of the second non-volatile memory to the FPGA board.

[0012] The startup data stored in the first non-volatile memory is obtained, and the startup data is written into the trusted chip to calculate the hash value to obtain a first hash value.

[0013] Determine whether the system is powered on for the first time. If so, store the first hash value as the first verification hash value in the storage circuit of the trusted chip; if not, verify the first hash value according to the first verification hash value stored in the trusted chip.

[0014] If the verification of the first hash value fails, the CPU chip is controlled to remain reset; if the verification of the first hash value succeeds, the configuration data stored in the second non-volatile memory is obtained, and the configuration data is written into the trusted chip to calculate the hash value to obtain the second hash value.

[0015] Determine whether the system is powered on for the first time. If so, store the second hash value as the second verification hash value in the storage circuit of the trusted chip; if not, verify the second hash value according to the second verification hash value stored in the trusted chip.

[0016] If the verification of the second hash value fails, the CPU chip is controlled to remain reset; if the verification of the second hash value succeeds, the CPU chip is controlled to start.

[0017] Optionally, determining whether the system is powered on for the first time specifically includes: obtaining a first verification hash value and a second verification hash value stored in the trusted chip; if the first verification hash value and the second verification hash value are empty, determining that the system is powered on for the first time; if the first verification hash value and the second verification hash value are not empty, determining that the system is not powered on for the first time.

[0018] Optionally, the first hash value is verified according to the first verification hash value stored in the trusted chip, specifically: the first verification hash value stored in the trusted chip is compared with the first hash value, if the two are consistent, it is determined that the startup data stored in the first non-volatile memory has not been illegally modified, and the verification of the first hash value is successful; if the two are inconsistent, it is determined that the startup data stored in the first non-volatile memory has been illegally modified, and the verification of the first hash value fails.

[0019] The second hash value is verified according to the second verification hash value stored in the trusted chip, specifically: the second verification hash value stored in the trusted chip is compared with the second hash value. If the two are consistent, it is determined that the configuration data stored in the second non-volatile memory has not been illegally modified, and the verification of the second hash value is successful; if the two are inconsistent, it is determined that the configuration data stored in the second non-volatile memory has been illegally modified, and the verification of the second hash value has failed.

[0020] Optionally, the FPGA board controls the CPU chip to remain reset, specifically by: keeping the reset pin at a low level and outputting a CPU reset signal to the CPU chip; the FPGA board controls the CPU chip to start, specifically by: pulling the reset pin level high and releasing the CPU reset signal output to the CPU chip.

[0021] Optionally, the first non-volatile memory is a NORFLASH memory, and the second non-volatile memory is a NANDFLASH memory; the first analog electronic switch is respectively connected to the first non-volatile memory, the CPU chip and the FPGA board through an SPI communication interface; the second analog electronic switch is respectively connected to the second non-volatile memory, the CPU chip and the FPGA board through a NANDFLASH parallel communication interface; the FPGA board is connected to the trusted chip through an SPI communication interface.

[0022] In a second aspect, the present application provides a method for using a non-security-level trusted system based on an FPGA, applying the non-security-level trusted system based on an FPGA as described above, and the method for using the non-security-level trusted system based on an FPGA comprises the following steps:

[0023] The first analog electronic switch and the second analog electronic switch are controlled to obtain the startup data stored in the first non-volatile memory and the configuration data stored in the second non-volatile memory.

[0024] The hash values ​​are calculated, stored and verified according to the startup data and configuration data, and the startup and reset of the CPU chip are controlled according to the verification results.

[0025] Optionally, controlling the first analog electronic switch and the second analog electronic switch to obtain the startup data stored in the first non-volatile memory and the configuration data stored in the second non-volatile memory specifically includes the following steps:

[0026] The first analog electronic switch and the second analog electronic switch are controlled to switch the interface of the first non-volatile memory and the interface of the second non-volatile memory to the FPGA board.

[0027] The startup data stored in the first non-volatile memory and the configuration data stored in the second non-volatile memory are acquired.

[0028] Optionally, the calculation, storage and hash value verification of the startup data and the configuration data are performed respectively, and the startup and reset of the CPU chip are controlled according to the verification result, which specifically includes the following steps:

[0029] The startup data is written into the trusted chip to calculate the hash value to obtain the first hash value.

[0030] Determine whether the system is powered on for the first time. If so, store the first hash value as the first verification hash value in the storage circuit of the trusted chip; if not, verify the first hash value according to the first verification hash value stored in the trusted chip.

[0031] If the verification of the first hash value fails, the CPU chip is controlled to remain reset; if the verification of the first hash value succeeds, the configuration data is written into the trusted chip to calculate the hash value to obtain the second hash value.

[0032] Determine whether the system is powered on for the first time. If so, store the second hash value as the second verification hash value in the storage circuit of the trusted chip; if not, verify the second hash value according to the second verification hash value stored in the trusted chip.

[0033] If the verification of the second hash value fails, the CPU chip is controlled to remain reset; if the verification of the second hash value succeeds, the CPU chip is controlled to start.

[0034] Optionally, determining whether the system is powered on for the first time specifically includes: obtaining a first verification hash value and a second verification hash value stored in the trusted chip; if the first verification hash value and the second verification hash value are empty, determining that the system is powered on for the first time; if the first verification hash value and the second verification hash value are not empty, determining that the system is not powered on for the first time.

[0035] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0036] The present application provides a non-security-level trusted system based on FPGA and a method for using the same. The non-security-level trusted system includes: a first non-volatile memory for storing startup data and a second non-volatile memory for storing configuration data, wherein the first non-volatile memory is respectively connected to a CPU chip and an FPGA board through a first analog electronic switch, and the second non-volatile memory is respectively connected to a CPU chip and an FPGA board through a second analog electronic switch, and the FPGA board is also respectively connected to the CPU chip and a trusted chip; the first analog electronic switch and the second analog electronic switch are controlled through the FPGA board to obtain startup data and configuration data, hash values ​​are calculated, stored, and hash value verification is performed based on the two, and finally the startup and reset of the CPU chip are controlled according to the verification result. The above-mentioned solution provided in the present application is a trusted system based on "hard" logic, which adopts a hardware architecture based on FPGA technology to realize the main control and communication functions. The trusted startup of the system does not rely on the microprocessor and software, and the hardware logic based on FPGA technology cannot be modified at will without engineering tools, providing better protection against malicious network attacks, with high reliability and integrity. In addition, the trusted chip controlled by FPGA board card has a faster processing speed than CPU control, is not easy to be decompiled and cracked, and is easier to be transplanted to the new FPGA board card, thereby improving the sustainability and economy of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1 A schematic diagram of the structure of a non-security-level trusted system based on FPGA provided in one embodiment of the present application.

[0039] Figure 2 A flowchart of a method for using a non-security-level trusted system based on FPGA is provided in one embodiment of the present application.

[0040] Figure 3 This is a flowchart of step A1 in a method for using a non-security-level trusted system based on FPGA provided in one embodiment of the present application.

[0041] Figure 4This is a flowchart of step A2 in a method for using a non-security-level trusted system based on FPGA provided in one embodiment of the present application.

[0042] Figure 5 A flowchart of step A2 in a method for using a non-security-level trusted system based on an FPGA provided in another embodiment of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0045] In an exemplary embodiment, Figure 1 As shown, the present application provides a non-security-level trusted system based on FPGA, including: an FPGA board, a CPU chip, a first non-volatile memory, a first analog electronic switch, a second non-volatile memory, a second analog electronic switch and a trusted chip; the first non-volatile memory is used to store startup data, and the second non-volatile memory is used to store configuration data; the first non-volatile memory is respectively communicated with the CPU chip and the FPGA board through the first analog electronic switch, and the second non-volatile memory is respectively communicated with the CPU chip and the FPGA board through the second analog electronic switch; the FPGA board is connected to the CPU chip and the trusted chip respectively; the FPGA board is used to control the first analog electronic switch and the second analog electronic switch to obtain the startup data stored in the first non-volatile memory and the configuration data stored in the second non-volatile memory, and calculate, store and verify the hash value according to the startup data and the configuration data, and control the startup and reset of the CPU chip according to the verification result.

[0046] In an exemplary embodiment, the FPGA board is specifically used to implement the following functions:

[0047] The first analog electronic switch and the second analog electronic switch are controlled to switch the interface of the first non-volatile memory and the interface of the second non-volatile memory to the FPGA board.

[0048] The startup data stored in the first non-volatile memory is obtained, and the startup data is written into the trusted chip to calculate the hash value to obtain a first hash value.

[0049] Determine whether the system is powered on for the first time. If so, store the first hash value as the first verification hash value in the storage circuit of the trusted chip; if not, verify the first hash value according to the first verification hash value stored in the trusted chip.

[0050] If the verification of the first hash value fails, the CPU chip is controlled to remain reset; if the verification of the first hash value succeeds, the configuration data stored in the second non-volatile memory is obtained, and the configuration data is written into the trusted chip to calculate the hash value to obtain the second hash value.

[0051] Determine whether the system is powered on for the first time. If so, store the second hash value as the second verification hash value in the storage circuit of the trusted chip; if not, verify the second hash value according to the second verification hash value stored in the trusted chip.

[0052] If the verification of the second hash value fails, the CPU chip is controlled to remain reset, the trusted verification fails, and the CPU does not start; if the verification of the second hash value succeeds, the CPU chip is controlled to start, and the trusted verification succeeds. At this time, it is also necessary to control the first analog electronic switch and the second analog electronic switch through the FPGA board to transfer the physical interface control of the first non-volatile memory and the second non-volatile memory to the CPU chip.

[0053] As an optional implementation, determining whether the system is powered on for the first time specifically includes: obtaining a first verification hash value and a second verification hash value stored in the trusted chip; if the first verification hash value and the second verification hash value are empty, determining that the system is powered on for the first time; if the first verification hash value and the second verification hash value are not empty, determining that the system is not powered on for the first time.

[0054] As an optional implementation, the first hash value is verified according to the first verification hash value stored in the trusted chip, specifically: the first verification hash value stored in the trusted chip is compared with the first hash value, if the two are consistent, it is determined that the startup data stored in the first non-volatile memory has not been illegally modified, and the verification of the first hash value is successful; if the two are inconsistent, it is determined that the startup data stored in the first non-volatile memory has been illegally modified, and the verification of the first hash value has failed.

[0055] The second hash value is verified according to the second verification hash value stored in the trusted chip, specifically: the second verification hash value stored in the trusted chip is compared with the second hash value. If the two are consistent, it is determined that the configuration data stored in the second non-volatile memory has not been illegally modified, and the verification of the second hash value is successful; if the two are inconsistent, it is determined that the configuration data stored in the second non-volatile memory has been illegally modified, and the verification of the second hash value has failed.

[0056] In an exemplary embodiment, the FPGA board controls the CPU chip to remain reset, specifically by: keeping the reset pin at a low level and outputting a CPU reset signal to the CPU chip; the FPGA board controls the CPU chip to start, specifically by: pulling the reset pin level high and releasing the CPU reset signal output to the CPU chip.

[0057] As an optional implementation, the first non-volatile memory is a NORFLASH memory, and the second non-volatile memory is a NANDFLASH memory; the first analog electronic switch is respectively connected to the first non-volatile memory, the CPU chip and the FPGA board through an SPI communication interface; the second analog electronic switch is respectively connected to the second non-volatile memory, the CPU chip and the FPGA board through a NANDFLASH parallel communication interface; the FPGA board is connected to the trusted chip through an SPI communication interface.

[0058] In an optional embodiment, the main control devices in the FPGA-based non-safety-level trusted system are domestic devices. For example, the FPGA board uses Gaoyun GW2ALV55, the CPU chip uses Loongson 2K1000, and the trusted chip uses National Technology Z32H10TC. The nuclear power non-safety-level trusted system based on domestic FPGA boards and CPU chips provided in this embodiment is a trusted platform based on "hard" logic with high reliability and integrity.

[0059] Based on the same inventive concept, the embodiment of the present application also provides a method for using a non-security-level trusted system based on FPGA, using the non-security-level trusted system based on FPGA described in the above embodiment, such as Figure 2 As shown in the flowchart, the method for using the FPGA-based non-safety-level trusted system includes the following steps:

[0060] A1. Control the first analog electronic switch and the second analog electronic switch to obtain the startup data stored in the first non-volatile memory and the configuration data stored in the second non-volatile memory. Figure 3 As shown, step A1 specifically includes the following steps:

[0061] A11. Control the first analog electronic switch and the second analog electronic switch to switch the interface of the first non-volatile memory and the interface of the second non-volatile memory to the FPGA board.

[0062] A12. Acquire the startup data stored in the first non-volatile memory and the configuration data stored in the second non-volatile memory.

[0063] A2. Calculate, store and verify the hash value according to the startup data and configuration data, and control the startup and reset of the CPU chip according to the verification result. Figure 4 As shown, step A2 specifically includes the following steps:

[0064] A21. Write the startup data into the trusted chip to calculate the hash value and obtain a first hash value.

[0065] A22. Determine whether the system is powered on for the first time. If not, execute step A23; if yes, execute step A24.

[0066] A23, verify the first hash value according to the first verification hash value stored in the trusted chip. If the verification of the first hash value succeeds, execute step A25; if the verification of the first hash value fails, execute step A29.

[0067] A24. Store the first hash value as a first verification hash value in a storage circuit of the trusted chip.

[0068] A25. Write the configuration data into the trusted chip to calculate the hash value and obtain a second hash value.

[0069] A26. Determine whether the system is powered on for the first time. If not, execute step A27; if yes, execute step A28.

[0070] A27, verify the second hash value according to the second verification hash value stored in the trusted chip. If the verification of the second hash value fails, execute step A29; if the verification of the second hash value succeeds, execute step A210.

[0071] A28. Store the second hash value as a second verification hash value in the storage circuit of the trusted chip, and jump to step A210.

[0072] A29, control the CPU chip to remain reset.

[0073] A210, controls the CPU chip startup.

[0074] Specifically, to determine whether the system is powered on for the first time, the first verification hash value and the second verification hash value stored in the trusted chip are obtained. If the first verification hash value and the second verification hash value are empty, it is determined that the system is powered on for the first time; if the first verification hash value and the second verification hash value are not empty, it is determined that the system is not powered on for the first time.

[0075] In another optional implementation, the trusted chip may pre-store hash data of the startup data and the configuration data, that is, the trusted chip may pre-store a first verification hash value and a second verification hash value. In this implementation, Figure 5 As shown, step A2 specifically includes the following steps:

[0076] A21. Write the startup data into the trusted chip to calculate the hash value and obtain a first hash value.

[0077] A22, verify the first hash value according to the first verification hash value stored in the trusted chip. If the verification of the first hash value succeeds, execute step A23; if the verification of the first hash value fails, execute step A25.

[0078] A23. Write the configuration data into the trusted chip to calculate the hash value and obtain a second hash value.

[0079] A24, verify the second hash value according to the second verification hash value stored in the trusted chip. If the verification of the second hash value fails, execute step A25; if the verification of the second hash value succeeds, execute step A26.

[0080] A25, control the CPU chip to remain reset.

[0081] A26, control CPU chip startup.

[0082] In this implementation, the determination of the first power-on of the system may also be performed between appropriate steps, and then corresponding steps may be executed according to the determination result.

[0083] The solution provided by the above embodiment provided by the present application is a nuclear power non-safety-level trusted system based on domestic FPGA and CPU. It is a trusted system based on "hard" logic. It adopts a hardware architecture based on FPGA technology to realize the main control and communication functions. The trusted startup of the system does not rely on the microprocessor and software. The FPGA board realizes the security function of the trusted system in the form of pure hardware circuits. The execution of the hardware circuit is more certain than the execution of software and operating system. Moreover, the hardware logic based on FPGA technology cannot be modified at will without engineering tools. Secondly, the modification of the hardware logic needs to be carried out through a special interface. When the system is running, the interface is disconnected; finally, the hardware logic adopts encryption measures to make it difficult for the FPGA logic to be reproduced through reverse engineering, providing better protection against malicious network attacks, with high reliability and integrity. In addition, the processing speed of the trusted chip controlled by the FPGA board is faster than that of the CPU control method, and it is not easy to be decompiled and cracked. Compared with the rapid update and replacement of CPU chips, the FPGA technology uses the FPGA logic code and register-level design compiled by the hardware description language to be transplanted into the new FPGA chip. The new FPGA chip only needs to use new software tools to re-synthesize and layout the existing code and design, which improves the sustainability and economy of the system.

[0084] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A non-security-level trusted system based on FPGA, characterized in that: include: FPGA board, CPU chip, first non-volatile memory, first analog electronic switch, second non-volatile memory, second analog electronic switch and trusted chip; The first non-volatile memory is used to store startup data, and the second non-volatile memory is used to store configuration data; The first non-volatile memory is respectively connected to the CPU chip and the FPGA board through the first analog electronic switch, and the second non-volatile memory is respectively connected to the CPU chip and the FPGA board through the second analog electronic switch; the FPGA board is respectively connected to the CPU chip and the trusted chip; the FPGA board is used to control the first analog electronic switch and the second analog electronic switch to obtain the startup data stored in the first non-volatile memory and the configuration data stored in the second non-volatile memory, calculate, store and verify the hash value according to the startup data and the configuration data, and control the startup and reset of the CPU chip according to the verification result.

2. The non-safety-level trusted system based on FPGA according to claim 1, characterized in that: The FPGA board is used for: Controlling the first analog electronic switch and the second analog electronic switch to switch the interface of the first non-volatile memory and the interface of the second non-volatile memory to the FPGA board; Acquire startup data stored in the first non-volatile memory, write the startup data into the trusted chip to calculate a hash value, and obtain a first hash value; Determine whether the system is powered on for the first time, and if so, store the first hash value as a first verification hash value in a storage circuit of the trusted chip; If not, verifying the first Hash value according to the first verification Hash value stored in the trusted chip; If the verification of the first hash value fails, the CPU chip is controlled to remain reset; if the verification of the first hash value succeeds, the configuration data stored in the second non-volatile memory is obtained, and the configuration data is written into the trusted chip to calculate the hash value to obtain a second hash value; Determine whether the system is powered on for the first time, and if so, store the second hash value as a second verification hash value in the storage circuit of the trusted chip; If not, verifying the second Hash value according to the second verification Hash value stored in the trusted chip; If the verification of the second hash value fails, the CPU chip is controlled to remain reset; if the verification of the second hash value succeeds, the CPU chip is controlled to start.

3. The non-safety-level trusted system based on FPGA according to claim 2, characterized in that: Determining whether the system is powered on for the first time specifically includes: obtaining a first verification hash value and a second verification hash value stored in the trusted chip, and if the first verification hash value and the second verification hash value are empty, determining that the system is powered on for the first time; if the first verification hash value and the second verification hash value are not empty, determining that the system is not powered on for the first time.

4. The non-safety-level trusted system based on FPGA according to claim 2, characterized in that: Verifying the first Hash value according to the first verification Hash value stored in the trusted chip, specifically: comparing the first verification Hash value stored in the trusted chip with the first Hash value, and if the two are consistent, determining that the startup data stored in the first non-volatile memory has not been illegally modified, and the verification of the first Hash value is successful; If the two are inconsistent, it is determined that the startup data stored in the first non-volatile memory has been illegally modified, and the verification of the first hash value has failed; Verifying the second Hash value according to the second verification Hash value stored in the trusted chip, specifically: comparing the second verification Hash value stored in the trusted chip with the second Hash value, and if the two are consistent, determining that the configuration data stored in the second non-volatile memory has not been illegally modified, and the verification of the second Hash value is successful; If the two are inconsistent, it is determined that the configuration data stored in the second non-volatile memory has been illegally modified, and the verification of the second hash value fails.

5. The non-safety-level trusted system based on FPGA according to claim 2, characterized in that: The FPGA board controls the CPU chip to remain reset, specifically by keeping the reset pin at a low level and outputting a CPU reset signal to the CPU chip; the FPGA board controls the CPU chip to start up, specifically by pulling the reset pin level high and releasing the CPU reset signal output to the CPU chip.

6. The non-safety-level trusted system based on FPGA according to claim 1, characterized in that: The first non-volatile memory is a NORFLASH memory, and the second non-volatile memory is a NANDFLASH memory; The first analog electronic switch is respectively connected to the first non-volatile memory, the CPU chip and the FPGA board through an SPI communication interface; the second analog electronic switch is respectively connected to the second non-volatile memory, the CPU chip and the FPGA board through a NANDFLASH parallel communication interface; the FPGA board is connected to the trusted chip through an SPI communication interface.

7. A method for using a non-security-level trusted system based on FPGA, characterized in that: The non-safety-level trusted system based on FPGA as claimed in any one of claims 1 to 6 is applied, and the method for using the non-safety-level trusted system based on FPGA includes: Controlling the first analog electronic switch and the second analog electronic switch to obtain the startup data stored in the first non-volatile memory and the configuration data stored in the second non-volatile memory; The hash values ​​are calculated, stored and verified according to the startup data and the configuration data, and the startup and reset of the CPU chip are controlled according to the verification result.

8. The method for using the non-safety-level trusted system based on FPGA according to claim 7, characterized in that: Controlling the first analog electronic switch and the second analog electronic switch to obtain the startup data stored in the first non-volatile memory and the configuration data stored in the second non-volatile memory specifically includes: Controlling the first analog electronic switch and the second analog electronic switch to switch the interface of the first non-volatile memory and the interface of the second non-volatile memory to the FPGA board; The startup data stored in the first non-volatile memory and the configuration data stored in the second non-volatile memory are acquired.

9. The method for using the non-safety-level trusted system based on FPGA according to claim 8, characterized in that: Calculating, storing, and verifying hash values ​​according to the startup data and the configuration data, and controlling startup and resetting of the CPU chip according to the verification results, specifically including: Writing the startup data into the trusted chip to calculate a hash value to obtain a first hash value; Determine whether the system is powered on for the first time, and if so, store the first Hash value as a first verification Hash value in the storage circuit of the trusted chip; if not, verify the first Hash value according to the first verification Hash value stored in the trusted chip; If the verification of the first hash value fails, the CPU chip is controlled to remain reset; if the verification of the first hash value succeeds, the configuration data is written into the trusted chip to calculate the hash value to obtain a second hash value; Determine whether the system is powered on for the first time, and if so, store the second hash value as a second verification hash value in the storage circuit of the trusted chip; if not, verify the second hash value according to the second verification hash value stored in the trusted chip; If the verification of the second hash value fails, the CPU chip is controlled to remain reset; if the verification of the second hash value succeeds, the CPU chip is controlled to start.

10. The method for using the non-safety-level trusted system based on FPGA according to claim 9, characterized in that: Determining whether the system is powered on for the first time specifically includes: obtaining a first verification hash value and a second verification hash value stored in the trusted chip, and if the first verification hash value and the second verification hash value are empty, determining that the system is powered on for the first time; if the first verification hash value and the second verification hash value are not empty, determining that the system is not powered on for the first time.

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