Graphics rendering method, device, electronic device and storage medium

Abstract

The present disclosure relates to a graphics rendering method, apparatus, electronic device, and storage medium. The method comprises: receiving a first drawing instruction sent by an application, wherein the first drawing instruction includes at least one first identifier for indicating a rendering target; if the first identifier also exists in a second drawing instruction, and a second identifier other than the first identifier in the second drawing instruction is set to a null value in the first drawing instruction, applying to bind the first drawing instruction to a GPU to keep the rendering target the same as the second drawing instruction, and instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction; and submitting an instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time so that the GPU can perform graphics rendering operations. Embodiments of the present disclosure can improve graphics rendering efficiency.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a graphics rendering method, device, electronic device, and storage medium. Background Art

[0002] Tile-Based Deferred Rendering (TBDR) is an efficient graphics rendering technology for graphics processing units (GPUs). It breaks down the rendering process into multiple small tiles (tiles) and significantly improves rendering efficiency by processing multiple tiles in parallel. In TBDR, the drawing instructions sent by the application are first collected and stored in the command buffer. After a frame of commands is collected, the rendering commands are assigned to tiles, and then the GPU processes these tiles in parallel. Each tile is handled by a high-speed renderer that processes all the commands within it and writes the results back to the frame buffer. Tiles have a specific data storage structure layout. If multiple drawing instructions share the same data storage structure and have no dependencies, they can be assigned to the same tile for batch processing, further improving efficiency and reducing state changes and memory access overhead.

[0003] However, when multiple consecutive drawing instructions (draw) in a frame of graphics frequently switch render targets (RT), the complexity of rendering increases, resulting in a decrease in rendering performance. Summary of the Invention

[0004] The present disclosure proposes a graphics rendering technology solution.

[0005] According to one aspect of the present disclosure, a graphics rendering method is provided, which is applied to a graphics processor (GPU) driver, comprising:

[0006] receiving a first drawing instruction sent by an application, wherein the first drawing instruction includes at least one first identifier for indicating a rendering target, and the rendering target is used to cache a rendering result obtained by executing the drawing instruction;

[0007] If the first identifier also exists in the second drawing instruction, and the second identifiers other than the first identifier in the second drawing instruction are set to null values ​​in the first drawing instruction, then the first drawing instruction is applied to bind to the same render target of the GPU as the second drawing instruction, and the GPU is instructed not to perform a write operation on the first render target corresponding to the second identifier when executing the first drawing instruction;

[0008] Submitting an instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time so that the GPU performs a graphics rendering operation.

[0009] In a possible implementation, instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction includes:

[0010] The write mask of the first rendering target in the first drawing instruction is set to a first indication flag, where the first indication flag is used to instruct the GPU not to perform a write operation on the first rendering target when executing the first drawing instruction.

[0011] In one possible implementation, the GPU driver sequentially and continuously receives multiple drawing instructions, where the second drawing instruction is a drawing instruction received before the first drawing instruction. After instructing the GPU not to perform a write operation on a first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes:

[0012] The first drawing instruction is added to the instruction set where the second drawing instruction is located.

[0013] In a possible implementation, after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes:

[0014] receiving a third drawing instruction sent by the application;

[0015] Submitting the instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time includes:

[0016] In a case where the third identifier in the third drawing instruction does not exist in the first drawing instruction, the instruction set is submitted to the GPU at one time.

[0017] In a possible implementation, the GPU driver sequentially and continuously receives multiple drawing instructions, where the multiple drawing instructions include the first drawing instruction and the second drawing instruction; and submitting the instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time includes:

[0018] Among any two drawing instructions that are adjacent in time sequence among the multiple drawing instructions, if the former drawing instruction includes all the identifiers in the latter drawing instruction, the multiple drawing instructions are submitted to the GPU at one time.

[0019] In a possible implementation, after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes:

[0020] The state flag corresponding to the first rendering target is set to a first state value, where the first state value is used to indicate that the first rendering target is in a non-writing state.

[0021] In a possible implementation, the method further includes:

[0022] When the state flag corresponding to the first rendering target is a first state value, if the third identifier in the third drawing instruction does not exist in the first drawing instruction, setting a write mask of the corresponding rendering target according to the identifier in the third drawing instruction.

[0023] According to one aspect of the present disclosure, a graphics rendering device is provided, which is applied to a graphics processor (GPU) driver, including:

[0024] An instruction receiving unit is configured to receive a first drawing instruction sent by an application, wherein the first drawing instruction includes at least one first identifier for indicating a rendering target, and the rendering target is configured to cache a rendering result obtained by executing the drawing instruction;

[0025] an instructing unit, configured to, if the first identifier also exists in the second drawing instruction and the second identifiers other than the first identifier in the second drawing instruction are set to null values ​​in the first drawing instruction, keep the rendering target of the GPU bound to the first drawing instruction the same as that of the second drawing instruction, and instruct the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction;

[0026] The submitting unit is configured to submit an instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time, so that the GPU performs a graphics rendering operation.

[0027] In a possible implementation, the instructing unit is configured to set a write mask of the first rendering target in the first drawing instruction to a first indication flag, where the first indication flag is configured to instruct the GPU not to perform a write operation on the first rendering target when executing the first drawing instruction.

[0028] In a possible implementation, the GPU driver receives multiple drawing instructions in sequence and continuously, the second drawing instruction is a drawing instruction received before the first drawing instruction, and the device further includes:

[0029] The aggregation unit is configured to add the first drawing instruction to the instruction set where the second drawing instruction is located.

[0030] In a possible implementation, after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the apparatus further includes:

[0031] a third instruction receiving unit, configured to receive a third drawing instruction sent by an application;

[0032] The submitting unit is configured to submit the instruction set to the GPU at one time when the third identifier in the third drawing instruction does not exist in the first drawing instruction.

[0033] In one possible implementation, the GPU driver sequentially and continuously receives multiple drawing instructions, where the multiple drawing instructions include the first drawing instruction and the second drawing instruction. The submitting unit is configured to submit the multiple drawing instructions to the GPU at once if, among any two sequentially adjacent drawing instructions, the earlier drawing instruction includes all identifiers in the later drawing instruction.

[0034] In a possible implementation, the apparatus further includes: a state setting unit, configured to set a state flag corresponding to the first rendering target to a first state value, where the first state value is used to indicate that the first rendering target is in a non-writing state.

[0035] In one possible implementation, the apparatus further includes: a write mask setting unit configured to, when a state flag corresponding to the first rendering target is a first state value, set a write mask of the corresponding rendering target according to the identifier in the third drawing instruction if the third identifier in the third drawing instruction does not exist in the first drawing instruction.

[0036] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0037] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above method is implemented.

[0038] In an embodiment of the present disclosure, after receiving a first drawing instruction sent by an application; if the first identifier in the first drawing instruction also exists in a second drawing instruction, and the second identifier in the second drawing instruction, other than the first identifier, is set to a null value in the first drawing instruction, then the first drawing instruction is applied to be bound to the same render target on the GPU as the second drawing instruction, and the GPU is instructed not to perform a write operation on the first render target corresponding to the second identifier when executing the first drawing instruction. Thus, the render target corresponding to the first drawing instruction is not actually set to a null value, but remains the same as the second drawing instruction. The first drawing instruction and the second drawing instruction can then share the same data storage structure (layout) and be placed in the same instruction set. By submitting the instruction set containing at least the first and second drawing instructions to the GPU at once, the additional overhead caused by the interaction between the GPU driver and the operating system can be reduced compared to submitting the instructions in multiple batches, thereby improving graphics rendering efficiency. Furthermore, the GPU can batch the instruction sets, further improving processing efficiency.

[0039] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0041] Figure 1 A flowchart of a graphics rendering method according to an embodiment of the present disclosure is shown.

[0042] Figure 2 A flowchart of a graphics rendering method according to an embodiment of the present disclosure in an actual application scenario is shown.

[0043] Figure 3 A flowchart of a graphics rendering method according to an embodiment of the present disclosure in an actual application scenario is shown.

[0044] Figure 4 A block diagram of a graphics rendering device according to an embodiment of the present disclosure is shown.

[0045] Figure 5 A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0046] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0047] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0048] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0049] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0050] When continuous drawing instructions (draw) for a frame of image frequently switch render targets (RT), the efficiency optimizations in the TBDR architecture are destroyed. Each render target may require a different layout (layout) or state settings, which makes it impossible to simply merge these drawing commands into the same tile for rendering. In this case, the User Mode Driver (UMD) needs to interrupt the continuous drawing commands and submit them to the hardware for execution in multiple batches.

[0051] Because the GPU driver needs to interact with the operating system (such as Windows) every time it submits instructions to the hardware, this adds additional overhead. Especially in a virtual environment built by a virtual machine, this interaction may be affected by greater latency because virtual environments usually have additional overhead and synchronization requirements, and the time interval between two rendering commands may reach around 0.2ms.

[0052] In an embodiment of the present disclosure, after receiving a first drawing instruction sent by an application; if the first identifier in the first drawing instruction also exists in a second drawing instruction, and the second identifier in the second drawing instruction, other than the first identifier, is set to a null value in the first drawing instruction, then the first drawing instruction is applied to be bound to the same render target on the GPU as the second drawing instruction, and the GPU is instructed not to perform a write operation on the first render target corresponding to the second identifier when executing the first drawing instruction. Thus, the render target corresponding to the first drawing instruction is not actually set to a null value, but remains the same as the second drawing instruction. The first drawing instruction and the second drawing instruction can then share the same data storage structure (layout) and be placed in the same instruction set. By submitting the instruction set containing at least the first and second drawing instructions to the GPU at once, the additional overhead caused by the interaction between the GPU driver and the operating system can be reduced compared to submitting the instructions in multiple batches, thereby improving graphics rendering efficiency. Furthermore, the GPU can batch the instruction sets, further improving processing efficiency.

[0053] Figure 1 A flowchart of a graphics rendering method according to an embodiment of the present disclosure is shown, which is applied to a graphics processor GPU driver. Figure 1 As shown, the method includes:

[0054] In step S11, a first drawing instruction sent by an application is received, where the first drawing instruction includes at least one first identifier for indicating a rendering target, where the rendering target is used to cache a rendering result obtained by executing the drawing instruction;

[0055] Applications here can be software that requires the GPU for graphics rendering, such as games and image processing software. These applications generate drawing instructions, such as drawing a shape (such as a triangle or rectangle) or rendering a texture, and send these instructions to the driver through the graphics interface. The driver receives these instructions and performs subsequent processing based on the information in the instructions, generating rendering commands that the GPU can execute, and ultimately sending them to the GPU for graphics rendering.

[0056] A render target (RT) is a memory area used to cache the rendering results obtained after executing a drawing instruction. It is usually one or more buffers, such as color, depth, and other buffers, used to store pixel-level rendering results. When a drawing instruction is executed, the rendering result is stored in the RT bound to the drawing instruction.

[0057] Render target identifiers are used to identify different render targets. In one example, a render target identifier can be a name or a string. These names can be programmer-defined or automatically generated by the system. By specifying these names, an application can tell the driver or GPU which render target it wants to use. Furthermore, render target identifiers can also be resource handles, memory locations, and so on, which are not limited in this disclosure.

[0058] After receiving the first drawing instruction sent by the application, the parameters in the drawing instruction are parsed to obtain the identifier contained in the first drawing instruction. For ease of description, the identifier contained in the first drawing instruction is referred to herein as the first identifier. It should be understood that the terms "first" and "second" in the embodiments of this disclosure are used to distinguish between the objects being described and should not be construed as limiting the order of the objects being described, indicating or implying relative importance, or other limitations.

[0059] In step S12, if the first identifier also exists in the second drawing instruction, and the second identifiers other than the first identifier in the second drawing instruction are set to null values ​​in the first drawing instruction, then the first drawing instruction is applied to be bound to the same render target of the GPU as that of the second drawing instruction, and the GPU is instructed not to perform a write operation on the first render target corresponding to the second identifier when executing the first drawing instruction;

[0060] The second drawing instruction can be an instruction received before the first drawing instruction. When rendering an image frame, the application can break the image frame into multiple small tiles, each of which can contain multiple drawing instructions. Each tile has a high-speed renderer that is responsible for processing all rendering commands within that tile. During the graphics rendering process, the GPU's renderer divides the frame buffer into small tiles, each corresponding to a tile. The renderer then executes all rendering commands within the tile and writes the results back to the frame buffer.

[0061] Each tile has a specific data storage structure (layout) that describes how data is organized in memory, determined by the render objects it contains. If multiple draw commands can share the same layout and have no dependencies on each other, they can be submitted all at once and rendered on the same tile. This batching technique can further improve rendering efficiency.

[0062] Then, after the driver receives the first drawing instruction, if the driver has previously received the second drawing instruction, the driver will check whether the newly received first drawing instruction can share the same data storage structure with the second drawing instruction.

[0063] Specifically, if the rendering targets of the first drawing instruction and the second drawing instruction are the same, it can be considered that the two can share the same data storage structure. In the absence of a mutual dependency relationship (for example, the first drawing instruction does not need to use the rendering result of the second drawing instruction), the instruction set including at least the first drawing instruction and the second drawing instruction can be submitted to the GPU at one time so that the GPU can perform graphics rendering operations.

[0064] The first identifier also exists in the second drawing instruction, and the second identifiers other than the first identifier in the second drawing instruction are set to null values ​​in the first drawing instruction. Specifically, all identifiers in the second drawing instruction include all identifiers in the first drawing instruction, and the identifiers other than the first identifier in the second drawing instruction (referred to as second identifiers for ease of description) are set to null values ​​in the first drawing instruction. For example, if the identifiers in the first drawing instruction draw1 are (RT0, nullptr, RT2, RT3) and the identifiers in the second drawing instruction draw0 are (RT0, RT1, RT2, RT3), then draw0 contains four identifiers, namely RT0, RT1, RT2, and RT3, while draw1 contains three identifiers, namely RT0, RT2, and RT3. Nullptr represents a null value. Therefore, RT1 is the second identifier mentioned above, which is set to null value in draw1.

[0065] In this case, the first drawing instruction can bind the same render target to the GPU as the second drawing instruction, without setting the second identifier RT to a null value in the driver. This allows the first drawing instruction to bind the same render target to the second drawing instruction. In other words, the first drawing instruction and the second drawing instruction can share the same data storage structure, meaning the rendering results from rendering the first and second drawing instructions are organized in the same way in memory. Continuing with the previous example, the first drawing instruction also applies to the render targets (RT0, RT1, RT2, RT3), without setting RT1 to a null value.

[0066] Furthermore, the GPU is instructed not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction. In this way, the GPU does not perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, thereby achieving the effect of setting the second identifier to a null value.

[0067] In step S13, an instruction set including at least the first drawing instruction and the second drawing instruction is submitted to the GPU at one time, so that the GPU performs a graphics rendering operation.

[0068] An instruction set can contain multiple drawing instructions that can share the same data storage structure. An instruction set can be sent to the GPU as a whole to reduce the number of communications between the GPU and the driver and improve rendering efficiency.

[0069] The user mode driver (UMD) in the driver converts the drawing instructions (draw) into rendering commands (command) that the GPU can execute efficiently. The rendering commands are packaged into submission data (submission) and sent to the GPU through the kernel mode driver (KMD).

[0070] After receiving the command, the GPU begins rendering and caches the rendering results in the bound render target. When executing the first drawing instruction, the first render target corresponding to the second identifier is not written to. After rendering a frame of data, the frame of data is displayed on the screen.

[0071] In an embodiment of the present disclosure, after receiving a first drawing instruction sent by an application; if the first identifier in the first drawing instruction also exists in a second drawing instruction, and the second identifier in the second drawing instruction, other than the first identifier, is set to a null value in the first drawing instruction, then the first drawing instruction is applied to be bound to the same render target on the GPU as the second drawing instruction, and the GPU is instructed not to perform a write operation on the first render target corresponding to the second identifier when executing the first drawing instruction. Thus, the render target corresponding to the first drawing instruction is not actually set to a null value, but remains the same as the second drawing instruction. The first drawing instruction and the second drawing instruction can then share the same data storage structure (layout) and be placed in the same instruction set. By submitting the instruction set containing at least the first and second drawing instructions to the GPU at once, the additional overhead caused by the interaction between the GPU driver and the operating system can be reduced compared to submitting the instructions in multiple batches, thereby improving graphics rendering efficiency. Furthermore, the GPU can batch the instruction sets, further improving processing efficiency.

[0072] In one possible implementation, instructing the GPU not to perform a write operation on the rendering target corresponding to the second identifier when executing the first drawing instruction includes: setting a write mask of the first rendering target in the first drawing instruction to a first indicator identifier, where the first indicator identifier is used to instruct the GPU not to perform a write operation on the first rendering target when executing the first drawing instruction.

[0073] The write mask (rtwritemask) is a mask used to control the GPU's writing of rendering results, and is used to specify which rendering targets should be updated by the rendering results. Each rendering target is usually represented by one bit. If this bit is set to the first indicator (for example, set to 0), the corresponding rendering target will not be written; if it is set to the second indicator (for example, set to 1), the corresponding rendering target will be written. If the driver sets the write mask of the first rendering target to the first indicator, it means that during the GPU's execution of the first drawing instruction, the first rendering target will not be written, and can be executed on the same tile as the second drawing instruction without changing the rendering target, thereby improving the efficiency of graphics rendering.

[0074] In an embodiment of the present disclosure, by setting the write mask of the first rendering target in the first drawing instruction to a first indicator, the first indicator is used to instruct the GPU not to perform a write operation on the first rendering target when executing the first drawing instruction. Therefore, when the second indicator is requested to be set to a null value in the first drawing instruction, the GPU is instructed not to perform a write operation on the first rendering target corresponding to the second indicator when executing the first drawing instruction by changing the write mask, so that there is no need to set the first rendering target bound to the GPU by the first drawing instruction to a null value, thereby achieving that the rendering target bound to the GPU by the first drawing instruction is the same as that of the second drawing instruction, so that the first drawing instruction and the second drawing instruction can share the same data storage structure (layout) and can be placed in the same instruction set. Then, by submitting the instruction set containing at least the first drawing instruction and the second drawing instruction to the GPU at one time, compared with submitting them multiple times, the additional overhead caused by the interaction between the GPU driver and the operating system can be reduced, thereby improving the efficiency of graphics rendering.

[0075] The application side does not require any improvements. Even if the application sets the RT to a null value, the driver does not actually set the RT to a null value. This allows the driver to avoid the actual RT switching overhead and reuse the previous rendering state. In addition, to ensure that the RT does not affect the final rendering output, the driver will disable the writing of drawing process data by setting rtwritemask to 0. This allows developers to keep the application logic unchanged without introducing additional performance overhead, making it more friendly to application developers.

[0076] In one possible implementation, the GPU driver continuously receives multiple drawing instructions, where the second drawing instruction is a drawing instruction received before the first drawing instruction. After instructing the GPU not to perform a write operation on a first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes: adding the first drawing instruction to an instruction set containing the second drawing instruction.

[0077] The GPU driver continuously receives drawing commands from the operating system or application. For two consecutive drawing commands, if the latter can share the same data storage structure with the former, the latter can be added to the instruction set of the former. For example, the four consecutive instructions received are: draw0(RT0,RT1,RT2,RT3), draw1(RT0,nullptr,RT2,RT3), draw2(RT0,nullptr,nullptr,RT3), and draw3(RT0,nullptr,nullptr,nullptr). Among these instructions, two adjacent instructions can share the same data storage structure. In this case, after receiving draw1, draw1 can be added to the instruction set of draw0, and the instruction set is now {draw0,draw1}. After receiving draw2, draw2 can be added to the instruction set of draw1, and the instruction set is now {draw0,draw1,draw2}. After receiving draw3, draw3 can be added to the instruction set of draw2, and the instruction set is now {draw0,draw1,draw2,draw3}.

[0078] In an embodiment of the present disclosure, the GPU driver continuously receives multiple drawing instructions, where the second drawing instruction is a drawing instruction received before the first drawing instruction. After instructing the GPU not to perform a write operation on the first render target corresponding to the second identifier when executing the first drawing instruction, the method further includes: adding the first drawing instruction to the instruction set containing the second drawing instruction. This allows the continuously received drawing instructions that share the same data storage structure to be grouped into a single instruction set for simultaneous submission to the GPU. This reduces the overhead associated with interaction between the GPU driver and the operating system, compared to submitting them multiple times, and improves graphics rendering efficiency.

[0079] In one possible implementation, after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes: receiving a third drawing instruction sent by the application; and submitting an instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time, including: submitting the instruction set to the GPU at one time if the third identifier in the third drawing instruction does not exist in the first drawing instruction.

[0080] The third identifier is used to indicate the render target in the third drawing instruction. If the third identifier is not present in the first drawing instruction, the third drawing instruction will need to request a new render target relative to the first drawing instruction. Therefore, the third drawing instruction cannot share the same data storage structure as the first drawing instruction and cannot be added to the instruction set containing the first drawing instruction. In this case, the instruction set containing the first drawing instruction can be submitted to the GPU all at once, avoiding the need to submit drawing instructions with different data storage structures together.

[0081] In one possible implementation, the GPU driver sequentially and continuously receives multiple drawing instructions, where the multiple drawing instructions include the first drawing instruction and the second drawing instruction. Submitting the instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at once includes: if, among any two sequentially adjacent drawing instructions among the multiple drawing instructions, the earlier drawing instruction includes all identifiers of the later drawing instruction, then submitting the multiple drawing instructions to the GPU at once.

[0082] The GPU driver receives multiple drawing instructions in a time sequence, which may include a first drawing instruction and a second drawing instruction, or may include more drawing instructions.

[0083] When the GPU driver needs to submit these multiple consecutively received drawing instructions to the GPU for execution, it will determine whether any two sequentially adjacent drawing instructions meet the condition that the previous drawing instruction contains all the identifiers of the next drawing instruction. If so, the previous drawing instruction of the two adjacent drawing instructions can be regarded as the second drawing instruction, and the next drawing instruction can be regarded as the first drawing instruction. According to the above processing of the first and second drawing instructions, the rendering target applied to the GPU for the first drawing instruction will be kept the same as that of the second drawing instruction. That is, the rendering target applied to the GPU for the next drawing instruction will be kept the same as that of the previous drawing instruction. In this way, the two adjacent instructions can share the same data storage structure, and these multiple drawing instructions can be submitted to the GPU at one time.

[0084] For example, the four consecutive instructions received are: draw0(RT0,RT1,RT2,RT3), draw1(RT0,nullptr,RT2,RT3), draw2(RT0,nullptr,nullptr,RT3), draw3(RT0,nullptr,nullptr,nullptr), where nullptr is empty. Obviously, in this example, between any two adjacent drawing instructions, the previous drawing instruction will contain all the identifiers of the next drawing instruction. Therefore, these four instructions can be submitted to the CPU at one time.

[0085] In an embodiment of the present disclosure, when multiple drawing instructions are received sequentially, if the previous drawing instruction of any two sequentially adjacent drawing instructions contains all the identifiers of the next drawing instruction, the multiple drawing instructions are submitted to the GPU at once. In this way, the rendering target of the GPU to which the next drawing instruction is bound can be kept the same as that of the previous drawing instruction. Then, the two adjacent instructions can share the same data storage structure, and the multiple drawing instructions can be submitted to the GPU at once. Since the number of instruction submissions is reduced, the communication overhead between the CPU and GPU is also correspondingly reduced, which helps to improve rendering performance, reduce rendering latency, and increase frame rate, thereby providing users with a smoother visual experience.

[0086] In one possible implementation, after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes: setting a status flag corresponding to the first rendering target to a first status value, where the first status value is used to indicate that the first rendering target is in a non-write state.

[0087] In order to mark the current state of the first rendering target so that the subsequently received drawing instructions can be accurately written into the corresponding rendering target, this can be achieved by setting a state flag in the driver. When the first rendering target is in a state where it is not written, the state flag corresponding to the first rendering target can be set to a first state value (such as 0 or a specific character). The GPU driver or other related components can quickly identify that this rendering target is currently in a state where it is not written.

[0088] In one possible implementation, the method further includes: when the state flag corresponding to the first rendering target is a first state value, if a third identifier in the third drawing instruction does not exist in the first drawing instruction, setting a write mask of the corresponding rendering target according to the identifier in the third drawing instruction.

[0089] When the first render target is marked as not being written to, the GPU driver checks whether the subsequent drawing instruction (such as the third drawing instruction) involves this render target. If the third identifier (a different identifier from the first identifier) ​​in the third drawing instruction does not exist in the first drawing instruction, it means that the new render target (the render target indicated by the third identifier) ​​needs to be written. At this time, based on the third identifier in the third drawing instruction, the GPU driver will set the write mask of the corresponding render target to ensure that the correct write operation occurs.

[0090] In the disclosed embodiment, by setting status flags and dynamically adjusting the write mask according to the drawing instructions, the GPU driver can more finely control the write operation of each rendering target, thereby adapting to more complex rendering scenarios. By precisely controlling the write operation of each rendering target, the possibility of data overwrite and rendering errors can be reduced, thereby ensuring rendering quality and stability while improving rendering efficiency.

[0091] In a possible implementation, a state flag corresponding to the first rendering target is set to a second state value, where the second state value is used to indicate that the first rendering target is currently in a write-allowed state.

[0092] After setting the write mask of the corresponding rendering target according to the third identifier in the third drawing instruction, the state of the first rendering target in the driver can be changed from not allowing writing to allowing writing, thereby accurately controlling the writing operations of subsequent rendering targets.

[0093] See also Figure 2 , Figure 2A flowchart of a graphics rendering method in an actual application scenario according to an embodiment of the present disclosure is shown. For example, four consecutive instructions are received: draw0(RT0, RT1, RT2, RT3), draw1(RT0, nullptr, RT2, RT3), draw2(RT0, nullptr, nullptr, RT3), draw3(RT0, nullptr, nullptr, nullptr). After receiving draw3(RT0, nullptr, nullptr, nullptr), these four instructions can be put into the same set. Therefore, the status flags of RT1, RT2, and RT3 are all set to 0 to indicate that they are currently in a state where writing is not allowed. If a new drawing instruction draw4 (RT0, RT1, RT2, RT3) is received later, and RT1, RT2, and RT3 in draw4 are not in draw3, then draw0, draw1, draw2, and draw3 need to be submitted at once, and the write masks corresponding to RT1, RT2, and RT3 are reset to the values ​​indicated in draw4, and the status flags of draw4 are all set to 1 to indicate that they are currently in a state where writing is not allowed.

[0094] See also Figure 3 , Figure 3 A flowchart of a graphics rendering method in an actual application scenario according to an embodiment of the present disclosure is shown. When drawing a frame of image, multiple drawing instructions are received. For a received drawing instruction, it is determined whether the instruction is the same as the previous instruction. If the same, the instruction is placed in the instruction set of the previous instruction, and subsequent instructions are continued to be received; if the instruction is different from the previous instruction, it is determined whether the second RT that appeared in the previous instruction is set to a null value in the current instruction, and other first RTs are the same. If not, the instruction set containing the previous instruction is submitted to the GPU, and the write mask and status flag are reset; if so, the instruction is placed in the instruction set of the previous instruction, and the second RT of the instruction is not set to a null value to keep the RT bound to the GPU of the instruction the same as the previous instruction, and the write mask of the second RT of the instruction is set to 0, and the status flag of the second RT is set to 0, and subsequent instructions are continued to be received.

[0095] In one possible implementation, the graphics rendering method can be executed by electronic devices such as terminal devices and servers. The terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. The method can be implemented by a processor calling computer-readable instructions stored in a memory.

[0096] In addition, the present disclosure also provides a graphics rendering device, an electronic device, a computer-readable storage medium, and a program, all of which can be used to implement any graphics rendering method provided by the present disclosure. The corresponding technical solutions and descriptions can be found in the corresponding records in the method section and will not be repeated here.

[0097] Figure 4 A block diagram of a graphics rendering device according to an embodiment of the present disclosure is shown, which is applied to a graphics processor GPU driver, such as Figure 4 As shown, the device 20 includes:

[0098] The instruction receiving unit 21 is configured to receive a first drawing instruction sent by an application, wherein the first drawing instruction includes at least one first identifier for indicating a rendering target, and the rendering target is used to cache a rendering result obtained by executing the drawing instruction;

[0099] an instructing unit 22 configured to, if the first identifier also exists in the second drawing instruction and the second identifiers other than the first identifier in the second drawing instruction are set to null values ​​in the first drawing instruction, bind the first drawing instruction to the same render target of the GPU as that of the second drawing instruction, and instruct the GPU not to perform a write operation on the first render target corresponding to the second identifier when executing the first drawing instruction;

[0100] The submitting unit 23 is configured to submit an instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time, so that the GPU performs a graphics rendering operation.

[0101] In a possible implementation, the instructing unit is configured to set a write mask of the first rendering target in the first drawing instruction to a first indication flag, where the first indication flag is configured to instruct the GPU not to perform a write operation on the first rendering target when executing the first drawing instruction.

[0102] In a possible implementation, the GPU driver receives multiple drawing instructions in sequence and continuously, the second drawing instruction is a drawing instruction received before the first drawing instruction, and the device further includes:

[0103] The aggregation unit is configured to add the first drawing instruction to the instruction set where the second drawing instruction is located.

[0104] In a possible implementation, after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the apparatus further includes:

[0105] a third instruction receiving unit, configured to receive a third drawing instruction sent by an application;

[0106] The submitting unit is configured to submit the instruction set to the GPU at one time when the third identifier in the third drawing instruction does not exist in the first drawing instruction.

[0107] In one possible implementation, the GPU driver sequentially and continuously receives multiple drawing instructions, where the multiple drawing instructions include the first drawing instruction and the second drawing instruction. The submitting unit is configured to submit the multiple drawing instructions to the GPU at once if, among any two sequentially adjacent drawing instructions, the earlier drawing instruction includes all identifiers in the later drawing instruction.

[0108] In a possible implementation, the apparatus further includes: a state setting unit, configured to set a state flag corresponding to the first rendering target to a first state value, where the first state value is used to indicate that the first rendering target is in a non-writing state.

[0109] In one possible implementation, the apparatus further includes: a write mask setting unit configured to, when a state flag corresponding to the first rendering target is a first state value, set a write mask of the corresponding rendering target according to the identifier in the third drawing instruction if the third identifier in the third drawing instruction does not exist in the first drawing instruction.

[0110] In some embodiments, the functions or modules included in the device provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0111] The present disclosure also provides a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0112] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0113] An embodiment of the present disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0114] The electronic device may be provided as a terminal, a server, or other forms of devices.

[0115] Figure 5 FIG1 shows a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 can be provided as a server or a terminal device. Figure 5 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above-described method.

[0116] The electronic device 1900 may further include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (Mac OSX TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open-source Unix-like operating system (FreeBSD TM ) or similar.

[0117] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0118] The present disclosure may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0119] Computer-readable storage media can be a tangible device that can hold and store the instructions used by the instruction execution device. Computer-readable storage media can be, for example, (but not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. Computer-readable storage media used herein is not interpreted as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagated by waveguides or other transmission media (for example, light pulses by fiber optic cables), or electrical signals transmitted by wires.

[0120] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0121] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., utilizing an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions. The electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0122] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0123] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0124] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0125] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0126] The computer program product may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0127] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0128] Those skilled in the art will understand that in the above-mentioned method of the specific implementation method, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0129] If the technical solution of this application involves personal information, the product that applies the technical solution of this application has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing personal information. If the technical solution of this application involves sensitive personal information, the product that applies the technical solution of this application has obtained the individual's separate consent before processing sensitive personal information, and at the same time meets the "explicit consent" requirement. For example, on personal information collection devices such as cameras, a clear and prominent sign is set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that they agree to the collection of their personal information; or on the personal information processing device, when the personal information processing rules are notified by obvious signs / information, the individual's authorization is obtained through pop-up information or by asking the individual to upload their personal information; among which, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0130] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A graphics rendering method, characterized in that: Applicable to graphics processor GPU drivers, including: receiving a first drawing instruction sent by an application, wherein the first drawing instruction includes at least one first identifier for indicating a rendering target, and the rendering target is used to cache a rendering result obtained by executing the drawing instruction; If the first identifier also exists in the second drawing instruction, and second identifiers other than the first identifier in the second drawing instruction are set to null values ​​in the first drawing instruction, applying to bind the first drawing instruction to the same rendering target of the GPU as that of the second drawing instruction, and instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, wherein the first drawing instruction and the second drawing instruction share the same data storage structure, and the second drawing instruction is a drawing instruction received before the first drawing instruction; Submitting an instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time, so that the GPU performs graphics rendering operations on the same tile.

2. The method according to claim 1, characterized in that The instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction includes: The write mask of the first rendering target in the first drawing instruction is set to a first indication flag, where the first indication flag is used to instruct the GPU not to perform a write operation on the first rendering target when executing the first drawing instruction.

3. The method according to claim 1, characterized in that The GPU driver receives multiple drawing instructions in sequence and continuously, and after instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes: The first drawing instruction is added to the instruction set where the second drawing instruction is located.

4. The method according to claim 1, wherein After instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes: receiving a third drawing instruction sent by the application; Submitting the instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time includes: In a case where the third identifier in the third drawing instruction does not exist in the first drawing instruction, the instruction set is submitted to the GPU at one time.

5. The method according to claim 1, wherein The GPU driver sequentially and continuously receives a plurality of drawing instructions, wherein the plurality of drawing instructions include the first drawing instruction and the second drawing instruction; and submitting the instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time, comprising: Among any two drawing instructions that are adjacent in time sequence among the multiple drawing instructions, if the former drawing instruction includes all the identifiers in the latter drawing instruction, the multiple drawing instructions are submitted to the GPU at one time.

6. The method according to claim 1, characterized in that After instructing the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, the method further includes: The state flag corresponding to the first rendering target is set to a first state value, where the first state value is used to indicate that the first rendering target is in a non-writing state.

7. The method according to claim 4, characterized in that The method further comprises: When the state flag corresponding to the first rendering target is a first state value, if the third identifier in the third drawing instruction does not exist in the first drawing instruction, setting a write mask of the corresponding rendering target according to the identifier in the third drawing instruction.

8. A graphics rendering device, characterized in that: Applicable to graphics processor GPU drivers, including: An instruction receiving unit is configured to receive a first drawing instruction sent by an application, wherein the first drawing instruction includes at least one first identifier for indicating a rendering target, and the rendering target is configured to cache a rendering result obtained by executing the drawing instruction; an instructing unit configured to, if the first identifier also exists in a second drawing instruction and a second identifier other than the first identifier in the second drawing instruction is set to a null value in the first drawing instruction, bind the first drawing instruction to the same rendering target of the GPU as the second drawing instruction, and instruct the GPU not to perform a write operation on the first rendering target corresponding to the second identifier when executing the first drawing instruction, wherein the first drawing instruction and the second drawing instruction share the same data storage structure, and the second drawing instruction is a drawing instruction received before the first drawing instruction; The submitting unit is configured to submit an instruction set including at least the first drawing instruction and the second drawing instruction to the GPU at one time, so that the GPU performs a graphics rendering operation on the same tile.

9. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

Images