Display device and driving method thereof

Abstract

There is provided a display device including: a display panel configured to display an image; a gate driving circuit connected to the display panel; a data driving circuit connected to the display panel; and a timing controller configured to control the gate driving circuit and the data driving circuit, in which the data driving circuit senses a gate signal output from the gate driving circuit and controls a data output timing based on an operation of the other device or a signal generated from the other device, and based on the sensed gate signal.

Description

[0001] This case is a divisional application, and its parent case is an application with a filing date of September 28, 2022, application number 202211192679X, and invention name “Display device and driving method of the display device”.

[0002] This application claims priority to Korean Patent Application No. 10-2021-0128016 filed on September 28, 2021. Technical Field

[0003] The present disclosure relates to a display device and a driving method of the display device. Background Art

[0004] As information technology develops, the market for display devices, which are a connection medium between users and information, continues to grow. As a result, the use of display devices such as light emitting display devices (LEDs), quantum dot display devices (QDDs), and liquid crystal display devices (LCDs) continues to increase.

[0005] Each of the above-mentioned display devices includes: a display panel including sub-pixels; a driving unit configured to output a driving signal for driving the display panel; a power supply unit configured to generate power to be supplied to the display panel or the driving unit; etc.

[0006] In each of the display devices, when a driving signal such as a scan signal, a data signal, etc. is supplied to sub-pixels formed in a display panel, an image may be displayed by transmitting light or directly emitting light by selecting a specific sub-pixel. Summary of the invention

[0007] Accordingly, the present disclosure is directed to a display device and a driving method thereof that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0008] The purpose of the embodiment is to automatically correct and optimize the data output timing of the data driving unit based on the interaction between the timing controller and the data driving circuit, so as to improve the driving stability and output accuracy of the data driving circuit.

[0009] Additional advantages, purposes and features of the embodiments will be described in part in the specification. These purposes and other advantages may be realized and obtained through the structures particularly pointed out in the written description, its claims and the drawings.

[0010] Therefore, a display device is provided, comprising: a display panel configured to display an image; a gate driving circuit connected to the display panel; a data driving circuit connected to the display panel; and a timing controller configured to control the gate driving circuit and the data driving circuit, wherein the data driving circuit senses a gate signal output from the gate driving circuit and controls data output timing based on the operation of another device (e.g., another component or another controller) or a signal generated from another device and based on the sensed gate signal.

[0011] The data driving circuit may include at least two sensing terminals connected to two points of a gate line or a dummy gate line located on the display panel to sense a gate signal output from the gate driving circuit.

[0012] At least two sensing terminals may be located at an outermost side of one side and an outermost side of the other side of the data driving circuit.

[0013] The data output timing of the data driving circuit may be controlled based on the gate signal and the gate start pulse applied to the gate driving circuit.

[0014] The data output timing of the data driving circuit may be controlled based on the gate signal and a source output enable signal applied to the data driving circuit.

[0015] The data output timing of the data driving circuit may be controlled by a data output signal based on the gate signal and through an interface coupled between the timing controller and the data driving circuit.

[0016] The data driving circuit may include at least two data driving circuits electrically connected to each other through a delay pulse line for inputting and outputting a pulse including data output delay information of another device or the data driving circuit.

[0017] The data driving circuit may include a signal sensing circuit configured to calculate the logic high start time, logic high end time, and logic high hold time of the gate signal based on the gate signal output from the gate driving circuit, the gate start pulse applied to the gate driving circuit, and the voltage maintained at the same level as the gate high level of the gate signal. For example, the logic high level can be interpreted as the value of a parameter (e.g., voltage) representing a digital signal 1 (on). Therefore, the logic high start time can be interpreted as the time when the digital signal changes to 1, the logic high end time can be interpreted as the time when the digital signal changes from 1, and the logic high hold time can be interpreted as the time when the logic high stays at (e.g., remains at) 1.

[0018] A method for driving a display device is also provided, the display device comprising: a display panel configured to display an image; a gate driving circuit connected to the display panel; a data driving circuit connected to the display panel; and a timing controller configured to control the gate driving circuit and the data driving circuit. The method comprises sensing a gate signal output from the gate driving circuit, calculating a data output delay of the data driving circuit based on the gate signal, and setting a data output timing of the data driving circuit based on the data output delay.

[0019] The data output timing of the data driving circuit can be controlled based on a gate signal and a gate start pulse applied to the gate driving circuit, based on a gate signal and a source output enable signal applied to the data driving circuit, or based on a gate signal and a data output signal through an interface coupled between a timing controller and the data driving circuit.

[0020] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present disclosure includes accompanying drawings to provide a further understanding of the present disclosure, and the accompanying drawings are incorporated into and constitute a part of the present application, illustrate embodiments and together with the description are used to support the claims. In the drawings:

[0022] Figure 1 is a block diagram schematically showing an LED display device, and Figure 2 It is schematically shown Figure 1 The configuration diagram of the sub-pixels shown in ;

[0023] Figure 3A and Figure 3B is a diagram showing an arrangement example of a gate-in-panel type gate driving unit, and Figure 4 and Figure 5 is an exemplary configuration diagram of a device related to a gate-in-panel type gate driving unit;

[0024] Figures 6 to 8 is a diagram schematically showing an automatic correction method of data output timing according to the first embodiment;

[0025] Fig. 9 is an exemplary configuration diagram of a timing controller and a data driving unit according to the first embodiment, and Fig.10 yes Fig. 9 The internal block diagram of the first data driving unit shown;

[0026] Fig.11 This is a partial configuration diagram of a large-size LED display device. Fig.12 It is shown by Fig.11An example diagram of a gate signal sensed by a gate line, and Fig.13 Is used to describe Fig.12 An example diagram of a delay characteristic of a gate signal of a portion of FIG.

[0027] Fig.14 is a first exemplary diagram showing a configuration of a signal sensing unit, Fig.15 is a second exemplary diagram showing a configuration of a signal sensing unit, Fig.16 is a third exemplary diagram showing a configuration of a signal sensing unit, and Fig.17 is a fourth exemplary diagram showing a configuration of a signal sensing unit;

[0028] Fig.18 is an exemplary diagram showing a data driving unit including a timing setting unit according to a second embodiment, Fig.19 is an exemplary configuration diagram of a data driving unit according to the second embodiment, Fig. 20 yes Fig.19 The internal block diagram of the first data driving unit is shown in FIG. Fig.21 It is a partial configuration diagram of a large-size LED display device;

[0029] Fig. 22 is a diagram for describing a driving method of an LED display device according to a second embodiment;

[0030] Fig.23 is a diagram for describing a driving method of an LED display device according to a third embodiment;

[0031] Fig.24 is a diagram for describing a driving method of an LED display device according to a fourth embodiment;

[0032] Fig.25 is an exemplary diagram showing a data driving unit including a timing setting unit according to a fifth embodiment, Fig.26 is an exemplary configuration diagram of data driving units connected by delay pulse lines according to a fifth embodiment, Fig. 27 yes Fig.26 The internal block diagram of the first data driving unit is shown in FIG. Fig.28 It is a partial configuration diagram of a large-size LED display device;

[0033] Fig.29 is a diagram for describing a driving method of an LED display device according to a fifth embodiment;

[0034] Fig.30 is a diagram for describing a driving method of an LED display device according to a sixth embodiment;

[0035] Fig.31is an exemplary diagram showing an adjustment method of output timing applicable to the second embodiment, the third embodiment and the sixth embodiment, Fig.32 is an exemplary diagram showing an adjustment method of output timing applicable to the fourth embodiment and the sixth embodiment, Fig.33 is an exemplary diagram showing an adjustment method of output timing applicable to the first to sixth embodiments, and Fig.34 : is a diagram showing an example of an adjustment method of output timing applicable to the fifth embodiment and the sixth embodiment. DETAILED DESCRIPTION

[0036] Reference will now be made in detail to the preferred embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0037] The display device according to the present disclosure may be implemented as a television, an image player, a personal computer (PC), a home theater, a vehicle electronic device, a smart phone, etc., but is not limited thereto. For example, the display device according to the present disclosure may be implemented as an LED display device (which may include an OLED display device), a QDD display device, an LCD display device, etc. However, hereinafter, for ease of description, an LED (e.g., an LED display device) that directly emits light based on an inorganic light emitting diode or an organic light emitting diode is given as an example.

[0038] Figure 1 is a block diagram schematically showing an LED display device, and Figure 2 It is schematically shown Figure 1 The sub-pixel configuration diagram is shown in .

[0039] like Figure 1 and Figure 2 As shown, the LED display device may include an image supply unit (circuit) 110, a timing controller 120, a gate driving unit (circuit) 130, a data driving unit (circuit) 140, a display panel 150, a power supply unit (circuit) 180, and the like.

[0040] The image supply unit (group or host system) 110 may output various driving signals and image data signals supplied from the outside or stored in an internal memory. The image supply unit 110 may supply data signals and various driving signals to the timing controller 120.

[0041] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the gate driving unit 130, a data timing control signal DDC for controlling the operation timing of the data driving unit 140, various synchronization signals (a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync), etc. The timing controller 120 may supply the data signal DATA supplied from the image supply unit 110 to the data driving unit 140 together with the data timing control signal DDC. The timing controller 120 may be formed as an integrated circuit (IC) and mounted on a printed circuit board, however, the timing controller 120 is not limited thereto.

[0042] The gate driving unit 130 may output a gate signal (or a scan signal) in response to a gate timing control signal GDC supplied from the timing controller 120. The gate driving unit 130 may supply the scan signal to the sub-pixels included in the display panel 150 through the gate lines GL1 to GLm. The gate driving unit 130 may be formed as an IC, or may be directly formed on the display panel 150 using a gate-in-panel method, but is not limited thereto.

[0043] The data driving unit 140 may sample and latch the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, convert the digital data signal into an analog data voltage based on the gamma reference voltage, and output the analog data voltage. The data driving unit 140 may supply the data voltage to the sub-pixels included in the display panel 150 through the data lines DL1 to DLn. The data driving unit 140 may be formed as an IC and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

[0044] The power supply unit 180 may generate a first power supply having a high potential and a second power supply having a low potential based on an external input voltage supplied from the outside, and output the first power supply and the second power supply through a first power supply line EVDD and a second power supply line EVSS. In addition to the first power supply and the second power supply, the power supply unit 180 may also generate and output a voltage required to drive the gate driving unit 130 (e.g., a gate voltage including a gate high voltage and a gate low voltage) or a voltage required to drive the data driving unit 140 (including a drain voltage and a half-drain voltage).

[0045] The display panel 150 may display an image in response to a driving signal including a gate signal and a data voltage, a first power source, a second power source, etc. The sub-pixels of the display panel 150 directly emit light. The display panel 150 may be manufactured based on a rigid or flexible substrate (e.g., glass, silicon, polyimide, etc.). In addition, the sub-pixels that emit light may include pixels including red, green, and blue or pixels including red, green, blue, and white.

[0046] For example, one sub-pixel SP may be connected to a first data line DL1, a first gate line GL1, a first power line EVDD, and a second power line EVSS, and may include a pixel circuit including a switching transistor, a driving transistor, a capacitor, an organic light emitting diode (OLED), etc. Since the sub-pixel SP used in the LED display device directly emits light, the circuit configuration is complex, for example, it may include a large number of transistors and connections between them. In addition, there are various compensation circuits to compensate for the degradation of the OLED that emits light and the driving transistor that supplies the driving current to the OLED. Therefore, in Figure 1 , note that the sub-pixels SP are schematically shown in the form of blocks.

[0047] Meanwhile, in the above description, the timing controller 120, the gate driving unit 130, the data driving unit 140, etc. have been described as separate components. However, according to the implementation method of the LED display device, one or more of the timing controller 120, the gate driving unit 130, and the data driving unit 140 may be integrated into one IC.

[0048] Figure 3A and Figure 3B is a diagram showing an arrangement example of a gate-in-panel type gate driving unit, and Figure 4 and Figure 5 is an exemplary configuration diagram of devices related to a gate-in-panel type gate driving unit.

[0049] like Figure 3A and 3B As shown, the intra-panel gate type gate driving units 130a and 130b are disposed in the non-display area NA of the display panel 150. Figure 3A As shown, the gate driving units 130a and 130b may be disposed at the left and right portions of the non-display area NA in the display panel 150. Alternatively, as shown in FIG. Figure 3B As shown, the gate driving units 130 a and 130 b may be disposed at upper and lower portions of the non-display area NA in the display panel 150 .

[0050] The gate driving units 130a and 130b are shown and described as being disposed in the non-display area NA located on the left and right sides or upper and lower sides of the display area AA. However, the scan driving units 130a and 130b may be disposed on one of the left, right, upper or lower sides.

[0051] like Figure 4As shown, the in-panel gate type gate driving unit 130 may include a shift register 131 and a level shifter 135. The level shifter 135 may generate a clock signal Clks and a start signal Vst (e.g., an in-panel gate start signal such as a gate start pulse) based on the signal and voltage output from the timing controller 120 and the power supply unit 180. The clock signal Clks may be generated in the form of K (K is an integer greater than or equal to 2) different phases, such as two phases, four phases, and eight phases.

[0052] The shift register 131 can operate based on the signals Clks and Vst output from the level shifter 135, and output gate signals Gate[1] to Gate[m] that can turn on or off the transistors formed on the display panel. The shift register 131 can be formed as a thin film on the display panel using a gate-in-panel method. Therefore, Figure 3A and Figure 3B The gate driving units 130 a and 130 b shown in FIG. 1 may correspond to the shift register 131 .

[0053] like Figure 4 and Figure 5 As shown, unlike the shift register 131 , the level shifter 135 may be independently formed as an IC or may be included in the power supply unit 180 , however this is merely an example configuration and the present disclosure is not limited thereto.

[0054] Figures 6 to 8 is a diagram for schematically describing the automatic correction method of data output timing according to the first embodiment.

[0055] like Figures 6 to 8 As shown, in the LED display device according to the present disclosure, the data output timing of the data driving unit 140 can be automatically corrected based on the interactive work (i.e., collaboration or interaction) between the timing controller 120 (T-CON) and the data driving unit 140 (SD-IC). Specifically, the data driving unit 140 (SD-IC) can refer to the work of another device or the signal generated from the other device and analyze it, and sense the gate signal through the gate line, which enables the data driving unit 140 to automatically control the data output timing (described below). Here, the term "another device" can be understood to mean another component of the controller, for example. For example, the other components can be the following components: the data driving circuit 140, another data driving circuit 140B of the display device, the timing controller, the timing setting unit 128 of the timing controller 120; the timing setting unit 128 of the data driving circuit 140; the timing control unit 145 of the data driving unit 140, the timing setting unit 128 of another data driving circuit 140B; or the timing control unit 145 of another data driving circuit 140B.

[0056] Although the embodiments describe a data driving circuit that senses a gate signal and a delay in the gate signal, it is understood that another component or IC may be dedicated to performing the sensing. Therefore, in some embodiments, the gate signal is sensed by a component other than the data driving circuit. Another component may include two sensing terminals that operate in the same manner as the sensing terminals of the data driving unit described herein. The sensing terminals are arranged to sense the gate signal at a position corresponding to the position of the data driving circuit.

[0057] First, a gate start pulse GSP may be applied to the gate driving unit GD-IC or GIP and the data driving unit 140 (SD-IC) (S110). In this case, the gate start pulse GSP may be implemented to be simultaneously transmitted to the gate driving unit GD-IC and the data driving unit 140 (SD-IC).

[0058] Next, a control operation may be performed so that the data driving unit 140 (SD-IC) senses a dummy gate line that transmits a dummy gate signal or a gate line that transmits a gate signal (S120). The execution of the control operation causes a sensing signal timing delay of the gate signal or the dummy gate signal. In this case, for example, since the dummy gate line does not cause an RC deviation caused by the connection of the sensing line, the data driving unit 140 (SD-IC) may be implemented to sense the dummy gate line, which may increase driving stability.

[0059] Next, a control operation may be performed such that the data driving unit 140 (SD-IC) calculates a data output delay based on a sensed signal timing delay (hereinafter, referred to as a delay characteristic) using the sensed gate signal ( S130 ).

[0060] Next, the data output timing and the delay timing of the data driving unit 140 (SD-IC) may be set based on the delay of the data output ( S140 ).

[0061] Next, the data output timing of the data driving unit 140 may be automatically corrected according to the set data output timing and delay timing ( S150 ).

[0062] In the first embodiment, as an example, the timing controller 120 (T-CON) and the data driving unit 140 (SD-IC) are implemented as separate ICs. Therefore, when the timing controller 120 (T-CON) and the data driving unit 140 (SD-IC) are implemented as separate ICs, the data driving unit 140 can sense the gate signal transmitted by the dummy gate line that transmits the dummy gate signal or the gate line that transmits the gate signal, etc., to provide gate line timing information (i.e., the timing characteristics of the gate signal to be described below, such as TDR (T_Delay Rising), TDF (T_Delay Falling), THS (T_High Start), THE (T_High End), etc.). In addition, the timing controller 120 can provide data output timing information for automatically correcting the data output timing of the data driving unit 140 based on the gate line timing information transmitted from the data driving unit 140.

[0063] According to the above method, the data output timing of the data driving unit 140 can be automatically corrected in response to the gate signal delay. Figure 8 The graph of shows an example of gate signal delay at various positions of the gate line.

[0064] Hereinafter, the first embodiment will be described in more detail. However, in the following description, as an example, the data driving unit senses the dummy gate line to provide the gate line timing information.

[0065] Fig. 9 is an exemplary configuration diagram of a timing controller and a data driving unit according to the first embodiment, and Fig.10 yes Fig. 9 An internal block diagram of the first data driving unit is shown.

[0066] like Fig. 9 As shown, the first data driving unit 140A and the second data driving unit 140B can be electrically connected to the gate start pulse line GSPL and the gate line (or dummy gate line) DGL, wherein the gate start pulse GSP is transmitted through the gate start pulse line GSPL and the gate signal is transmitted through the gate line (or dummy gate line) DGL.

[0067] The sensing terminal of the first data driving unit 140A can be connected to the first sensing point SENP1 of the gate line DGL and the second sensing point SENP2 separated from the first sensing point SENP1. In addition, the sensing terminal of the second data driving unit 140B can be connected to the third sensing point SENP3 of the gate line DGL and the fourth sensing point SENP4 separated from the third sensing point SENP3. The sensing terminals described herein are described as sensing terminals of the first data driving unit 140A and sensing terminals of the second data driving unit 140B. However, it can be understood that, alternatively, a part or all of the sensing terminals (e.g., at least two sensing terminals) can be connected to a separate component of the display device. For example, a part or all of the sensing terminals can be connected to another IC other than the data driving unit, and the other IC can act as an intermediate component between the gate line DGL and the data driving units 140A, 140B and can relay the sensing signal from the terminal to the data driving unit.

[0068] As can be seen from the accompanying drawings, the data driving units 140A and 140B can receive a gate start pulse to determine the delay characteristics of the sensed gate signal, and based on at least two sensing terminals (e.g., corresponding to the position) respectively set at the outermost part on the left and the outermost part on the right, sense the gate signal output from the gate driving unit. The outermost part on the left and the outermost part on the right can be the outermost part of a specific data driving unit (e.g., the first data driving unit 140A or the second data driving unit 140B). Alternatively, at least two sensing terminals can be located at the outermost side of one side and the outermost side of the other side (i.e., both ends) of the data driving units 140A and 140B. In this way, the distance between the sensing points on the gate line (or dummy gate line) is maximized, and the sensing accuracy of the gate signal is improved.

[0069] The data driving units 140A and 140B may transmit gate line timing information provided based on the gate start pulse and the sensed gate signal to the timing controller 120 through the gate line timing lines GLT.

[0070] The timing controller 120 may transmit data output timing information provided based on the timing information (gate line timing) to the data driving units 140A and 140B through the data output timing line DOT.

[0071] like Fig.10As shown, the first data driving unit 140A may include a serial-parallel controller, a shift register, a latch, a digital-to-analog conversion unit (circuit) DAC, a multi-channel output unit (circuit) Multi-channel Output, a first signal sensing unit (circuit) SENC1, a second signal sensing unit (circuit) SENC2, a timing control unit Timing Control (also referred to as a controller or timing control), an amplification unit (circuit) G / A, an analog-to-digital conversion unit (circuit) ADC, a sampling circuit unit (circuit) Sample Circuit, a signal transmission unit (circuit) TX, etc. The second data driving unit 140B may have the same configuration as the first data driving unit 140A.

[0072] The serial-parallel controller may be configured to perform a function of controlling a shift register and a latch to convert a data signal of a serial system applied from the outside into a parallel system.

[0073] The shift register and the latch may be configured to perform a function of converting a data signal applied in a serial system into a parallel system and storing the data signal in response to a control of the serial-parallel controller.

[0074] The digital-to-analog conversion unit DAC may be configured to perform a function of converting a digital data signal of a parallel system output from the latch into an analog data voltage. The multi-channel output unit Multi-channel Output may be configured to perform a function of outputting an analog data voltage to the data lines DL1 to DLn.

[0075] The timing control unit Timing Control may be configured to perform a function of controlling operation timings of devices included in the first data driving unit 140A.

[0076] The sampling circuit unit Sample Circuit may be configured to perform a function of sensing and sampling the characteristics of the device included in the sub-pixel through a reference line set together with the data line. The amplification unit G / A may be configured to perform a function of amplifying the sampled value output from the sampling circuit unit Sample Circuit. The analog-to-digital conversion unit ADC may be configured to perform a function of converting the analog sampled value output from the amplification unit G / A into a digital sampled value. The signal transmission unit TX may be configured to perform a function of transmitting the digital sampled value to the timing controller.

[0077] The amplification unit G / A, the analog-to-digital conversion unit ADC, the sampling circuit unit Sample Circuit, and the signal transmission unit TX are components for compensating elements (eg, a driving transistor, an organic light emitting diode, etc.) included in a subpixel and may be omitted.

[0078] The first signal sensing unit SENC1 and the second signal sensing unit SENC2 may be configured to perform a function of sensing a gate signal through a gate line and providing and outputting gate line timing information. The first signal sensing unit SENC1 may be configured to sense a first point of the gate line by connecting to a first sensing terminal SENT1 of the first sensing line, and the second signal sensing unit SENC2 may be configured to sense a second point of the gate line by connecting to a second sensing terminal SENT2 of the second sensing line.

[0079] Hereinafter, an LED display device (eg, a large-sized LED display device) including four data driving units and one timing controller and implemented so that gate signals are applied from the left and right sides will be described as an example.

[0080] Fig.11 It is a partial configuration diagram of LED display equipment. Fig.12 It is shown by Fig.11 An example diagram of a gate signal sensed by a gate line, and Fig.13 Is used to describe Fig.12 An example diagram of the delay characteristics of a portion of a gate signal.

[0081] like Figures 11 to 13 As shown, the LED display device may include at least four data driving units 140A to 140D. The first data driving unit 140A and the second data driving unit 140B may apply data signals to a left display area relative to a center line of the display panel, and the third data driving unit 140C and the fourth data driving unit 140D may apply data signals to a right display area relative to the center line of the display panel.

[0082] A dummy gate line DGL transmitting the gate signals Gate L and Gate R and a gate start pulse line GSPL transmitting the gate start pulse GSP may be disposed in a display region or a non-display region of the display panel.

[0083] The first to fourth data driving units 140A to 140D may be connected in common to the gate start pulse line GSP. The first data driving unit 140A may sense the first side gate signal Gate L from the first and second points of the dummy gate line DGL. The second data driving unit 140B may sense the first side gate signal Gate L from the third and fourth points of the dummy gate line DGL. The third data driving unit 140C may sense the second side gate signal Gate R from the fifth and sixth points of the dummy gate line DGL. The fourth data driving unit 140D may sense the second side gate signal Gate R from the seventh and eighth points of the dummy gate line DGL.

[0084] When a portion of the first data driving unit 140A is representatively examined, the first signal sensing unit SENC1 may include a gate signal sensing unit (Gate Sensing) 141 receiving the first sensing signal SEN1 and a timing counter unit (Timing Counter) 143 receiving the gate start pulse GSP. The gate signal sensing unit 141 may be configured to perform a function of sensing the gate signal of each point on the gate line DGL. The timing counter unit 143 may be configured to perform a function of counting the start time and the end time of the gate start pulse GSP.

[0085] The dummy gate line DGL may simultaneously transmit a first (left) gate signal Gate L outputted from a gate driving unit disposed in a first (left) non-display area and a second (right) gate signal Gate R outputted from a gate driving unit disposed in a second (right) non-display area.

[0086] However, referring to Fig.12 and Fig.11 , starting from the input point ([1]) to which the first side gate signal Gate L is applied, the delay characteristics of the gate signal may deteriorate (i.e., distorted or delayed) toward the first point ([3]), the second point ([4]), the third point ([5]), and the fourth point ([6]). Conversely, starting from the input point ([2]) to which the second side gate signal Gate R is applied, the delay characteristics of the gate signal may deteriorate toward the eighth point (

[10] ), the seventh point ([9]), the sixth point ([6]), and the fifth point ([7]). That is, the fourth point ([6]) farthest from the input point ([1]) to which the first side gate signal Gate L is applied and the fifth point ([7]) farthest from the input point ([2]) to which the second side gate signal Gate R is applied may be the points where the delay (and / or distortion) characteristics of the gate signal are the worst (i.e., the largest or most obvious).

[0087] Refer to Figure 11-13 , it can be seen that the gate signal sensed from the first point ([3]) may have a delay characteristic compared to the input point ([1]) to which the first side gate signal Gate L is applied. The second side gate signal Gate R applied from the side opposite to the first side gate signal Gate L may have the same characteristic. In this article, the first point ([3]) is referenced only for exemplary purposes, and the same or similar delay characteristics may exist in the gate signal sensed at any other point. However, the delay characteristics sensed at other points may have different values ​​and sizes.

[0088] Factors that may determine the delay characteristics of the gate signal include TDR (T_Delay Rising), TDF (T_Delay Falling), THS (T_High Start), THE (T_High End), etc., which will be described below.

[0089] TDR may be a factor for determining the time at which the gate signal at the first point ([3]) rises from logic low (L) to logic high (H) after a delay time compared to the logic high start time of the gate signal at the input point ([1]). TDF may be a factor for determining the time at which the gate signal at the first point ([3]) falls from logic high (H) to logic low (L) after a delay time compared to the logic low start time of the gate signal at the input point ([1]). THS may be a factor for determining the logic high (H) start time of the gate signal at the first point ([3]), and THE may be a factor for determining the logic high (H) end time of the gate signal at the first point ([3]).

[0090] In addition, TR can be a factor for determining the time required for the gate signal at the first point ([3]) to rise from logic low (L) to logic high (H), THW can be a factor for determining the logic high (H) holding time (or pulse width) of the gate signal at the first point ([3]), and TF can be a factor for determining the time required for the gate signal at the first point ([3]) to fall from logic high (H) to logic low (L).

[0091] Therefore, when the gate start pulse GSP indicating the start of output of the gate signal is applied and the gate signal Gate is sensed from a plurality of points, the delay characteristic of the gate signal may be found.

[0092] Therefore, it can be understood that the first signal sensing unit SENC1 includes a gate signal sensing unit 141 that can sense the gate signal of each point and a timing counter unit 143 that can sense the gate start pulse. Therefore, the first signal sensing unit SENC1 can count the start time and the end time of the gate start pulse GSP. In addition, it can be understood that the timing controller 120 includes a timing setting unit 128, and the timing setting unit 128 is used to provide data output timing information Data OutputTiming to automatically correct the data output timing of the data driving unit 140 based on the delay characteristics of the gate signal. For example, it can be based on THS and THE (or THW) or the like or Fig.13 to correct the data output timing by taking into account any other characteristics shown in order to determine the delay characteristics of the gate signal.

[0093] Hereinafter, a signal sensing unit (eg, Fig.11 Various examples of the signal sensing unit SENC1).

[0094] Fig.14 is a first exemplary diagram showing a configuration of a signal sensing unit, Fig.15 is a second exemplary diagram showing a configuration of a signal sensing unit, Fig.16 is a third exemplary diagram showing a configuration of a signal sensing unit, and Fig.17 is a fourth example diagram showing the configuration of the signal sensing unit.

[0095] like Fig.14 As shown, the signal sensing units (circuits) SENC1 and SENC2 may include a first comparator CMP1, a second comparator CMP2, and a third comparator CMP3, and the timing counter unit (circuit) 143 may include a first counter unit CNT1 and a second counter unit CNT2. That is, each of the first signal sensing unit SENC1 and the second signal sensing unit SENC2 may include three comparators and two counters.

[0096] The first comparator CMP1 may have a non-inverting terminal (+) connected to a sensing line SENL, an inverting terminal (-) connected to a reference line REFL, and an output terminal connected to a first input terminal of a first counter unit CNT1. The reference line REFL may be connected to a voltage source capable of maintaining a level that is the same as a gate high level of a gate signal. The output of the first comparator CMP1 may be used as a signal capable of generating a trigger (Positive Edge of Sensing Line Triggered) at a rising edge of a sensing line. As used herein, a rising edge of a sensing line may be interpreted as a time when a signal in a sensing line transitions from a logic low to a logic high or from a cutoff signal to a conduction signal.

[0097] The second comparator CMP2 may have an inverting terminal (-) connected to the sensing line SENL, a non-inverting terminal (+) connected to the reference line REFL, and an output terminal connected to the first input terminal of the second counter unit CNT2. The output of the second comparator CMP2 may be used as a signal capable of generating a trigger (Negative Edge of Sensing Line Triggered) at the falling edge of the sensing line. As used herein, the falling edge of the sensing line may be interpreted as indicating the time when the signal in the sensing line changes from a logic high to a logic low or from a conduction signal to a cutoff signal.

[0098] The third comparator CMP3 may have an inverting terminal (-) connected to the reference line REFL, a non-inverting terminal (+) connected to the gate start pulse line GSPL, and an output terminal connected to the second input terminal of the first counter unit CNT1 and the second input terminal of the second counter unit CNT2. The output of the third comparator CMP3 may be used as a signal capable of generating a trigger (Positive Edge of GSP Triggered) at the rising edge of the gate start pulse.

[0099] The first counter unit CNT1 may generate and output the signal THS for determining a logic high start time of the gate signal using a method of starting counting based on the output of the third comparator CMP3 and suspending counting based on the output of the first comparator CMP1 .

[0100] The second counter unit CNT2 may generate and output the signal THE for determining the logic high end time of the gate signal using a method of starting counting based on the output of the third comparator CMP3 and suspending counting based on the output of the second comparator CMP2 .

[0101] like Fig.15 As shown, the gate signal sensing unit 141 may include a first comparator CMP1, a second comparator CMP2, and a third comparator CMP3, and the timing counter units CNT1 and CNT2 may include a first counter unit CNT1 and a second counter unit CNT2. That is, each of the first signal sensing unit SENC1 and the second signal sensing unit SENC2 may include three comparators and two counters.

[0102] The first comparator CMP1 may have a non-inverting terminal (+) connected to the sensing line SENL, an inverting terminal (-) connected to the reference line REFL, and an output terminal connected to the first input terminal of the first counter unit CNT1 and the second input terminal of the second counter unit CNT2. The reference line REFL may be connected to a voltage source capable of maintaining the same level as the gate high level of the gate signal. The output of the first comparator CMP1 may be used as a signal capable of generating a trigger at the rising edge of the sensing line (Positive Edge of Sensing Line Triggered).

[0103] The second comparator CMP2 may have an inverting terminal (-) connected to the sensing line SENL, a non-inverting terminal (+) connected to the reference line REFL, and an output terminal connected to the first input terminal of the second counter unit CNT2. The output of the second comparator CMP2 may be used as a signal capable of generating a trigger at a falling edge of the sensing line (Negative Edge of Sensing Line Triggered).

[0104] The third comparator CMP3 may have an inverting terminal (-) connected to the reference line REFL, a non-inverting terminal (+) connected to the gate start pulse line GSPL, and an output terminal connected to the second input terminal of the first counter unit CNT1. The output of the third comparator CMP3 may be used as a signal capable of generating a trigger (PositiveEdge of GSP Triggered) at the rising edge of the gate start pulse.

[0105] The first counter unit CNT1 may generate and output the signal THS for determining a logic high start time of the gate signal using a method of starting counting based on the output of the third comparator CMP3 and suspending counting based on the output of the third comparator CMP3 .

[0106] The second counter unit CNT2 may generate and output a signal THW for determining a logic high (H) holding time (or pulse width) of a gate signal using a method of starting counting based on an output of the first comparator CMP1 and pausing counting based on an output of the second comparator CMP2 .

[0107] like Fig.16 As shown, the gate signal sensing unit 141 may include a first comparator CMP1, a second comparator CMP2, a third comparator CMP3 and an analog-to-digital conversion unit ADC, and the timing counter units CNT1 and CNT2 may include a first counter unit CNT1 and a second counter unit CNT2. That is, the first signal sensing unit SENC1 and the second signal sensing unit SENC2 may include an analog-to-digital conversion unit, three comparators and two counters.

[0108] The analog-to-digital conversion unit ADC may have an input terminal connected to the sensing line SENL and an output terminal connected to the non-inverting terminal (+) of the first comparator CMP1 and the inverting terminal (-) of the second comparator CMP2. The analog-to-digital conversion unit ADC may output 0 or 1 corresponding to the logic state of the gate signal.

[0109] The first comparator CMP1 may have a non-inverting terminal (+) connected to the output terminal of the analog-to-digital conversion unit ADC, an inverting terminal (-) connected to the threshold voltage line THL, and an output terminal connected to the first input terminal of the first counter unit CNT1. The threshold voltage line THL may be connected to a device capable of applying a signal equal to a logic high 1. The output of the first comparator CMP1 may be used as a signal capable of generating a trigger (Positive Edge of SensingLine Triggered) at a rising edge of a sensing line.

[0110] The second comparator CMP2 may have an inverting terminal (-) connected to the output terminal of the analog-to-digital conversion unit ADC, a non-inverting terminal (+) connected to the threshold voltage line THL, and an output terminal connected to the first input terminal of the second counter unit CNT2. The output of the second comparator CMP2 may be used as a signal capable of generating a trigger (Negative Edge of Sensing Line Triggered) at a falling edge of the sensing line.

[0111] The third comparator CMP3 may have an inverting terminal (-) connected to the reference line REFL, a non-inverting terminal (+) connected to the gate start pulse line GSPL, and an output terminal connected to the second input terminal of the first counter unit CNT1 and the second input terminal of the second counter unit CNT2. The output of the third comparator CMP3 may be used as a signal capable of generating a trigger (Positive Edge of GSP Triggered) at the rising edge of the gate start pulse.

[0112] The first counter unit CNT1 may generate and output a signal TADC obtained by digitizing a gate signal using a method of starting counting based on an output of the third comparator CMP3 and pausing counting based on an output of the first comparator CMP1 .

[0113] The second counter unit CNT2 may generate and output the signal THE for determining the logic high end time of the gate signal using a method of starting counting based on the output of the third comparator CMP3 and suspending counting based on the output of the second comparator CMP2 .

[0114] like Fig.17 As shown, the gate signal sensing unit 141 may include a first comparator CMP1, a second comparator CMP2, a third comparator CMP3, and an analog-to-digital conversion unit ADC, and the timing counter units CNT1 and CNT2 may include a first counter unit CNT1 and a second counter unit CNT2. That is, the first signal sensing unit SENC1 and the second signal sensing unit SENC2 may include an analog-to-digital conversion unit, three comparators, and two counters.

[0115] The analog-to-digital conversion unit ADC may have an input terminal connected to the sensing line SENL and an output terminal connected to the non-inverting terminal (+) of the first comparator CMP1 and the inverting terminal (-) of the second comparator CMP2. The analog-to-digital conversion unit ADC may output 0 or 1 corresponding to the logic state of the gate signal.

[0116] The first comparator CMP1 may have a non-inverting terminal (+) connected to the output terminal of the analog-to-digital conversion unit ADC, an inverting terminal (-) connected to the threshold voltage line THL, and an output terminal connected to the first input terminal of the first counter unit CNT1 and the second input terminal of the second counter unit CNT2. The threshold voltage line THL may be connected to a device capable of applying a signal equal to a logic high 1. The output of the first comparator CMP1 may be used as a signal capable of generating a trigger (Positive Edge of Sensing Line Triggered) at a rising edge of a sensing line.

[0117] The second comparator CMP2 may have an inverting terminal (-) connected to the output terminal of the analog-to-digital conversion unit ADC, a non-inverting terminal (+) connected to the threshold voltage line THL, and an output terminal connected to the first input terminal of the second counter unit CNT2. The output of the second comparator CMP2 may be used as a signal capable of generating a trigger (Negative Edge of Sensing Line Triggered) at a falling edge of the sensing line.

[0118] The third comparator CMP3 may have an inverting terminal (-) connected to the reference line REFL, a non-inverting terminal (+) connected to the gate start pulse line GSPL, and an output terminal connected to the second input terminal of the first counter unit CNT1 and the second input terminal of the second counter unit CNT2. The output of the third comparator CMP3 may be used as a signal capable of generating a trigger (Positive Edge of GSP Triggered) at the rising edge of the gate start pulse.

[0119] The first counter unit CNT1 may generate and output a signal TADC obtained by digitizing a gate signal using a method of starting counting based on an output of the third comparator CMP3 and pausing counting based on an output of the first comparator CMP1 .

[0120] The second counter unit CNT2 may generate and output a signal THW for determining a logic high (H) holding time (or pulse width) of a gate signal using a method of starting counting based on an output of the first comparator CMP1 and pausing counting based on an output of the second comparator CMP2 .

[0121] Hereinafter, a description will be given of a second embodiment in which a timing setting unit for providing data output timing information and the like are included in a data driving unit.

[0122] Fig.18 is an exemplary diagram showing a data driving unit including a timing setting unit according to a second embodiment, Fig.19is an exemplary configuration diagram of a data driving unit according to the second embodiment, Fig. 20 yes Fig.19 The internal block diagram of the first data driving unit is shown in FIG. Fig.21 It is a partial configuration diagram of an LED display device (eg, a large-size LED display device).

[0123] like Fig.18 As shown, the data driving unit 140 may further include a timing setting unit (Timing Setting) for providing data output timing information to automatically correct the data output timing of the data driving unit 140 based on the gate line timing information transmitted from the data driving unit, which is different from the first embodiment of the timing setting unit for this purpose in the timing controller 120. Fig.19 As shown, even if a timing setting unit (Timing Setting) and the like are further included, the first data driving unit 140A and the second data driving unit 140B can also be electrically connected to the gate line (or dummy gate line) DGL, and the gate signal is transmitted through the gate line (or dummy gate line) DGL together with the gate start pulse line GSPL that transmits the gate start pulse GSP.

[0124] like Fig. 20 As shown, as in the first embodiment, the first data driving unit 140A may include a serial-parallel controller, a shift register, a latch, a digital-to-analog conversion unit DAC, a multi-channel output unit Multi-channel Output, a first signal sensing unit SENC1, a second signal sensing unit SENC2, a controller (e.g., a timing control unit) Timing Control, an amplification unit G / A, an analog-to-digital conversion unit ADC, a sampling circuit unit Sample Circuit, a signal transmission unit (circuit) TX, etc. However, unlike the first embodiment, the first data driving unit 140A may include a timing setting unit (TimingSetting). Fig. 20 In the illustrated embodiment, the second data driving unit 140B may have the same configuration as the first data driving unit 140A.

[0125] like Fig.21 As shown, when implemented as a large-size LED display device, as in the first embodiment, at least four data driving units 140A to 140D may be included. The first data driving unit 140A and the second data driving unit 140B may apply data signals to the left display area relative to the center line of the display panel, and the third data driving unit 140C and the fourth data driving unit 140D may apply data signals to the right display area relative to the center line of the display panel.

[0126] Like the first embodiment, the first signal sensing unit SENC1 may include a gate signal sensing unit (Gate Sensing) 141 receiving the first sensing signal SEN1 and a timing counter unit (TimingCounter) 143 receiving the gate start pulse GSP. In addition, the second signal sensing unit SENC1 may have the same configuration as the first signal sensing unit SENC1.

[0127] Hereinafter, a description will be given of a driving method of the LED display device according to the second embodiment.

[0128] Fig. 22 1 is a diagram for describing a driving method of an LED display device according to a first embodiment and a second embodiment. Fig. 22 In the description, it is noted that the order ① to ⑩ is described to help understand the content related to the process of the driving method. However, it is not necessary to perform the steps ① to ⑩ in the order described. In addition, it is described that although parallel control is performed simultaneously in the timing setting unit 148 and the timing control unit 145 (also referred to as a controller or timing controller) of the data driving unit, serial control is performed at different times in the gate signal sensing unit 141 and the timing counter unit 143, which should be interpreted as an example for better understanding. That is, depending on the device configuration, algorithm, reaction speed, etc., the control method performed in the same configuration can be executed simultaneously or at different times.

[0129] like Fig. 22 As shown, first (①), a gate start pulse GSP may be output from the timing controller 120. Next (②), a first point of the gate line may be sensed through a first sensing line SENL1 ​​connected to a gate signal sensing unit 141 of a data driving unit. Next (③), a second point of the gate line may be sensed through a second sensing line SENL2 connected to a gate signal sensing unit 141 of a data driving unit.

[0130] Next (④), the gate start pulse GSP (for example, the gate start pulse timing) can be sensed by the timing counter unit 143 of the data driving unit. Next (⑤), the logic high start time THS1 of the gate signal at the first point can be sensed from the first point of the gate line by the timing counter unit 143 of the data driving unit. Next (⑥), the logic high start time THS2 of the gate signal at the second point can be sensed from the second point of the gate line by the timing counter unit 143 of the data driving unit. Next (⑦), the logic high end time THE1 of the gate signal at the first point can be sensed from the first point of the gate line by the timing counter unit 143 of the data driving unit. Next (⑧), the logic high end time THE2 of the gate signal at the second point can be sensed from the second point of the gate line by the timing counter unit 143 of the data driving unit.

[0131] Next (⑨), the difference between the logic high start time THS1 of the gate signal at the first point and the gate start pulse GSP can be calculated by the timing setting unit 148 of the data driving unit. At the same time (⑨), the difference between the logic high start time THS1 of the gate signal at the first point and the logic high end time THS1 of the gate signal at the first point can be calculated by the timing setting unit 148 of the data driving unit. At the same time (⑨), the difference between the logic high start time THS1 of the gate signal at the first point and the logic high start time THS2 of the gate signal at the second point can be divided by the number of output channels of the data driving unit by the timing setting unit 148 of the data driving unit. At the same time (⑨), the difference between the logic high start time THS1 of the gate signal at the first point and the logic high start time THS2 of the gate signal at the second point can be calculated by the timing setting unit 148 of the data driving unit. In this case, the delay value according to the output channel direction of the data driving unit can be determined according to whether the difference between the two values ​​is a positive number or a negative number.

[0132] Next (⑩), the timing control unit 145 of the data driving unit can control the data output start timing (Output StartTiming) based on the difference between the logic high start time THS1 of the gate signal at the first point and the gate start pulse GSP. At the same time (⑩), the timing control unit 145 of the data driving unit can control the data output width (Output Width) based on the difference between the logic high start time THS1 of the gate signal at the first point and the logic high end time THE1 of the gate signal at the first point. At the same time (⑩), the timing control unit 145 of the data driving unit can control the delay value (ChannelDelay) between the data output channels based on the value obtained by dividing the difference between the logic high start time THS1 of the gate signal at the first point and the logic high start time THS2 of the gate signal at the second point by the number of output channels of the data driving unit. At the same time (⑩), the timing control unit 145 of the data driving unit can control the direction of the delay value (Direction of Channel Delay) according to the direction of the output channel of the data driving unit based on the difference between the logic high start time THS1 of the gate signal at the first point and the logic high start time THS2 of the gate signal at the second point. For example, when the difference between the two values ​​is a positive number, the delay value increases. However, when a negative number is obtained, the delay value may decrease. Therefore, although the delay value is from Fig.21 From the first point ([3]) to the second point ([4]), the delay value can be reduced from the eighth point (

[10] ) to the seventh point ([9]).

[0133] As described above, in the second embodiment, the method of automatically correcting the data output timing of the data driving unit after sensing the delay characteristics of the gate signal at each position based on the gate start pulse GSP has been described as an example.

[0134] However, the embodiment can utilize the source output enable signal (SOE, a signal that enables the data signal to be output) output from the timing controller 120 and apply the source output enable signal SOE instead of the gate start pulse GSP to the data driving unit. For example, the source output enable signal SOE can be a signal that controls the output of the data driving unit transmitted to the pixel. Here, the output of the data driving unit starts at the start time of the source output enable signal SOE, and the output width is based on the width of the source output enable signal SOE. In addition, the embodiment can replace the gate start pulse GSP by using the data output signal EPIData (hereinafter referred to as the interface data output signal) of the interface engaged between the timing controller 120 and the data driving unit. For example, the data output signal EPIData can be a signal that determines the voltage output from the data driving unit, wherein the level of the output voltage of the data driving unit is determined according to the interface data output signal EPIData. In some embodiments, the source output enable signal SOE can be implemented as a data packet in the data output signal EPIData. Therefore, hereinafter, the third embodiment and the fourth embodiment will be described using an example using the source output enable signal SOE or the interface data output signal EPIData.

[0135] At the same time, when the source output enable signal SOE or the interface data output signal EPIData is used, the sensing of the gate signal or the gate start pulse can be omitted. However, sensing the gate signal can at least improve the accuracy of the output timing. In the following, a description will be given using an example including sensing of the gate signal.

[0136] Fig.23 1 is a diagram for describing a driving method of an LED display device according to a third embodiment. Note that the description in order ① to ⑩ is to help understand the contents related to the process of the driving method. At the same time, the third embodiment is different from the second embodiment in that the gate start pulse GSP is replaced by the source output enable signal SOE, and only the relevant part will be described. However, it is not necessary to perform in the order of the steps ① to ⑩ described.

[0137] like Fig.23 As shown, first (①), the source output enable signal SOE can be output from the timing controller 120. Next (②), the first point of the gate line can be sensed through the first sensing line SENL1 ​​connected to the gate signal sensing unit 141 of the data driving unit. Next (③), the second point of the gate line can be sensed through the second sensing line SENL2 connected to the gate signal sensing unit 141 of the data driving unit.

[0138] Next (④), the logic high start time THS1 of the gate signal at the first point can be sensed from the first point of the gate line by the timing counter unit 143 of the data driving unit. Next (⑤), the logic high start time THS2 of the gate signal at the second point can be sensed from the second point of the gate line by the timing counter unit 143 of the data driving unit. Next (⑥), the logic high end time THE1 of the gate signal at the first point can be sensed from the first point of the gate line by the timing counter unit 143 of the data driving unit. Next (⑦), the logic high end time THE2 of the gate signal at the second point can be sensed from the second point of the gate line by the timing counter unit 143 of the data driving unit.

[0139] Next (⑧), the difference between the logic high start time THS1 of the gate signal at the first point and the source output enable signal SOE can be calculated by the timing setting unit 148 of the data driving unit. At the same time (⑧), the timing setting unit 148 of the data driving unit can correct the width of the source output enable signal SOE by (and based on) the difference between the logic high start time THS1 of the gate signal at the first point and the logic high end time THS1 of the gate signal at the first point. At the same time (⑧), the timing setting unit 148 of the data driving unit can divide the difference between the logic high start time THS1 of the gate signal at the first point and the logic high start time THS2 of the gate signal at the second point by the number of output channels of the data driving unit. At the same time (⑧), the difference between the logic high start time THS1 of the gate signal at the first point and the logic high start time THS2 of the gate signal at the second point can be calculated by the timing setting unit 148 of the data driving unit.

[0140] Next (⑨), the timing control unit 145 of the data driving unit can control the data output width (Output Width) based on the correction width of the source output enable signal SOE. It can be seen from the above process that when the source output enable signal SOE is used, it is not necessary to sense the gate start pulse GSP. Therefore, the data driving unit can omit the terminal for receiving the gate start pulse GSP and omit the step for sensing the gate start pulse GSP. Omitting the terminal for receiving the gate start pulse can simplify manufacturing and reduce the cost of the display device.

[0141] Fig.24 4 is a diagram for describing a driving method of an LED display device according to a fourth embodiment. Fig.24In the description, it is noted that the order ① to ⑨ is described to help understand the contents related to the process of the driving method. At the same time, the fourth embodiment differs from the second embodiment in that the gate start pulse GSP is replaced by the interface data output signal EPIData, and only the relevant parts will be described. However, it is not necessary to perform in the order of the described steps ① to ⑨. Similar to the above, replacing the gate start pulse GSP with the interface data output signal EPIData avoids the need to sense the gate start pulse GSP and set a terminal for receiving the gate start pulse GSP.

[0142] like Fig.24 As shown, first (①), the interface data output signal EPIData can be generated from the timing controller 120. Next (②), the first point of the gate line can be sensed by the first sensing line SENL1 ​​connected to the gate signal sensing unit 141 of the data driving unit. Next (③), the second point of the gate line can be sensed by the second sensing line SENL2 connected to the gate signal sensing unit 141 of the data driving unit.

[0143] Next (④), the input timing of the interface data output signal EPIData can be sensed by the timing counter unit 143 of the data driving unit. Next (⑤), the logic high start time THS1 of the gate signal at the first point can be sensed from the first point of the gate line by the timing counter unit 143 of the data driving unit. Next (⑥), the logic high start time THS2 of the gate signal at the second point can be sensed from the second point of the gate line by the timing counter unit 143 of the data driving unit. Next (⑦), the logic high end time THE1 of the gate signal at the first point can be sensed from the first point of the gate line by the timing counter unit 143 of the data driving unit. Next (⑧), the logic high end time THE2 of the gate signal at the second point can be sensed from the second point of the gate line by the timing counter unit 143 of the data driving unit.

[0144] Next (⑨), the difference between the logic high start time THS1 of the gate signal at the first point and the input timing of the interface data output signal EPIData can be calculated by the timing setting unit 148 of the data driving unit. Next (⑩), the timing control unit 145 of the data driving unit can control the data output start timing (Output Start Timing) based on the difference between the logic high start time THS1 of the gate signal at the first point and the input timing of the interface data output signal EPIData.

[0145] Hereinafter, a description will be given of a fifth embodiment in which data output delay information can be exchanged between data driving units based on a delay pulse line (or an additionally provided signal line for performing a function similar to the delay pulse line).

[0146] Fig.25 is an exemplary diagram showing a data driving unit including a timing setting unit according to a fifth embodiment, Fig.26 is an exemplary configuration diagram of data driving units connected by delay pulse lines according to a fifth embodiment, Fig. 27 yes Fig.26 The internal block diagram of the first data driving unit is shown in FIG. Fig.28 This is a partial configuration diagram of a large-size LED display device.

[0147] like Fig.25 As shown in FIG. 1 , as in the second embodiment, the data driving unit 140 may further include a timing setting unit (Timing Setting) for providing data output timing information. Fig.26 As shown, the first and second data driving units 140A and 140B may be electrically connected to a delay pulse line DPL together with a gate start pulse line GSPL transmitting a gate start pulse GSP and a gate line (or a dummy gate line) transmitting a gate signal.

[0148] The delay pulse line DPL is a line for transmitting a delay pulse DP capable of reporting data output delay information. The first data driver unit 140A can receive a delay pulse DP from the outside, and can output a delay pulse DP by adding a value capable of reporting its data output state to an adjacent second data driver unit 140B. In addition, the second data driver unit 140B can control its data output timing based on the delay pulse DP output from the first data driver unit 140A. For example, the second data driver unit 140B can be configured to perform a control operation based on the delay pulse DP output from the first data driver unit 140A, so that the output timing of the first output channel of the second data driver unit 140B follows the output timing of the last output channel of the first data driver unit 140A.

[0149] like Fig. 27 As shown, as in the second embodiment, the first data driving unit 140A may include a series-parallel controller, a shift register, a latch, a digital-to-analog conversion unit DAC, a multi-channel output unit Multi-channel Output, a first signal sensing unit SENC1, a second signal sensing unit SENC2, a controller (also referred to as a timing control unit in this article) Timing Control, a timing setting unit (Timing Setting), an amplification unit G / A, an analog-to-digital conversion unit ADC, a sampling circuit unit Sample Circuit, a signal transmission unit TX, etc.

[0150] At the same time, if Fig.26As shown, the series-parallel controller may include a first pulse input terminal connected to a first delayed pulse line DPL1 and a second pulse input terminal connected to a second delayed pulse line DPL2 to exchange delayed pulses through the delayed pulse lines DPL. The delayed pulses input or output through the first delayed pulse line DPL1 and the second delayed pulse line DPL2 can be transmitted to the series-parallel controller, signal sensing units SENC1 and SENC2, latches, timing control units TimingControl, timing setting units (Timing Setting), etc.

[0151] In addition, the serial-parallel controller can output an output control signal LDOS capable of controlling the data output of the latch based on the delay pulse. In addition, the serial-parallel controller can receive an output end signal LCOS for determining the output timing of the last output channel from the latch to control (change) and output the delay pulse.

[0152] like Fig.28 As shown, in the case of being implemented as a large-size LED display device, as in the second embodiment, at least four data driving units 140A to 140D may be included. The first data driving unit 140A and the second data driving unit 140B may apply data signals to the left display area relative to the center line of the display panel, and the third data driving unit 140C and the fourth data driving unit 140D may apply data signals to the right display area relative to the center line of the display panel.

[0153] As in the second embodiment, the first signal sensing unit SENC1 may include a gate signal sensing unit (Gate Sensing) 141 receiving the first sensing signal SEN1 and a timing counter unit (TimingCounter) 143 receiving the gate start pulse GSP. In addition, the second signal sensing unit SENC1 may be configured similarly to the first signal sensing unit SENC1. In addition, the timing control unit Timing Control and the timing setting unit (Timing Setting) may receive the delay pulse DP to perform the function of controlling the data output timing thereof.

[0154] Hereinafter, a driving method of the LED display device according to the fifth embodiment will be described. However, the operation of the second data driving unit capable of receiving a delayed pulse from the first data driving unit will be described as an example.

[0155] Fig.29 1 is a diagram for describing a driving method of an LED display device according to a fifth embodiment. Fig.29 In the sequence ① to The description is intended to help understand the content related to the process of driving the method. However, it is not necessary to follow the steps ① to ② described. Execute in order.

[0156] like Fig.29 As shown, first (①), a delayed pulse DP may be output from the first data driving unit 140A. Next (②), a third point of the gate line may be sensed through the third sensing line SENL3 connected to the gate signal sensing unit 141 of the second data driving unit. Next (③), a fourth point of the gate line may be sensed through the fourth sensing line SENL4 connected to the gate signal sensing unit 141 of the second data driving unit.

[0157] Next (④), the delay time (Delay Timing) of the first data driving unit 140A can be counted by the timing counter unit 143 of the second data driving unit 140B. Next (5), the logic high start time THS3 of the gate signal at the third point can be sensed from the third point of the gate line by the timing counter unit 143 of the second data driving unit. Next (⑥), the logic high start time THS4 of the gate signal at the fourth point can be sensed from the fourth point of the gate line by the timing counter unit 143 of the second data driving unit. Next (⑦), the logic high end time THE3 of the gate signal at the third point can be sensed from the third point of the gate line by the timing counter unit 143 of the second driving unit. Next (⑧), the logic high end time THE4 of the gate signal at the fourth point can be sensed from the fourth point of the gate line by the timing counter unit 143 of the second data driving unit.

[0158] Next (⑨), the delay time (Delay Timing) between the first data driving unit and the second data driving unit can be calculated by the timing setting unit 148 of the second data driving unit. At the same time (⑨), the difference between the logic high start time THS3 of the gate signal at the third point and the logic high end time THE3 of the gate signal at the third point can be calculated by the timing setting unit 148 of the second data driving unit. At the same time (⑨), the difference between the logic high start time THS3 of the gate signal at the third point and the logic high start time THS4 of the gate signal at the fourth point can be divided by the number of output channels of the second data driving unit by the timing setting unit 148 of the second data driving unit. At the same time (⑨), the difference between the logic high start time THS3 of the gate signal at the third point and the logic high start time THS4 of the gate signal at the fourth point can be calculated by the timing setting unit 148 of the second data driving unit. In this case, the delay value according to the output channel direction of the data driving unit can be determined according to whether the difference between the two values ​​is a positive number or a negative number.

[0159] Next (⑩), the timing control unit 145 of the second data driving unit can control (correct) the data output start timing (Output Start Timing) based on the delay time (Delay Timing) between the first data driving unit and the second data driving unit. At the same time (⑩), the timing control unit 145 of the second data driving unit can control the data output width (Output Width) based on the difference between the logic high start time THS3 of the gate signal at the third point and the logic high end time THE3 of the gate signal at the third point. At the same time (⑩), the timing control unit 145 of the second data driving unit can control the delay value (Channel Delay) between the data output channels based on the value obtained by dividing the difference between the logic high start time THS3 of the gate signal at the third point and the logic high start time THS4 of the gate signal at the fourth point by the number of output channels of the second data driving unit. At the same time (⑩), the timing control unit 145 of the second data driving unit can control the direction of the delay value (Direction of Channel Delay) according to the output channel direction of the second data driving unit based on the difference between the logic high start time THS3 of the gate signal at the third point and the logic high start time THS4 of the gate signal at the fourth point.

[0160] Next ( ), the timing setting unit 148 of the second data driving unit can calculate a signal indicating that the output timing (Last Channel Output Timing) of the last output channel has occurred. Next ( ), the timing control unit 145 of the second data driving unit can control the delay pulse timing (DP Timing) to be transmitted to the next data driving unit (for example, the third data driving unit) based on the signal indicating that the output timing (Last Channel Output) of the last output channel has occurred.

[0161] Meanwhile, in an embodiment, at least any two of the foregoing embodiments (methods) may be combined to improve driving stability and output accuracy when automatically correcting data output timing. The corrected data output timing will be described below. However, the operation of the second data driving unit capable of receiving a delayed pulse from the first data driving unit will be described as an example.

[0162] Fig.30 1 is a diagram for describing a driving method of an LED display device according to a sixth embodiment. Fig.30 In the sequence ① to The description is intended to help understand the content related to the process of driving the method. However, it is not necessary to follow the steps ① to ② described. Execute in order.

[0163] like Fig.30 As shown, first (①), a gate start pulse GSP may be output from the timing controller 120. Next (②), an interface data output signal EPIData may be generated while a source output enable signal SOE is output from the timing controller 120.

[0164] Next (③), a delay pulse DP may be output from the first data driving unit 140A. Next (④), a third point of the gate line may be sensed through the third sensing line SENL3 connected to the gate signal sensing unit 141 of the second data driving unit. Next (⑤), a fourth point of the gate line may be sensed through the fourth sensing line SENL4 connected to the gate signal sensing unit 141 of the second data driving unit.

[0165] Next (⑥), the gate start pulse GSP may be sensed by the timing counter unit 143 of the second data driving unit. Next (⑦), the input timing of the interface data output signal EPIData may be sensed by the timing counter unit 143 of the second data driving unit. Next (⑧), the delay time (Delay Timing) of the first data driving unit 140A may be counted by the timing counter unit 143 of the second data driving unit.

[0166] Next (⑨), the logic high start time THS3 of the gate signal at the third point can be sensed from the third point of the gate line by the timing counter unit 143 of the second data driving unit. Next (⑩), the logic high start time THS4 of the gate signal at the fourth point can be sensed from the fourth point of the gate line by the timing counter unit 143 of the second data driving unit. Next ( ), the logic high end time THE3 of the gate signal at the third point can be sensed from the third point of the gate line by the timing counter unit 143 of the second data driving unit. Next ( ), the logic high end time THE4 of the gate signal at the fourth point can be sensed from the fourth point of the gate line by the timing counter unit 143 of the second data driving unit.

[0167] Next ( ), the difference between the logic high start time THS3 of the gate signal at the third point and the gate start pulse GSP can be calculated by the timing setting unit 148 of the second data driving unit. ), the difference between the logic high start time THS3 of the gate signal at the third point and the input timing of the interface data output signal EPIData can be calculated by the timing setting unit 148 of the second data driving unit. ), the difference between the logic high start time THS3 of the gate signal at the third point and the source output enable signal SOE can be calculated by the timing setting unit 148 of the second data driving unit. ), the delay time (Delay Timing) between the first data driving unit and the second data driving unit can be calculated by the timing setting unit 148 of the second data driving unit. ), the width of the source output enable signal SOE can be corrected by using the difference between the logic high start time THS3 of the gate signal at the third point and the logic high end time THE3 of the gate signal at the third point through the timing setting unit 148 of the second data driving unit. ), the difference between the logic high start time THS3 of the gate signal at the third point and the logic high start time THS4 of the gate signal at the fourth point can be divided by the number of output channels of the second data driving unit through the timing setting unit 148 of the second data driving unit. ), the difference between the logic high start time THS3 of the gate signal at the third point and the logic high start time THS4 of the gate signal at the fourth point can be calculated by the timing setting unit 148 of the second data driving unit. In this case, the delay value according to the output channel direction of the data driving unit can be determined according to whether the difference between the two values ​​is a positive number or a negative number.

[0168] Next ( ), at least one of the following (A), (B), (C) or (D) can be selected and output, so as to control the data output start timing (Output Start Timing) through the timing setting unit 148 of the second data driving unit, wherein (A) the difference between the logic high start time THS3 of the gate signal at the third point and the gate start pulse GSP, (B) the difference between the logic high start time THS1 of the gate signal at the first point and the interface data output signal EPIData, (C) the difference between the logic high start time THS3 of the gate signal at the third point and the source output enable signal SOE, (D) the delay time (Delay Timing) between the first data driving unit and the second data driving unit.

[0169] Next ( ), the timing control unit 145 of the second data driving unit can control (correct) the data output start timing (Output Start Timing) based on at least one selected from (A), (B), (C) or (D). ), the timing control unit 145 of the second data driving unit can control the data output width (OutputWidth) based on the difference between the logic high start time THS3 of the gate signal at the third point and the logic high end time THE3 of the gate signal at the third point. ), the timing control unit 145 of the second data driving unit can control the delay value (ChannelDelay) between the data output channels based on the value obtained by dividing the difference between the logic high start time THS3 of the gate signal at the third point and the logic high start time THS4 of the gate signal at the fourth point by the number of output channels of the second data driving unit. At the same time ( ), the timing control unit 145 of the second data driving unit can control the direction of the delay value (Direction of Channel Delay) according to the output channel direction of the second data driving unit based on the difference between the logic high start time THS3 of the gate signal at the third point and the logic high start time THS4 of the gate signal at the fourth point.

[0170] Next ( ), a signal indicating that the output timing (Last Channel Output Timing) of the last output channel has appeared can be calculated by the timing setting unit 148 of the second data driving unit.

[0171] Next ( ), the timing control unit 145 of the second data driving unit can control the delayed pulse timing (DP Timing) to be transmitted to the next data driving unit (for example, the third data driving unit) based on the signal indicating that the output timing (Last Channel Output Timing) of the last output channel has been generated.

[0172] Hereinafter, an example of the adjustment method of the output timing in the above-described embodiment will be described as follows.

[0173] Fig.31 is an exemplary diagram showing an adjustment method of output timing applicable to the second embodiment, the third embodiment and the sixth embodiment, Fig.32 is an exemplary diagram showing an adjustment method of output timing applicable to the fourth embodiment and the sixth embodiment, Fig.33 is an exemplary diagram showing an adjustment method of output timing applicable to the first to sixth embodiments, and Fig.34 : is a diagram showing an example of an adjustment method of output timing applicable to the fifth embodiment and the sixth embodiment.

[0174] like Fig.31As shown, in the second embodiment, the third embodiment, and the sixth embodiment, the data output timing can be controlled based on the source output enable signal SOE. Whenever the source output enable signal SOE is generated as logic high (H), the data signal Data can be output as D00, D01, D02, etc. However, when a delayed source output enable signal SOE' is provided by delaying the start time TS and the end time TE of the source output enable signal SOE, a delayed output timing of the data signal Data' can be generated.

[0175] As Fig.32 shown, in the fourth embodiment and the sixth embodiment, the data output timing can be controlled based on the interface data output signal EPI Data. Whenever the interface data output signal EPIData such as EP10, EP11, EP12, etc. is generated (generated in the form of packets), the data signal Data can be output as D00, D01, D02, etc. However, when a delayed interface data output signal EPIData' is provided by delaying the interface data output signal EPIData by TED, a delayed output timing of the data signal Data' can be generated.

[0176] As Fig.33 shown, in the first embodiment to the sixth embodiment, the data output timing can be controlled based on the delay values between the output channels of the data driving unit. The data signal Data can be output simultaneously in all channels as D00, D01, D02, etc. However, when the delay values between the output channels are delayed such that the delay values gradually increase as T1 < T2 < T3, a delayed output timing of the data signal Data' can be generated between the output channels.

[0177] In Fig.33 this, the delay values gradually increase, taking "T2 = T1 + Delay (delay value) * 1", "T3 = T1 + Delay (delay value) * 2", and "T (Channel No, channel number) = T1 + Delay (delay value) * (channel number - 1)" as examples, which are only examples and the embodiments are not limited thereto.

[0178] As Fig.34As shown, the fifth embodiment and the sixth embodiment can control the data output timing based on the delay pulse applied to the data driving unit. For example, the first data driving unit SD-IC_A can receive the basic delay value (SD-IC Delay) from the timing controller T-CON. In addition, the first data driving unit SD-IC_A can transmit the delay pulse DP to the second data driving unit SD-IC_B without changing the basic delay value (SD-IC Delay), or can reflect its data output state, change the delay pulse DP, and transmit the delay pulse DP to the second data driving unit SD-IC_B.

[0179] Therefore, although the first data driving unit SD-IC_A can output the data signal #1Data in a general form (a form without delay) such as D00, D01, D02, etc., the second data driving unit SD-IC_B can output the data signal #2Data in a form delayed by a time corresponding to the delay pulse DP, such as D00, D01, D02, etc.

[0180] In addition, referring to the above embodiments, it can be seen that, in order to help understanding, the configuration of the device or method related to the method of automatically correcting the data output timing has been described. However, it should be understood that one or more of the various embodiments can be combined.

[0181] As described above, for example, based on the interaction between the timing controller and the data driving unit, the embodiment has the effect of automatically correcting and optimizing the data output timing of the data driving unit. In addition, since the gate signal is sensed through the gate line, and the data output timing is controlled by referring to the operation of another device (or component) or the signal generated by it and analyzing the operation and the signal, the embodiment has the effect of improving the driving stability and output accuracy of the data driving unit.

[0182] It will be apparent to those skilled in the art that various modifications and variations may be made to the embodiments without departing from the scope of the appended claims. Therefore, it is intended that the present disclosure covers modifications and variations that come within the scope of the appended claims and their equivalents.

[0183] In addition, the present disclosure includes the following:

[0184] Item 1: A display device comprising:

[0185] a display panel configured to display an image;

[0186] A gate driving circuit connected to the display panel;

[0187] a data driving circuit connected to the display panel; and

[0188] The timing controller is configured to control the gate driving circuit and the data driving circuit,

[0189] The data driving circuit senses a gate signal output from the gate driving circuit, and controls data output timing based on the operation of another device or a signal generated from another device and based on the sensed gate signal.

[0190] Item 2. A display device according to item 1, wherein the data driving circuit comprises at least two sensing terminals, and the at least two sensing terminals are connected to two points of a gate line or a dummy gate line located on the display panel to sense a gate signal output from the gate driving circuit.

[0191] Item 3. The display device according to Item 2, wherein the at least two sensing terminals are located at the outermost side of one side and the outermost side of the other side of the data driving circuit.

[0192] Item 4. A display device according to any of the preceding items, wherein a data output timing of the data driving circuit is controlled based on a gate signal and a gate start pulse applied to the gate driving circuit.

[0193] Item 5. A display device according to any of the preceding items, wherein a data output timing of the data driving circuit is controlled based on a gate signal and a source output enable signal applied to the data driving circuit.

[0194] Item 6. The display device according to Item 5, wherein the data output timing of the data driving circuit is controlled by a data output signal based on a gate signal and through an interface coupled between the timing controller and the data driving circuit.

[0195] Item 7. A display device according to any of the preceding items, wherein the data driving circuit includes at least two data driving circuits electrically connected to each other through a delay pulse line, and the delay pulse line is used to input and output pulses including data output delay information of another device or data driving circuit.

[0196] Item 8. A display device according to any of the preceding items, wherein the data driving circuit includes a signal sensing circuit, and the signal sensing circuit is configured to calculate a logic high start time, a logic high end time, and a logic high hold time of the gate signal based on a gate signal output from the gate driving circuit, a gate start pulse applied to the gate driving circuit, and a voltage maintained at the same level as a gate high level of the gate signal.

[0197] Item 9. A method for driving a display device, the display device comprising: a display panel configured to display an image; a gate driving circuit connected to the display panel; a data driving circuit connected to the display panel; and a timing controller configured to control the gate driving circuit and the data driving circuit, the method comprising:

[0198] sensing a gate signal output from a gate driving circuit;

[0199] calculating a data output delay of a data driving circuit based on the gate signal; and

[0200] The data output timing of the data driving circuit is set based on the data output delay.

[0201] Item 10. A display device according to any of the preceding items, wherein the data output timing of the data driving circuit is controlled based on a gate signal and a gate start pulse applied to a gate driving circuit, based on a gate signal and a source output enable signal applied to a data driving circuit, or based on a gate signal and a data output signal through an interface coupled between a timing controller and a data driving circuit.

Claims

1. A display device, comprising: a display panel configured to display an image; A gate driving circuit connected to the display panel; A data driving circuit connected to the display panel; as well as a timing controller configured to control the gate driving circuit and the data driving circuit, The data driving circuit is configured to: control the data output timing of the data driving circuit based on the gate signal sensed from the gate driving circuit, and The data driving circuit is configured to control the data output timing of the data driving circuit based on the operation of a component of the display device or a signal generated by the component of the display device and the sensed gate signal.

2. The display device according to claim 1, wherein: The components are: the data driving circuit, another data driving circuit of the display device, the timing controller, a timing setting unit of the timing controller; a timing setting unit of the data driving circuit; a timing control unit of the data driving circuit; a timing setting unit of another data driving circuit; or a timing control unit of another data driving circuit.

3. The display device according to claim 1, wherein: The display device includes at least two sensing terminals connected to different points of a gate line or a dummy gate line located on the display panel, wherein the at least two sensing terminals are configured to sense the gate signal output from the gate driving circuit, Wherein, the data driving circuit includes the at least two sensing terminals.

4. The display device according to claim 3, wherein: The at least two sensing terminals are located at the outermost side of one side or the outermost side of the other side of the data driving circuit.

5. The display device according to any one of claims 1 to 3, wherein: The data driving circuit is configured to control the data output timing of the data driving circuit based on the sensed gate signal and a gate start pulse applied to the gate driving circuit.

6. The display device according to any one of claims 1 to 3, wherein: The data driving circuit is configured to control the data output timing of the data driving circuit based on the sensed gate signal and a source output enable signal applied to the data driving circuit.

7. The display device according to any one of claims 1 to 3, wherein: The data driving circuit is configured to control the data output timing of the data driving circuit based on the sensed gate signal and a data output signal through an interface coupled between the timing controller and the data driving circuit.

8. The display device according to any one of claims 1 to 3, wherein: The data driving circuit includes at least two data driving units electrically connected to each other through a delayed pulse line for inputting and outputting pulses, wherein the pulses include data output delay information of the component or the data driving circuit.

9. The display device according to any one of claims 1 to 3, wherein: The data driving circuit includes a signal sensing circuit, which is configured to calculate a logic high start time, a logic high end time, and a logic high hold time of the sensed gate signal based on the gate signal output from the gate driving circuit, a gate start pulse applied to the gate driving circuit, and a voltage source maintained at the same level as a gate high level of the sensed gate signal.

10. A method for driving a display device, the display device comprising: a display panel configured to display an image; A gate driving circuit connected to the display panel; A data driving circuit connected to the display panel; and a timing controller configured to control the gate driving circuit and the data driving circuit, the method comprising: sensing a gate signal output from the gate driving circuit; controlling the data output timing of the data driving circuit based on the sensed gate signal, The data driving circuit is configured to control the data output timing of the data driving circuit based on the operation of a component of the display device or a signal generated by the component of the display device and the sensed gate signal.

11. The method according to claim 10, further comprising: Calculating a data output delay of the data driving circuit based on the gate signal; as well as Based on the data output delay, a data output timing of the data driving circuit is set.

12. The method according to claim 11, wherein: based on the gate signal and a gate start pulse applied to the gate driving circuit; a source output enable signal applied to the data driving circuit based on the gate signal; or Based on the gate signal and the data output signal through the interface coupled between the timing controller and the data driving circuit, Controlling the data output timing of the data driving circuit.

13. The method according to any one of claims 10 to 12, wherein: The components are: the data driving circuit, another data driving circuit of the display device, the timing controller, a timing setting unit of the timing controller; a timing setting unit of the data driving circuit; a timing control unit of the data driving circuit; a timing setting unit of another data driving circuit; or a timing control unit of another data driving circuit.

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