Pixel circuit

Abstract

The invention relates to a pixel circuit. The pixel circuit includes: a light emitting element including an anode electrode and a cathode electrode; a driving transistor including a gate electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a data write transistor including a gate electrode, a first electrode, and a second electrode connected to the second node; a compensation transistor including a gate electrode, a first electrode connected to the third node, and a second electrode connected to the first node; an initialization transistor including a gate electrode, a first electrode, and a second electrode connected to the first node; a first light emission control transistor including a gate electrode, a first electrode, and a second electrode connected to the second node; and a storage capacitor including a first electrode and a second electrode connected to the first node.

Description

Technical Field

[0001] The present invention relates to a pixel circuit, and more particularly, to a pixel circuit having a high pixel per inch (PPI) and a display device including the pixel circuit. Background Art

[0002] Generally, a display device may include a display panel and a display panel driver. The display panel may include a gate line, a data line, an emission line, and a pixel circuit. The display panel driver may include a gate driver for providing a gate signal to the gate line, a data driver for providing a data voltage to the data line, an emission driver for providing an emission signal to the emission line, and a drive controller for controlling the gate driver, the data driver, and the emission driver.

[0003] Recently, display devices that provide virtual reality (VR) or augmented reality (AR) have gained attention. In this case, since the pitch occupied by the pixel circuit becomes narrower, there may be restrictions on the number of transistors constituting the pixel circuit and the signal applied to the pixel circuit. Summary of the invention

[0004] Embodiments of the present invention provide pixel circuits for low area and high PPI.

[0005] In an embodiment, a pixel circuit includes: a light-emitting element including an anode electrode and a cathode electrode receiving a second power voltage; a driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a data write transistor including a gate electrode receiving a data write gate signal, a first electrode connected to a data line providing a data voltage, and a second electrode connected to the second node; a compensation transistor including a gate electrode receiving the data write gate signal, a first electrode connected to the third node, and a second electrode connected to the first node; an initialization transistor including a gate electrode receiving an initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a first light-emitting control transistor including a gate electrode receiving the data write gate signal, a first electrode receiving a first power voltage, and a second electrode connected to the second node; and a storage capacitor including a first electrode receiving the first power voltage and a second electrode connected to the first node.

[0006] In an embodiment, the data writing transistor is an N-type transistor, and the first light emission control transistor may be a P-type transistor.

[0007] In an embodiment, the data write transistor and the first light emission control transistor may form a complementary metal oxide semiconductor (CMOS).

[0008] In an embodiment, the pixel circuit may further include: a second light emission control transistor including a gate electrode receiving the data write gate signal, a first electrode connected to the third node, and a second electrode connected to the anode electrode.

[0009] In an embodiment, the compensation transistor may be an N-type transistor, and the second light emission control transistor may be a P-type transistor.

[0010] In an embodiment, the compensation transistor and the second light emission control transistor may form a CMOS.

[0011] In an embodiment, in a first period, the initialization gate signal and the data write gate signal may have a high voltage level.

[0012] In an embodiment, in the first period, the initialization transistor may provide the initialization voltage to the first node, and the initialization transistor and the compensation transistor may provide the initialization voltage to the third node.

[0013] In an embodiment, in a second period after the first period, the initialization gate signal may have a low voltage level, and the data write gate signal may have the high voltage level.

[0014] In an embodiment, in the second period, the data voltage may be provided to the gate electrode of the driving transistor through the data write transistor, the driving transistor, and the compensation transistor.

[0015] In an embodiment, in the second period, when the compensation transistor is turned on, the compensation transistor may be diode-connected to the driving transistor.

[0016] In an embodiment, in a third period after the second period, the initialization gate signal may have the low voltage level, and the data write gate signal may have a low voltage level.

[0017] In an embodiment, in the third period, the driving current of the driving transistor may flow to the light emitting element.

[0018] According to the pixel circuit, since some transistors included in the pixel circuit are N-type transistors, the leakage current of the pixel circuit can be minimized. Since the data write transistor and the first light emission control transistor form a CMOS, the area of ​​the pixel circuit can be reduced. Since the compensation transistor and the second light emission control transistor form a CMOS, the area of ​​the pixel circuit can be reduced. Since the compensation transistor is connected to the drive transistor in a diode manner, the threshold voltage of the drive transistor can be compensated. Since the second light emission control transistor is turned off in a non-emission period other than the emission period, the light emission of the light emitting element caused by the leakage current flowing into the light emitting element can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other features of the embodiments of the present invention will become more apparent by describing detailed embodiments of the present invention with reference to the accompanying drawings, in which:

[0020] Figure 1 is a block diagram showing a display device according to an embodiment;

[0021] Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A circuit diagram of an example of a pixel circuit;

[0022] Figure 3 is a diagram showing a driving Figure 2 A timing diagram of an example of a pixel circuit;

[0023] Figure 4 is a diagram showing the operation in the first cycle according to the embodiment Figure 2 A timing diagram of an example of a pixel circuit;

[0024] Figure 5 is a diagram showing the operation in the first cycle according to the embodiment Figure 2 A circuit diagram of an example of a pixel circuit;

[0025] Figure 6 is a diagram showing the operation in the second cycle according to an embodiment Figure 2 A timing diagram of an example of a pixel circuit;

[0026] Figure 7 is a diagram showing the operation in the second cycle according to an embodiment Figure 2 A circuit diagram of an example of a pixel circuit;

[0027] Figure 8 is a diagram showing the operation in the third cycle according to an embodiment Figure 2 A timing diagram of an example of a pixel circuit;

[0028] Fig. 9 is a diagram showing the operation in the third cycle according to an embodiment Figure 2 A circuit diagram of an example of a pixel circuit;

[0029] Fig.10 is a block diagram showing an electronic device according to an embodiment; and

[0030] Fig.11 It shows that Fig.10 FIG. 1 is a diagram of an embodiment of an electronic device 1000 implemented as a VR device. DETAILED DESCRIPTION

[0031] In the following, the present invention will be described in more detail with reference to the accompanying drawings, in which various embodiments are shown. Like reference numerals refer to like elements throughout.

[0032] It will be understood that when an element (or region, layer, portion, etc.) is referred to as being related to another element, such as "on" another element, "connected to" another element, or "coupled to" another element, it can be directly disposed on the other element, directly connected to or coupled to the other element, or intervening elements may be disposed therebetween.

[0033] The same reference numerals or symbols always indicate the same elements. In the drawings, the thickness, proportion and size of the elements are exaggerated in order to effectively describe the technical content. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0034] The term "and / or" may include all possible combinations of one or more relevant configurations.

[0035] It will be understood that, although the term first, second, etc. can be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the scope of the present invention, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part. Similarly, the second element, component, region, layer or part can be referred to as the first element, component, region, layer or part. As used herein, unless the context clearly indicates otherwise, the singular form "one", "a kind of" and "the (the)" are also intended to include plural forms.

[0036] In addition, the relationship of elements shown in the drawings may be described using “below”, “on the lower side”, “above” or “on the upper side” etc. These terms have relative concepts and are described based on directions indicated in the drawings.

[0037] It will also be understood that when used in this specification, the terms "comprising", "including" and / or "having" indicate the presence of the described features, integers, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. As used herein, "directly disposed on" may mean that there are no additional layers, films, regions or plates, etc. between one part and another part (such as a layer, film, region or plate, etc.). For example, "directly disposed on" may mean that no additional components (such as an adhesive component) are used between two layers or two components.

[0038] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation of the particular value determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0040] Figure 1 is a block diagram showing a display device according to an embodiment.

[0041] In the examples and with reference to Figure 1 The display device 10 may include a display panel 100 and a display panel driver. The display panel driver may include a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0042] In an embodiment, the driving controller 200 and the data driver 500 may be integrally formed. In another embodiment, the driving controller 200, the gamma reference voltage generator 400 and the data driver 500 may be integrally formed. In another embodiment, the driving controller 200, the gate driver 300, the gamma reference voltage generator 400 and the data driver 500 may be integrally formed. In an embodiment, the driving module in which at least the driving controller 200 and the data driver 500 are integrally formed may be referred to as a timing controller embedded data driver (TED).

[0043] In an embodiment, the display panel 100 may include a display area for displaying an image and a peripheral area disposed adjacent to the display area.

[0044] In an embodiment, the display panel 100 may be an organic light emitting diode display panel including an organic light emitting diode. In an embodiment, the display panel 100 may be a quantum dot organic light emitting diode display panel including an organic light emitting diode and a quantum dot color filter. In another embodiment, the display panel 100 may be a quantum dot nano light emitting diode display panel including a nano light emitting diode and a quantum dot color filter.

[0045] In an embodiment, the display panel 100 may include gate lines GL, data lines DL, and pixel circuits P electrically connected to the gate lines GL and the data lines DL. The gate lines GL may extend in a first direction, and the data lines DL may extend in a second direction crossing the first direction.

[0046] In an embodiment, the drive controller 200 may receive input image data IMG and an input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0047] In an embodiment, the driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0048] In an embodiment, the driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0049] In an embodiment, the driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT and output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0050] In an embodiment, the driving controller 200 may generate a data signal DATA based on the input image data IMG. The driving controller 200 may output the data signal DATA to the data driver 500.

[0051] In an embodiment, the driving controller 200 may generate a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and output the third control signal CONT3 to the gamma reference voltage generator 400 .

[0052] In an embodiment, the gate driver 300 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate line GL.

[0053] In an embodiment, the gate driver 300 may be integrated on a peripheral area of ​​the display panel 100 .

[0054] In an embodiment, the gamma reference voltage generator 400 may generate the gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 may provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF may have a value corresponding to each data signal DATA.

[0055] In an embodiment, the gamma reference voltage generator 400 may be provided in the driving controller 200 , or may be provided in the data driver 500 .

[0056] In an embodiment, the data driver 500 may receive the second control signal CONT2 and the data signal DATA from the driving controller 200, and receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 may convert the data signal DATA into a data voltage of an analog type using the gamma reference voltage VGREF. The data driver 500 may output the data voltage to the data line DL.

[0057] Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A circuit diagram of an example of a pixel circuit. Figure 3 is a diagram showing a driving Figure 2 A timing diagram of an example of a pixel circuit.

[0058] In the examples and with reference to Figures 1 to 3The pixel circuit P may include a light emitting element EE, a driving transistor T1, a data writing transistor T2, a compensation transistor T3, an initialization transistor T4, a first light emitting control transistor T5 and a storage capacitor CST. In an embodiment, the pixel circuit P may further include a second light emitting control transistor T6.

[0059] In an embodiment, the light emitting element EE may include an anode electrode and a cathode electrode receiving the second power voltage ELVSS.

[0060] In an embodiment, the driving transistor T1 may include a gate electrode connected to the first node N1 , a first electrode connected to the second node N2 , and a second electrode connected to the third node N3 .

[0061] In an embodiment, the data write transistor T2 may include a gate electrode receiving the data write gate signal GW, a first electrode connected to the data line DL providing the data voltage VDATA, and a second electrode connected to the second node N2.

[0062] In an embodiment, the compensation transistor T3 may include a gate electrode receiving the data write gate signal GW, a first electrode connected to the third node N3 , and a second electrode connected to the first node N1 .

[0063] In an embodiment, the initialization transistor T4 may include a gate electrode receiving the initialization gate signal GI, a first electrode receiving the initialization voltage VINT, and a second electrode connected to the first node N1.

[0064] In an embodiment, the first light emission control transistor T5 may include a gate electrode receiving the data write gate signal GW, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the second node N2.

[0065] In an embodiment, the storage capacitor CST may include a first electrode receiving the first power voltage ELVDD and a second electrode connected to the first node N1.

[0066] In an embodiment, the second light emission control transistor T6 may include a gate electrode receiving the data write gate signal GW, a first electrode connected to the third node N3, and a second electrode connected to the anode electrode of the light emitting element EE.

[0067] In an embodiment, more leakage current may occur in a P-type transistor than in an N-type transistor. Therefore, some transistors included in the pixel circuit P may be N-type transistors. In an embodiment, the data write transistor T2 may be an N-type transistor, and the initialization transistor T4 may be a P-type transistor. In an embodiment, the drive transistor T1 and the compensation transistor T3 may be P-type transistors, and the first light emission control transistor T5 may be an N-type transistor. In an embodiment, the data write transistor T2 may be an N-type transistor, and the first light emission control transistor T5 may be a P-type transistor. In an embodiment, the compensation transistor T3 may be an N-type transistor, and the second light emission control transistor T6 may be a P-type transistor. In an embodiment, the drive transistor T1 may be a P-type transistor, and the initialization transistor T4 may be an N-type transistor. In an embodiment, the data write transistor T2 and the first light emission control transistor T5 may form a complementary metal oxide semiconductor (CMOS). The present disclosure is not limited thereto. Therefore, the number of gate signals and the number of lines transmitting gate signals may be reduced, and therefore, the area of ​​the pixel circuit P may be reduced. For example, when the signal applied to the gate electrode of the P-type transistor has a low voltage level, the P-type transistor may be turned on. For example, when a signal applied to the gate terminal of the P-type transistor has a high voltage level, the P-type transistor may be turned off. For example, when a signal applied to the gate electrode of the N-type transistor has a high voltage level, the N-type transistor may be turned on. For example, when a signal applied to the gate terminal of the N-type transistor has a low voltage level, the N-type transistor may be turned off.

[0068] In an embodiment, in the first period P1 , the initialization gate signal GI and the data write gate signal GW may have a high voltage level.

[0069] In an embodiment, in the second period P2 after the first period P1, the initialization gate signal GI may have a low voltage level, and the data write gate signal GW may have a high voltage level.

[0070] In an embodiment, in a third period P3 after the second period P2, the initialization gate signal GI and the data write gate signal GW may have a low voltage level.

[0071] Figure 4 is a diagram showing the operation in the first cycle according to the embodiment Figure 2 A timing diagram of an example of a pixel circuit. Figure 5 is a diagram showing the operation in the first cycle according to the embodiment Figure 2 A circuit diagram of an example of a pixel circuit.

[0072] In the examples and with reference to Figures 1 to 5, in the first period P1, the compensation transistor T3 and the initialization transistor T4 may be turned on, and the data writing transistor T2, the first light emission control transistor T5, and the second light emission control transistor T6 may be turned off.

[0073] In an embodiment, when the compensation transistor T3 and the initialization transistor T4 are turned on, the initialization transistor T4 can provide the initialization voltage VINT to the first node N1 (i.e., the gate electrode of the driving transistor T1), and the initialization transistor T4 and the compensation transistor T3 can provide the initialization voltage VINT to the third node N3 (i.e., the second electrode of the driving transistor T1). The first node N1 and the third node N3 can be initialized to the initialization voltage VINT.

[0074] Figure 6 is a diagram showing the operation in the second cycle according to an embodiment Figure 2 A timing diagram of an example of a pixel circuit. Figure 7 is a diagram showing the operation in the second cycle according to an embodiment Figure 2 A circuit diagram of an example of a pixel circuit.

[0075] In the examples and with reference to Figures 1 to 7 , in the second period P2, the data writing transistor T2 and the compensation transistor T3 may be turned on, and the initialization transistor T4, the first light emission control transistor T5, and the second light emission control transistor T6 may be turned off.

[0076] In an embodiment, when the data write transistor T2 and the compensation transistor T3 are turned on, the data voltage VDATA may be provided to the first node N1 (ie, the gate electrode of the driving transistor T1 ) through the data write transistor T2 , the driving transistor T1 , and the compensation transistor T3 .

[0077] In an embodiment, when the compensation transistor T3 is turned on, the compensation transistor T3 may be connected to the driving transistor T1 in a diode manner. Therefore, the threshold voltage of the driving transistor T1 may be compensated.

[0078] Meanwhile, in the embodiment, since the second light emission control transistor T6 is turned off in the first period P1 and the second period P2, the light emission of the light emitting element EE due to the leakage current flowing into the light emitting element EE can be prevented.

[0079] Figure 8 is a diagram showing the operation in the third cycle according to an embodiment Figure 2 A timing diagram of an example of a pixel circuit. Fig. 9 is a diagram showing the operation in the third cycle according to an embodiment Figure 2 A circuit diagram of an example of a pixel circuit.

[0080] refer to Figures 1 to 9 , in the third period P3, the first light emission control transistor T5 and the second light emission control transistor T6 may be turned on, and the data writing transistor T2, the compensation transistor T3, and the initialization transistor T4 may be turned off.

[0081] In an embodiment, the voltage of the first node N1 may be determined based on the data voltage VDATA, the driving current of the driving transistor T1 may be determined based on the voltage of the first node N1, and the driving transistor T1 may provide the driving current to the light emitting element EE. The light emitting element EE may emit light with brightness corresponding to the driving current.

[0082] In an embodiment, since some transistors included in the pixel circuit P are N-type transistors, the leakage current of the pixel circuit P can be minimized. Since the data writing transistor T2 and the first light emission control transistor T5 form a CMOS, the area of ​​the pixel circuit P can be reduced. Since the compensation transistor T3 and the second light emission control transistor T6 form a CMOS, the area of ​​the pixel circuit P can be reduced. Since the compensation transistor T3 is connected to the driving transistor T1 in a diode manner, the threshold voltage of the driving transistor T1 can be compensated. Since the second light emission control transistor T6 is turned off in a non-emission period other than the emission period, the light emission of the light emitting element EE caused by the leakage current flowing into the light emitting element EE can be prevented.

[0083] Fig.10 is a block diagram illustrating an electronic device according to an embodiment. Fig.11 It shows that Fig.10 FIG. 1 is a diagram of an embodiment of an electronic device 1000 implemented as a VR device.

[0084] In the examples and with reference to Fig.10 and Fig.11 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 The display device 10. In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, and other electronic devices.

[0085] In an embodiment, Fig.11As shown, the electronic device 1000 can be implemented as a VR device. However, the electronic device 1000 is not limited thereto. In other embodiments, the electronic device 1000 can be implemented as a mobile phone, a video phone, a smart tablet, a smart watch, a tablet personal computer (PC), a vehicle navigation system, a computer monitor, a laptop computer, and a head mounted display (HMD) device, etc.

[0086] In an embodiment, the processor 1010 may perform various computing functions. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, and a data bus, etc. In addition, the processor 1010 may be coupled to an extended bus (such as a peripheral component interconnect standard (PCI) bus).

[0087] In an embodiment, the memory device 1020 may store data for operation of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device.

[0088] In an embodiment, the storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a compact disk read only memory (CD-ROM) device, and the like.

[0089] In an embodiment, I / O device 1040 may include input devices (such as keyboards, keypads, mouse devices, touch pads, and touch screens) and output devices (such as printers and speakers). In some embodiments, I / O device 1040 may include display device 1060.

[0090] In an embodiment, the power supply 1050 may provide power for the operation of the electronic device 1000 .

[0091] In an embodiment, the display device 1060 may be connected to other components via a bus or other communication link.

[0092] Embodiments of the present invention can be applied to any display device and any electronic device including a touch panel. In embodiments, the present invention can be applied to mobile phones, smart phones, digital televisions (TVs), three-dimensional (3D) TVs, personal computers (PCs) (such as tablet computers, laptop computers), home appliances, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, etc.

[0093] The foregoing is an illustration of the present invention and should not be construed as limiting the present invention. Although some embodiments of the present invention have been described, it will be readily understood by those skilled in the art that many modifications may be made without departing substantially from the scope of the present invention. Therefore, all of these modifications are intended to be included within the scope of the present invention. In the claims, any "means plus function clause" is intended to cover the structures described herein as performing the functions described, and includes not only structural equivalents, but also equivalent structures. Therefore, it should be understood that the foregoing is an illustration of the present invention and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the present invention. In addition, embodiments or portions of embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A pixel circuit, wherein: The pixel circuit comprises: a light emitting element including an anode electrode and a cathode electrode receiving a second power voltage; a driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a data writing transistor including a gate electrode receiving a data writing gate signal, a first electrode connected to a data line providing a data voltage, and a second electrode connected to the second node; a compensation transistor including a gate electrode receiving the data write gate signal, a first electrode connected to the third node, and a second electrode connected to the first node; an initialization transistor, comprising a gate electrode receiving an initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a first light emission control transistor including a gate electrode receiving the data write gate signal, a first electrode receiving a first power voltage, and a second electrode connected to the second node; and A storage capacitor includes a first electrode receiving the first power voltage and a second electrode connected to the first node.

2. The pixel circuit according to claim 1, wherein: The data writing transistor is an N-type transistor, and the first light emission controlling transistor is a P-type transistor.

3. The pixel circuit according to claim 2, wherein: The data writing transistor and the first light emission controlling transistor form a complementary metal oxide semiconductor.

4. The pixel circuit according to claim 1, wherein: The pixel circuit further includes: The second light emission control transistor includes a gate electrode receiving the data write gate signal, a first electrode connected to the third node, and a second electrode connected to the anode electrode.

5. The pixel circuit according to claim 4, wherein: The compensation transistor is an N-type transistor, and the second light emission control transistor is a P-type transistor.

6. The pixel circuit according to claim 5, wherein: The compensation transistor and the second light emission control transistor form a complementary metal oxide semiconductor.

7. The pixel circuit according to claim 4, wherein: In a first period, the initialization gate signal and the data write gate signal have a high voltage level.

8. The pixel circuit according to claim 7, wherein: In the first period, the initialization transistor supplies the initialization voltage to the first node, and the initialization transistor and the compensation transistor supply the initialization voltage to the third node.

9. The pixel circuit according to claim 7, wherein: In a second period after the first period, the initialization gate signal has a low voltage level, and the data write gate signal has the high voltage level.

10. The pixel circuit according to claim 9, wherein: In the second period, the data voltage is provided to the gate electrode of the driving transistor through the data writing transistor, the driving transistor, and the compensation transistor.

11. The pixel circuit according to claim 9, wherein: In the second period, when the compensation transistor is turned on, the compensation transistor is diode-connected to the driving transistor.

12. The pixel circuit according to claim 9, wherein: In a third period after the second period, the initialization gate signal has the low voltage level, and the data write gate signal has a low voltage level.

13. The pixel circuit according to claim 12, wherein: In the third period, the driving current of the driving transistor flows to the light emitting element.

Images