Pixel circuit

Abstract

A pixel circuit includes: a light emitting element including an anode electrode and a cathode electrode configured to receive a second power voltage; a driving transistor including a gate electrode connected to the first node, a first electrode connected to the second node, and a second electrode connected to the third node; a compensation transistor including a gate electrode configured to receive a compensation gate signal, a first electrode configured to receive a ground voltage, and a second electrode connected to the third node; a data write transistor including a gate electrode configured to receive a data write gate signal, a first electrode connected to a data line, and a second electrode connected to the first node; a first light emission control transistor including a first electrode configured to receive a first power voltage and a second electrode connected to the second node; a storage capacitor; and a holding capacitor.

Description

Technical Field

[0001] Embodiments supported by aspects of the present disclosure relate to pixel circuits. Background Art

[0002] Generally, a display device may include a display panel and a display panel driver. The display panel may include a gate line, a data line, an emission line, and a pixel circuit. The display panel driver may include a gate driver for providing a gate signal to the gate line, a data driver for providing a data voltage to the data line, an emission driver for providing an emission signal to the emission line, and a drive controller for controlling the gate driver, the data driver, and the emission driver.

[0003] Recently, display devices capable of providing virtual reality (VR) or augmented reality (AR) have become increasingly prominent. To this end, target specifications for display devices may include small area and high PPI (pixels per inch). In this case, due to the narrowing of the spacing occupied by the pixel circuit, the narrowing of the spacing may limit the number of transistors constituting the pixel circuit and the signal applied to the pixel circuit.

[0004] In some aspects, as the PPI increases, the data range of the data voltage may decrease. That is, as the PPI increases, the brightness accuracy according to the change of the data voltage may be relatively reduced. Summary of the invention

[0005] Embodiments of the present disclosure provide a pixel circuit with a small area and a high PPI.

[0006] In an embodiment of a pixel circuit according to an aspect of the present disclosure, the pixel circuit includes: a light-emitting element including an anode electrode and a cathode electrode, wherein the cathode electrode is configured to receive a second power voltage; a driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a compensation transistor including a gate electrode configured to receive a compensation gate signal, a first electrode configured to receive a ground voltage, and a second electrode connected to the third node; a data write transistor including a gate electrode configured to receive a data write gate signal, a first electrode connected to a data line configured to provide a reference voltage or a data voltage, and a second electrode connected to the first node; a first light emission control transistor including a gate electrode configured to receive the compensation gate signal, a first electrode configured to receive a first power voltage, and a second electrode connected to the second node; a storage capacitor including a first electrode connected to the second node and a second electrode connected to the first node; and a holding capacitor including a first electrode configured to receive the ground voltage and a second electrode connected to the second node.

[0007] In an embodiment, the compensation transistor may be an N-type transistor, and the first light emission control transistor may be a P-type transistor.

[0008] In an embodiment, the compensation transistor and the first light emission control transistor may form a complementary metal oxide semiconductor (CMOS) transistor.

[0009] In an embodiment, the pixel circuit may further include: a second light emission control transistor including a gate electrode configured to receive an emission signal, a first electrode connected to the third node, and a second electrode connected to the anode electrode.

[0010] In an embodiment, the driving transistor and the data writing transistor may be P-type transistors, and the second light emission control transistor may be a P-type transistor.

[0011] In an embodiment, in a first period, the compensation gate signal and the data write gate signal may have a low voltage level, the emission signal may have a high voltage level, and the data line may be configured to provide the reference voltage.

[0012] In an embodiment, in the first period, the data write transistor may be configured to provide the reference voltage to the gate electrode of the drive transistor.

[0013] In an embodiment, in a second cycle after the first cycle, the compensation gate signal and the emission signal may have the high voltage level, the data write gate signal may have the low voltage level, and the data line may be configured to provide the reference voltage.

[0014] In an embodiment, in the second period, the compensation transistor is turned on, and the storage capacitor may store a threshold voltage of the driving transistor.

[0015] In an embodiment, in a third period after the second period, the compensation gate signal and the emission signal may have the high voltage level, the data write gate signal may have the low voltage level, and the data line may be configured to provide the data voltage.

[0016] According to the pixel circuit, since some transistors included in the pixel circuit may be N-type transistors, the leakage current of the pixel circuit can be minimized. Since the compensation transistor and the first light emission control transistor form a CMOS transistor, the area of ​​the pixel circuit can be reduced. Since the drive transistor operates as a source follower, the threshold voltage of the drive transistor can be compensated. Since the voltage at the first electrode of the drive transistor is distributed by the storage capacitor and the holding capacitor, the data range can be expanded. Since the second light emission control transistor is turned off in a non-light emission period that does not include a light emission period, the light emitting element can be prevented from emitting light due to the leakage current flowing into the light emitting element. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other features of the embodiments supported by aspects of the present disclosure will become more apparent by describing the embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0018] Figure 1 is a block diagram showing a display device according to an embodiment supported by aspects of the present disclosure;

[0019] Figure 2A The present invention is a diagram showing one or more embodiments of the present invention. Figure 1 A circuit diagram of an example of a pixel circuit;

[0020] Figure 2B Is shown driving Figure 2A A timing diagram of an example of a pixel circuit;

[0021] Figure 2C It is shown Figure 2A A timing diagram showing an example of operation of a pixel circuit in a first cycle;

[0022] Figure 2D It is shown Figure 2A A circuit diagram of an example of a pixel circuit operating in a first cycle;

[0023] Figure 2E It is shown Figure 2A A timing diagram showing an example of operation of a pixel circuit in a second cycle;

[0024] Figure 2F It is shown Figure 2A A circuit diagram of an example of a pixel circuit operating in a second cycle;

[0025] Figure 2G It is shown Figure 2A A timing diagram showing an example of the pixel circuit operating in a third cycle;

[0026] Figure 2H It is shown Figure 2A A circuit diagram of an example of a pixel circuit operating in a third cycle;

[0027] Fig.2I It is shown Figure 2A A timing diagram showing an example of the pixel circuit operating in a fourth cycle;

[0028] Figure 2J It is shown Figure 2A A circuit diagram of an example of a pixel circuit operating in a fourth cycle;

[0029] Figure 3A The present invention is a diagram showing one or more embodiments of the present invention. Figure 1 A circuit diagram of an example of a pixel circuit;

[0030] Figure 3B It is shown Figure 3A A timing diagram of an example of the operation of a pixel circuit;

[0031] Figure 3C It is shown Figure 3A A timing diagram showing an example of operation of a pixel circuit in a first cycle;

[0032] Figure 3D It is shown Figure 3A A circuit diagram of an example of a pixel circuit operating in a first cycle;

[0033] Figure 3E It is shown Figure 3A A timing diagram showing an example of operation of a pixel circuit in a second cycle;

[0034] Figure 3F It is shown Figure 3A A circuit diagram of an example of a pixel circuit operating in a second cycle;

[0035] Figure 3G It is shown Figure 3A A timing diagram showing an example of the pixel circuit operating in a third cycle;

[0036] Figure 3H It is shown Figure 3A A circuit diagram of an example of a pixel circuit operating in a third cycle;

[0037] Fig. 3I It is shown Figure 3A A timing diagram showing an example of the pixel circuit operating in a fourth cycle;

[0038] Figure 3J It is shown Figure 3A A circuit diagram of an example of a pixel circuit operating in a fourth cycle;

[0039] Figure 4 is a block diagram showing an electronic device; and

[0040] Figure 5It shows that Figure 4 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a VR device. DETAILED DESCRIPTION

[0041] Hereinafter, the embodiments supported by the present disclosure will be described more fully with reference to the accompanying drawings, in which one or more example embodiments are shown. However, the aspects supported by the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these example embodiments are provided so that the present disclosure will be comprehensive and complete, and the scope of the example aspects of the present invention will be fully conveyed to those skilled in the art.

[0042] Various components may be described using terms such as "first" and "second" as examples, but these components should not be limited by the terms. Terms as used herein may distinguish one component from other components and are not limited by the terms. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the present disclosure. Unless otherwise specified, terms in the singular may include plural forms.

[0043] The terms used herein are for the purpose of describing specific embodiments and are not intended to be restrictive. Unless the context clearly indicates otherwise, "one", "one (kind / person)", "the (said)" and "at least one (kind / person)" as used herein do not represent a limitation on quantity, and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "an element" has the same meaning as "at least one element". "At least one (kind / person)" is not interpreted as being limited to "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when used in this specification, the term "comprises and / or comprising" or "includes and / or including" indicates the presence of stated features, regions, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, components and / or combinations thereof.

[0044] As used herein, the term "substantially" means approximately or practically. The term "substantially equal" means approximately equal or practically equal. The term "substantially identical" means approximately identical or practically identical. The term "substantially similar" means approximately similar or practically similar. The term "substantially perpendicular" means approximately perpendicular or practically perpendicular.

[0045] For ease of description, as shown in the accompanying drawings, spatial relative terms, such as "under", "below", "below", "above", and "on" may be used herein to describe the relationship of one element or feature to another element or feature. It will be understood that in addition to the orientations depicted in the accompanying drawings, spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as "below" or "below" other elements or features will then be oriented "above" other elements or features. Therefore, the term "below" can cover both above and below. The device can be oriented in other ways (rotated 90 degrees or at other orientations) and the spatial relative descriptors used in this article are interpreted accordingly.

[0046] Embodiments are described herein with reference to cross-sectional views as schematic diagrams of example embodiments. Thus, variations in the shapes of the diagrams due to, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the zones shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, a zone shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the zones shown in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones, nor are they intended to limit the scope of the present disclosure.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless explicitly defined as such in this specification, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formalized sense.

[0048] It should be understood that the various embodiments of the present disclosure and the terms used in the various embodiments of the present disclosure are not intended to limit the technical features set forth herein to specific embodiments, and include various variations, equivalents or substitutes of the corresponding embodiments. With regard to the description of the accompanying drawings, the same reference numerals may be used to refer to similar or related elements. It will be understood that, unless the relevant context clearly indicates otherwise, the singular form of the noun corresponding to the article may include one or more things. As used herein, each such phrase in "A or B", "at least one of A and B", "at least one of A and B", "A, B or C", "at least one of A, B and C", and "at least one of A, B and C" may include any one or all possible combinations of the corresponding one of the items listed together in the phrase.

[0049] It will be understood that, regardless of whether the term "operably" or "communicably" is present, if an element (e.g., a first element) is referred to as being "coupled to" another element (e.g., a second element), "coupled to" another element (e.g., the second element), "connected to" another element (e.g., the second element), or "connected to" another element (e.g., the second element), this means that the element can be coupled to the other element directly (e.g., by wire), wirelessly, or via a third element.

[0050] Hereinafter, the present disclosure will be described in more detail with reference to the accompanying drawings.

[0051] Figure 1 is a block diagram illustrating a display device according to an embodiment supported by aspects of the present disclosure.

[0052] Reference Figure 1 The display device 10 may include a display panel 100 and a display panel driver. The display panel driver may include a driving controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and an emission driver 600.

[0053] In an example, the driving controller 200 and the data driver 500 may be integrally formed. In an example, the driving controller 200, the gamma reference voltage generator 400, and the data driver 500 may be integrally formed. In an example, the driving controller 200, the gate driver 300, the gamma reference voltage generator 400, and the data driver 500 may be integrally formed. In an example, the driving controller 200, the gate driver 300, the gamma reference voltage generator 400, and the data driver 500 may be integrally formed. In an example, the driving controller 200, the gate driver 300, the gamma reference voltage generator 400, the data driver 500, and the emission driver 600 may be integrally formed. The driving module in which at least the driving controller 200 and the data driver 500 are integrally formed may be referred to as a timing controller embedded data driver (TED).

[0054] The display panel 100 may include a display area for displaying an image and a peripheral area disposed adjacent to the display area.

[0055] In an example, in the present embodiment, the display panel 100 may be an organic light emitting diode display panel including an organic light emitting diode. For example, the display panel 100 may be a quantum dot organic light emitting diode display panel including an organic light emitting diode and a quantum dot color filter. For example, the display panel 100 may be a quantum dot nano light emitting diode display panel including a nano light emitting diode and a quantum dot color filter.

[0056] The display panel 100 may include gate lines GL, data lines DL, emission lines EML, and pixel circuits P electrically connected to the gate lines GL, data lines DL, and emission lines EML, respectively. The gate lines GL may extend in a first direction, the data lines DL may extend in a second direction crossing the first direction, and the emission lines EML may extend in the first direction.

[0057] The driving controller 200 may receive input image data IMG and an input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0058] The driving controller 200 may generate a first control signal CONT1 , a second control signal CONT2 , a third control signal CONT3 , a fourth control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0059] The driving controller 200 may generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0060] The driving controller 200 may generate a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and the driving controller 200 may output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0061] The driving controller 200 may generate a data signal DATA based on the input image data IMG. The driving controller 200 may output the data signal DATA to the data driver 500.

[0062] The driving controller 200 may generate a third control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT, and the driving controller 200 may output the third control signal CONT3 to the gamma reference voltage generator 400 .

[0063] The driving controller 200 may generate a fourth control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT, and the driving controller 200 may output the fourth control signal CONT4 to the emission driver 600 .

[0064] The gate driver 300 may generate a gate signal for driving the gate line GL in response to the first control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signal to the gate line GL.

[0065] In an embodiment, the gate driver 300 may be integrated at a peripheral area of ​​the display panel 100 .

[0066] The gamma reference voltage generator 400 may generate a gamma reference voltage VGREF in response to the third control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 may provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF may have a value corresponding to each data signal DATA.

[0067] In an example, the gamma reference voltage generator 400 may be provided in the driving controller 200 or may be provided in the data driver 500 .

[0068] The data driver 500 may receive the second control signal CONT2 and the data signal DATA from the driving controller 200, and the data driver 500 may receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 may convert the data signal DATA into an analog type data voltage (e.g., a data voltage VDATA described later herein) using the gamma reference voltage VGREF. The data driver 500 may output the data voltage to the data line DL.

[0069] The emission driver 600 may generate an emission signal for driving the emission lines EML in response to the fourth control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal to the emission lines EML.

[0070] In an embodiment, the emission driver 600 may be integrated into a peripheral area of ​​the display panel 100. In an embodiment, the emission driver 600 may be mounted on a peripheral area of ​​the display panel 100.

[0071] exist Figure 1 In the embodiment, for ease of explanation, the gate driver 300 may be disposed on a first side of the display panel 100, and the emission driver 600 may be disposed on a second side of the display panel 100. Although shown, the exemplary embodiments supported by the present disclosure are not limited thereto. For example, both the gate driver 300 and the emission driver 600 may be disposed on a first side of the display panel 100. In another example, both the gate driver 300 and the emission driver 600 may be disposed on both sides of the display panel 100. In another example, the gate driver 300 and the emission driver 600 may be disposed on different sides of the display panel 100, respectively. For example, the gate driver 300 and the emission driver 600 may be formed as one body.

[0072] Figure 2A The present invention is a diagram showing one or more embodiments of the present invention. Figure 1 A circuit diagram of an example of a pixel circuit. Figure 2B Is shown driving Figure 2A A timing diagram of an example of a pixel circuit.

[0073] Reference Figures 1 to 2B The pixel circuit P may include a light emitting element EE, a driving transistor T1, a compensation transistor T2, a data writing transistor T3, a first light emission control transistor T4, a storage capacitor CST and a holding capacitor CHOLD. In an embodiment, the pixel circuit P may further include a second light emission control transistor T5.

[0074] The light emitting element EE may include an anode electrode and a cathode electrode configured to receive the second power voltage ELVSS.

[0075] The driving transistor T1 may include a gate electrode connected to the first node N1 , a first electrode connected to the second node N2 , and a second electrode connected to the third node N3 .

[0076] The compensation transistor T2 may include a gate electrode configured to receive the compensation gate signal GC, a first electrode configured to receive the ground voltage VGND, and a second electrode connected to the third node N3.

[0077] The data write transistor T3 may include a gate electrode configured to receive a data write gate signal GW, a first electrode connected to a data line DL configured to provide a reference voltage VREF or a data voltage VDATA, and a second electrode connected to a first node N1.

[0078] The first light emission control transistor T4 may include a gate electrode configured to receive the compensation gate signal GC, a first electrode configured to receive the first power voltage ELVDD, and a second electrode connected to the second node N2.

[0079] The storage capacitor CST may include a first electrode connected to the second node N2 and a second electrode connected to the first node N1.

[0080] The holding capacitor CHOLD may include a first electrode configured to receive the ground voltage VGND and a second electrode connected to the second node N2 .

[0081] The second light emission control transistor T5 may include a gate electrode configured to receive the emission signal EM, a first electrode connected to the third node N3, and a second electrode connected to the anode electrode.

[0082] In some cases, leakage current may occur more in a P-type transistor than in an N-type transistor. Therefore, some transistors included in the pixel circuit P may be N-type transistors that can reduce the total amount of leakage current of the pixel circuit P. In an embodiment, the compensation transistor T2 may be an N-type transistor, and the first light emission control transistor T4 may be a P-type transistor. In an embodiment, the drive transistor T1 and the data write transistor T3 may be a P-type transistor, and the second light emission control transistor T5 may be an N-type transistor. In an embodiment, the compensation transistor T2 and the first light emission control transistor T4 may form a complementary metal oxide semiconductor (CMOS) transistor. Therefore, compared with some other pixel circuits, the embodiment of the pixel circuit P according to one or more embodiments of the present disclosure supports a reduced number of gate signals and a reduced number of lines for transmitting gate signals, and the area is reduced accordingly. In an example where the signal applied to the gate electrode of the P-type transistor has a low voltage level, the P-type transistor may be turned on. In an example where the signal applied to the gate electrode of the P-type transistor has a high voltage level, the P-type transistor may be turned off. In an example where the signal applied to the gate electrode of the N-type transistor has a high voltage level, the N-type transistor may be turned on. In an example where a signal applied to the gate electrode of the N-type transistor has a low voltage level, the N-type transistor may be turned off.

[0083] In the first period P1 , the compensation gate signal GC and the data write gate signal GW may have a low voltage level, the emission signal EM may have a high voltage level, and the data line DL may provide the reference voltage VREF.

[0084] In a second period P2 after the first period P1 , the compensation gate signal GC and the emission signal EM may have a high voltage level, the data write gate signal GW may have a low voltage level, and the data line DL may provide the reference voltage VREF.

[0085] In a third period P3 after the second period P2 , the compensation gate signal GC and the emission signal EM may have a high voltage level, the data write gate signal GW may have a low voltage level, and the data line DL may provide the data voltage VDATA.

[0086] In a fourth period P4 after the third period P3 , the compensation gate signal GC and the emission signal EM may have a low voltage level, the data write gate signal GW may have a high voltage level, and the data line DL may provide the reference voltage VREF.

[0087] The terms "high voltage level" and "low voltage level" are relative terms that describe levels of voltage that, when applied to the transistors described herein, activate the transistors (e.g., turn them on) or disable the transistors (e.g., turn them off).

[0088] It will be understood that the periods described herein (e.g., the first period P1 to the fourth period P4, etc.) may be periods of time. In some cases, the respective amount of time associated with a given period (e.g., the first period P1) may be equal to or different from the respective amount of time associated with another given period (e.g., the second period P2 or the third period P3, etc.).

[0089] Figure 2C It is shown Figure 2A 1 is a timing diagram of an example of operation of a pixel circuit in a first cycle. Figure 2D It is shown Figure 2A A circuit diagram of an example of a pixel circuit operating in a first cycle.

[0090] Reference Figures 1 to 2D , in the first period P1, the data writing transistor T3 and the first light emission control transistor T4 may be turned on, and the compensation transistor T2 and the second light emission control transistor T5 may be turned off.

[0091] When the data line DL provides the reference voltage VREF and the data write transistor T3 is turned on, the data write transistor T3 can provide the reference voltage VREF to the first node N1 (i.e., the gate electrode of the driving transistor T1). The first node N1 can be initialized to the reference voltage VREF. The reference to the data line DL providing the described voltage (e.g., the reference voltage VREF, the data voltage VDATA) includes a data driver 500 that provides the described voltage via the data line DL.

[0092] A path may be formed by the first light emission control transistor T4 and the driving transistor T1. The second node N2 and the third node N3 may be initialized by the path. For example, the second node N2 may be initialized to the first power voltage ELVDD.

[0093] Figure 2E It is shown Figure 2A 1 is a timing diagram of an example of the pixel circuit operating in the second cycle. Figure 2F It is shown Figure 2A A circuit diagram of an example of a pixel circuit operating in the second period.

[0094] Reference Figures 1 to 2F , in the second period P2, the compensation transistor T2 and the data writing transistor T3 may be turned on, and the first light emission control transistor T4 and the second light emission control transistor T5 may be turned off.

[0095] When the data line DL provides the reference voltage VREF and the data write transistor T3 is turned on, the data write transistor T3 may provide the reference voltage VREF to the first node N1 .

[0096] When the compensation transistor T2 is turned on, a path through the driving transistor T1 and the compensation transistor T2 may be formed, and the driving transistor T1 may operate as a source follower. In an example where the driving transistor T1 operates as a source follower, the voltage at the second node N2 may be transferred from ELVDD to VREF+VTH. Here, VTH may be the threshold voltage of the driving transistor T1. Therefore, the storage capacitor CST may store the threshold voltage (VTH) of the driving transistor T1, and therefore, the threshold voltage (VTH) of the driving transistor T1 may be compensated.

[0097] Figure 2G It is shown Figure 2A A timing diagram of an example in which the pixel circuit of FIG. 1 operates in the third cycle. Figure 2H It is shown Figure 2A A circuit diagram of an example in which a pixel circuit operates in a third cycle.

[0098] Reference Figures 1 to 2H , in the third period P3, the compensation transistor T2 and the data writing transistor T3 may be turned on, and the first light emission control transistor T4 and the second light emission control transistor T5 may be turned off.

[0099] When the data line DL provides the data voltage VDATA and the data write transistor T3 is turned on, the data write transistor T3 may provide the data voltage VDATA to the first node N1.

[0100] The voltage at the first node N1 can be transferred from the reference voltage VREF to the data voltage VDATA. Therefore, the voltage at the second node N2 (i.e., the voltage at the first electrode of the driving transistor T1) can be boosted by the storage capacitor CST. In some embodiments, the voltage at the second node N2 (i.e., the voltage at the gate electrode of the driving transistor T1) can be distributed by the storage capacitor CST and the holding capacitor CHOLD. The driving current of the driving transistor T1 can be determined based on the gate-source voltage of the driving transistor T1. Since the voltage at the second node N2 is distributed by the storage capacitor CST and the holding capacitor CHOLD, even in the case where the data voltage VDATA increases, the resulting degree of increase in the gate-source voltage of the driving transistor T1 can be small. Therefore, an embodiment of the pixel circuit P can support an extended data range of the data voltage VDATA.

[0101] In some embodiments, since the second light emission control transistor T5 is turned off in the first to third periods P1 to P3, light emission through the light emitting element EE due to leakage current flowing to the light emitting element EE may be prevented.

[0102] Fig.2I It is shown Figure 2A A timing diagram of an example of the pixel circuit operating in the fourth cycle. Figure 2J It is shown Figure 2A A circuit diagram of an example in which a pixel circuit operates in a fourth cycle.

[0103] Reference Figures 1 to 2J , in the fourth period P4, the first light emission control transistor T4 and the second light emission control transistor T5 may be turned on, and the compensation transistor T2 and the data writing transistor T3 may be turned off.

[0104] The voltage at the first node N1 may be determined based on the data voltage VDATA, the driving current of the driving transistor T1 may be determined based on the voltage at the first node N1 and the voltage at the second node N2, and the driving transistor T1 may provide the driving current to the light emitting element EE. The light emitting element EE may emit light with brightness corresponding to the driving current.

[0105] Therefore, since some transistors included in the pixel circuit P are N-type transistors, the leakage current of the pixel circuit P can be minimized. Since the compensation transistor T2 and the first light emission control transistor T4 form a CMOS transistor, the area of ​​the pixel circuit P can be reduced. Since the driving transistor T1 operates as a source follower, the threshold voltage of the driving transistor T1 can be compensated. Since the voltage at the first electrode of the driving transistor T1 is distributed through the storage capacitor CST and the holding capacitor CHOLD, the embodiment of the present disclosure can support an expanded data range. Since the second light emission control transistor T5 is turned off during a non-emission period that does not include a light emission period, light emission through the light emitting element EE due to leakage current flowing into the light emitting element EE can be prevented.

[0106] Figure 3A The present invention is a diagram showing one or more embodiments of the present invention. Figure 1 A circuit diagram of an example of a pixel circuit. Figure 3B It is shown Figure 3A A timing diagram of an example of the operation of a pixel circuit. Figure 3C It is shown Figure 3A 1 is a timing diagram of an example of operation of a pixel circuit in a first cycle. Figure 3D It is shown Figure 3A A circuit diagram of an example of a pixel circuit operating in a first cycle. Figure 3E It is shown Figure 3A 1 is a timing diagram of an example of the pixel circuit operating in the second cycle. Figure 3F It is shown Figure 3A A circuit diagram of an example of a pixel circuit operating in the second period. Figure 3G It is shown Figure 3A A timing diagram of an example in which the pixel circuit of FIG. 1 operates in the third cycle. Figure 3H It is shown Figure 3A A circuit diagram of an example in which a pixel circuit operates in a third cycle. Fig. 3I It is shown Figure 3A A timing diagram of an example of the pixel circuit operating in the fourth cycle. Figure 3J It is shown Figure 3A A circuit diagram of an example in which a pixel circuit operates in a fourth cycle.

[0107] Figure 3A The pixel circuit P' may include a reference Figure 2A In describing aspects of the pixel circuit P, repeated descriptions of the same elements may be omitted for the sake of brevity. Figures 1 to 3J, except that the gate electrode of the data write transistor T3 and the gate electrode of the second light emission control transistor T5 are configured to commonly receive the data write gate signal GW, the data write transistor T3 is an N-type transistor, the second light emission control transistor T5 is a P-type transistor, and the data write transistor T3 and the second light emission control transistor T5 form a CMOS transistor, Figure 3A The pixel circuit P' and Figure 2A The pixel circuit P is basically the same. Since the data writing transistor T3 and the second light emission control transistor T5 form Figure 3A The CMOS transistor in the pixel circuit P' is therefore Figure 2A Compared with the area of ​​the pixel circuit P, Figure 3A The area of ​​the pixel circuit P' can be further reduced.

[0108] Since the gate electrode of the data writing transistor T3 and the gate electrode of the second light emission controlling transistor T5 commonly receive the data writing gate signal GW, it is possible to write the data to the transistor T3 without the reference signal GW. Figure 2A The pixel circuit P described above is implemented in the case of the emission signal EM Figure 3A Example operation of the pixel circuit P'. For example, Figure 2B The timing diagram is different. Figure 3B The timing diagram of the emission signal EM is omitted in the timing diagram of the data write gate signal GW. However, the phase of the data write gate signal GW may be opposite to the phase of the emission signal EM. Figure 3C to Figure 3J In Figure 3A The operation of the pixel circuit P' can be compared with the Figure 2C to Figure 2J middle Figure 2A The operation of the pixel circuit P is substantially the same. Therefore, the description of Figure 3A The redundant description of the pixel circuit P'.

[0109] Figure 4 is a block diagram illustrating an electronic device. Figure 5 It shows that Figure 4 FIG. 1 is a diagram of an embodiment in which the electronic device is implemented as a VR device.

[0110] Reference Figure 4 and Figure 5 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 The display device 10. In some aspects, the electronic device 1000 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, another electronic device, and the like.

[0111] In an embodiment, as in Figure 5 As shown in , the electronic device 1000 can be implemented as a VR device. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet personal computer (PC), a car navigation system, a computer monitor, a notebook computer, and a head mounted display (HMD) device, etc.

[0112] The processor 1010 may perform various computing functions. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, and a data bus, etc. In addition, the processor 1010 may be coupled to an extended bus such as a peripheral component interconnect (PCI) bus. The term "coupling" herein may refer to electrical coupling or electrical connection. The term "coupling" may refer to a physical connection that supports electrical coupling or electrical connection.

[0113] The memory device 1020 may store data for operation of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device, etc.).

[0114] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a compact disk read only memory (CD-ROM) device, and the like.

[0115] I / O device 1040 may include input devices (such as keyboard, keypad, mouse device, touch pad and touch screen) and output devices (such as printer and speaker). In some embodiments, I / O device 1040 may include display device 1060.

[0116] The power supply 1050 may provide power for the operation of the electronic device 1000 .

[0117] The display device 1060 may be connected to other components via a bus or other communication links.

[0118] The inventive concept can be applied to any display device and any electronic device including a touch panel. For example, the inventive concept can be applied to a mobile phone, a smart phone, a digital television (TV), a 3D TV, a personal computer (PC) (e.g., a tablet computer or a notebook computer), a home appliance, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, or a navigation device, etc.

[0119] The above contents are exemplary embodiments supported by the present disclosure and are not to be construed as limitations on the present disclosure. Although the exemplary embodiments supported by aspects of the present disclosure have been described, it will be readily understood by those skilled in the art that many modifications may be made to the embodiments without substantially departing from the novel teachings and advantages of the embodiments of the present disclosure described herein. Therefore, all of these modifications are intended to be included within the scope of the exemplary embodiments and aspects supported by the aspects of the present disclosure defined in the claims. In the claims, the means plus function clause is intended to cover the structures described herein that perform the functions described, and not only structural equivalents, but also equivalent structures. Therefore, it should be understood that the above contents are descriptions of the exemplary embodiments supported by the present disclosure, and are not to be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims, and the equivalents of the claims are included in the inventive concept.

Claims

1. A pixel circuit, wherein: The pixel circuit comprises: a light emitting element comprising an anode electrode and a cathode electrode, wherein the cathode electrode is configured to receive a second power voltage; a driving transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a compensation transistor comprising a gate electrode configured to receive a compensation gate signal, a first electrode configured to receive a ground voltage, and a second electrode connected to the third node; a data writing transistor including a gate electrode configured to receive a data writing gate signal, a first electrode connected to a data line configured to provide a reference voltage or a data voltage, and a second electrode connected to the first node; a first light emission control transistor including a gate electrode configured to receive the compensation gate signal, a first electrode configured to receive a first power voltage, and a second electrode connected to the second node; a storage capacitor including a first electrode connected to the second node and a second electrode connected to the first node; and A holding capacitor includes a first electrode configured to receive the ground voltage and a second electrode connected to the second node.

2. The pixel circuit according to claim 1, wherein: The compensation transistor is an N-type transistor, and the first light emission control transistor is a P-type transistor.

3. The pixel circuit according to claim 2, wherein: The compensation transistor and the first light emission control transistor form a complementary metal oxide semiconductor transistor.

4. The pixel circuit according to claim 1, wherein: The pixel circuit further includes: The second light emission control transistor includes a gate electrode configured to receive an emission signal, a first electrode connected to the third node, and a second electrode connected to the anode electrode.

5. The pixel circuit according to claim 4, wherein: The driving transistor and the data writing transistor are P-type transistors, and the second light emission controlling transistor is a P-type transistor.

6. The pixel circuit according to claim 4, wherein: In a first period, the compensation gate signal and the data write gate signal have a low voltage level, the emission signal has a high voltage level, and the data line is configured to provide the reference voltage.

7. The pixel circuit according to claim 6, wherein: In the first period, the data write transistor is configured to provide the reference voltage to the gate electrode of the drive transistor.

8. The pixel circuit according to claim 6, wherein: In a second cycle after the first cycle, the compensation gate signal and the emission signal have the high voltage level, the data write gate signal has the low voltage level, and the data line is configured to provide the reference voltage.

9. The pixel circuit according to claim 8, wherein: In the second period, the compensation transistor is turned on, and the storage capacitor stores a threshold voltage of the driving transistor.

10. The pixel circuit according to claim 8, wherein: In a third period after the second period, the compensation gate signal and the emission signal have the high voltage level, the data write gate signal has the low voltage level, and the data line is configured to provide the data voltage.

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