Pixel and display device

Abstract

The invention relates to a pixel and a display device. The pixel includes: a light emitting element; a first transistor connected between a first voltage line and the light emitting element; a second transistor connected between the first voltage line and the first transistor; a third transistor connected between the first transistor and the light emitting element; and a fourth transistor connected between the light emitting element and a second voltage line, in which the pixel is configured to emit light in a plurality of emission periods between a plurality of non-emission periods during one frame, and in a plurality of even non-emission periods among the plurality of non-emission periods, the second transistor is turned off, and in a plurality of even non-emission periods among the plurality of non-emission periods, the fourth transistor is turned off. And the third transistor is conducted.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0128493 filed in the Korean Intellectual Property Office on September 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a pixel and a display device including the pixel. Background Art

[0004] Recently, the use of display devices has been diversified. As display devices have become thinner and lighter, the uses of display devices are gradually expanding.

[0005] As display devices are variously utilized, there are various methods of designing the shape of the display devices, and functions combined with or associated with the display devices have increased. Summary of the invention

[0006] One or more embodiments include a display device capable of improving display quality. However, such technical goals are only examples, and the embodiments are not limited thereto.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the embodiments.

[0008] According to one or more embodiments, a pixel may include: a light emitting element; a first transistor connected between a first voltage line and the light emitting element; a second transistor connected between the first voltage line and the first transistor; a third transistor connected between the first transistor and the light emitting element; and a fourth transistor connected between the light emitting element and the second voltage line. The pixel may be configured to emit light in a plurality of emission periods between a plurality of non-emission periods during a frame, and in a plurality of even-numbered non-emission periods among the plurality of non-emission periods, the second transistor may be turned off and the third transistor may be turned on.

[0009] The pixel may be configured to emit light in at least four emission periods among the plurality of emission periods during the one frame.

[0010] The fourth transistor can be turned on in multiple odd non-emission time periods among the multiple non-emission time periods, and among the multiple odd non-emission time periods, the time period during which the fourth transistor is turned on in each of the odd non-emission time periods except the first non-emission time period can be greater than the time period during which the fourth transistor is turned on in the first non-emission time period.

[0011] In a portion of the period during each of the plurality of odd-numbered non-emission periods in which the fourth transistor is turned on, the second transistor may be turned off and the third transistor may be turned on.

[0012] During the odd non-emission periods other than the first non-emission period among the plurality of odd non-emission periods, the fourth transistor may be switched from the off state to the on state after the third transistor is switched from the on state to the off state.

[0013] The first non-emission period may include: a writing period in which a data signal is supplied to the pixel; a first period before which the fourth transistor is turned on in the first period; and a second period after which the fourth transistor is turned on in the second period, and during a portion of the second period, the second transistor may be turned off and the third transistor may be turned on.

[0014] During the first period, the second transistor may be turned off, and the third transistor may be turned on.

[0015] The pixel may further include: a fifth transistor connected between a third voltage line and a gate of the first transistor, wherein the first non-emission period may further include a third period between the first period and the writing period, and the fifth transistor may be turned on during the first period and the third period.

[0016] During the third period, the second transistor may be turned on, and the third transistor may be turned off.

[0017] The pixel may further include: a first capacitor connected between a gate of the first transistor and a node to which the first transistor and the third transistor are connected; and a second capacitor connected between the first voltage line and the node.

[0018] According to one or more embodiments, a display device may include: a plurality of pixels; and a driving circuit that outputs a gate signal to the plurality of pixels. Each of the plurality of pixels includes: a light-emitting element; a first transistor connected between a first voltage line and the light-emitting element; a second transistor connected between the first voltage line and the first transistor; a third transistor connected between the first transistor and the light-emitting element; and a fourth transistor connected between the light-emitting element and the second voltage line. The plurality of pixels may be configured to emit light in a plurality of emission periods between a plurality of non-emission periods during a frame. The driving circuit may be configured to output a first gate signal of a gate-off voltage to the second transistor in a plurality of even-numbered non-emission periods among the plurality of non-emission periods, and output a second gate signal of a gate-on voltage to the third transistor.

[0019] The plurality of pixels may be configured to emit light in at least four emission periods among the plurality of emission periods during the one frame.

[0020] The driving circuit can be configured to output a third gate signal of a gate-on voltage to the fourth transistor in a plurality of odd non-emission periods among the plurality of non-emission periods, and among the plurality of odd non-emission periods, a period in which the third gate signal is a gate-on voltage in each of the odd non-emission periods except the first non-emission period may be greater than a period in which the third gate signal is a gate-on voltage in the first non-emission period.

[0021] The driving circuit may be configured to output the first gate signal of the gate-off voltage and the second gate signal of the gate-on voltage in a portion of the period in which the third gate signal during each of the plurality of odd-numbered non-emission periods is the gate-on voltage.

[0022] The driving circuit can be configured to: during the odd non-emission period among the multiple odd non-emission period except the first non-emission period, change the second gate signal from the gate-on voltage to the gate-off voltage and output the second gate signal, and then change the third gate signal from the gate-off voltage to the gate-on voltage and output the third gate signal.

[0023] The first non-emission period may include a writing period, a first period before the writing period, and a second period after the writing period, the data signal is supplied to the multiple pixels during the writing period, the third gate signal is a gate-on voltage in the first period, the third gate signal is a gate-on voltage in the second period, and the driving circuit may be configured to output the first gate signal of the gate-off voltage and the second gate signal of the gate-on voltage in a part of the second period.

[0024] The driving circuit may be configured to output the first gate signal of a gate-off voltage and the second gate signal of a gate-on voltage during the first period.

[0025] Each of the multiple pixels may also include a fifth transistor connected between a third voltage line and the gate of the first transistor, wherein the first non-emission period may also include a third period between the first period and the writing period, and the driving circuit may be configured to output a fourth gate signal of a gate-on voltage to the fifth transistor during the first period and the third period.

[0026] The driving circuit may be configured to output the first gate signal of a gate-on voltage and the second gate signal of a gate-off voltage during the third period.

[0027] The driving circuit may be configured to change a period during which the first gate signal is a gate-on voltage and a period during which the first gate signal is a gate-off voltage based on an emission ratio.

[0028] According to one or more embodiments, a method for driving a display device includes: turning on a fourth transistor in an odd non-emission period among a plurality of non-emission periods, wherein, among the odd non-emission periods, the period during which the fourth transistor is turned on in each of the odd non-emission periods except a first non-emission period is greater than the period during which the fourth transistor is turned on in the first non-emission period. The method further includes: during a portion of the period during which the fourth transistor is turned on during each of the odd non-emission periods, the second transistor is turned off and the third transistor is turned on. During the period except the first non-emission period among the odd non-emission periods, the method further includes: after the third transistor is switched from the on state to the off state, the fourth transistor is switched from the off state to the on state.

[0029] In a preferred embodiment of the method, the first non-emission period includes: during a first period, turning on the fourth transistor, turning off the second transistor, and turning on the third transistor; then in a writing period after the first period, supplying a data signal to the pixel; and then in a second period after the writing period, turning on the fourth transistor, and during a part of the second period: turning off the second transistor and turning on the third transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects, features and advantages of some embodiments will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0031] Figure 1A and Figure 1B is a schematic diagram of a display device according to an embodiment;

[0032] Figure 2 is a schematic diagram of a display device according to an embodiment;

[0033] Figure 3A and Figure 3B is a schematic diagram for explaining a method of driving a display device according to a driving frequency;

[0034] Figure 4 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment;

[0035] Figure 5 is a diagram of a signal supplied to a pixel during a first scanning period according to an embodiment;

[0036] Figure 6 yes Figure 5 an enlarged view of a portion of a first scanning period;

[0037] Figure 7 is a diagram of a signal supplied to a pixel during a second scanning period according to an embodiment;

[0038] Figure 8 and Fig. 9 is a view of signals supplied to pixels during a first scanning period and a second scanning period according to a comparative example;

[0039] Fig.10 It is shown in Figure 4 A view showing a difference in flicker characteristics for each frequency in a case where the pixel shown in FIG. 1 is operated according to a comparative example;

[0040] Fig.11 It is shown in Figure 4 A view showing a change in driving voltage when the pixel shown in FIG. 1 is operated according to a comparative example;

[0041] Fig.12 It is shown in Figure 4 A diagram showing the difference in flicker characteristics for each frequency when the pixel shown in FIG. 1 is operated according to an embodiment;

[0042] Fig.13 It is shown in Figure 4 A view of brightness changes in a portion of an image in the case where the pixels shown in FIG. 1 operate according to the embodiment and the comparative example;

[0043] Fig.14A is a view showing a mottle effect (visual unevenness or irregularity) occurring in a portion of an image according to a comparative example;

[0044] Fig. 14B is a view of an image according to an embodiment showing a state in which a streak effect is prevented;

[0045] Fig.15 is a diagram of a signal supplied to a pixel during a first scanning period according to an embodiment;

[0046] Fig.16 is a diagram of a signal supplied to a pixel during a second scanning period according to an embodiment;

[0047] Fig.17 is a schematic cross-sectional view of a structure of a display element according to an embodiment;

[0048] Fig.18A , Fig.18B , Fig. 18C , Fig.18D , Fig.19A and Fig.19B is a schematic cross-sectional view of a structure of a display element according to an embodiment; and

[0049] Fig. 20 is a schematic cross-sectional view of a structure of a pixel of a display device according to an embodiment. DETAILED DESCRIPTION

[0050] Now will be referred to in detail embodiment, the example of embodiment is shown in the accompanying drawings, wherein the same reference numerals represent the same elements from time to time. In this respect, the embodiment can have different forms and should not be construed as being limited to the description set forth in this article. Therefore, the embodiment is described below only by reference to the accompanying drawings to illustrate the various aspects of the description. As used in this article, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. Throughout this disclosure, the statement "at least one of a, b and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or its variations.

[0051] Since the present disclosure allows various changes and many embodiments, specific embodiments will be shown in the drawings and described in the written description. The effects and features of the present disclosure and the methods for achieving these effects and features will be explained with reference to the embodiments described in detail below with reference to the drawings. However, the present disclosure is not limited to the following embodiments and can be implemented in various forms.

[0052] Although terms such as "first" and "second" may be used to describe various elements, these elements should not be limited by the above terms. The above terms are used to distinguish one element from another.

[0053] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0054] It will be understood that the terms “comprising,” “including,” “containing,” and / or “having” as used herein specify the presence of stated features or elements, but do not preclude the addition of one or more other features or elements.

[0055] It will also be understood that when a layer, region or element is referred to as being “on” another layer, region or element, it can be directly or indirectly on the other layer, region or element. For example, intervening layers, regions or elements may be present.

[0056] For convenience of explanation, the size of the elements in the drawings may be exaggerated or reduced. As an example, for convenience of description, the size and thickness of each element shown in the drawings are arbitrarily represented, and therefore, the present disclosure is not necessarily limited thereto.

[0057] In the present specification, "A and / or B" means A or B, or A and B. In the present specification, "at least one of A and B" means A or B, or A and B.

[0058] In the following embodiments, when it is described that X is connected to Y, X may be electrically connected to Y with or without at least one intervening element, X may be functionally connected to Y with or without at least one intervening element, or X may be physically connected to Y with or without at least one intervening element. Here, X and Y may be objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive layers, and various layers, etc.). Therefore, X and Y are not limited to the preset connection relationship and the connection relationship shown and described in the drawings and detailed description, but may include connection relationships other than the connection relationships shown and described in the drawings and detailed description.

[0059] The case where X is electrically connected to Y may include a case where X and Y are directly electrically connected and a case where at least one element (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, etc.) capable of achieving electrical connection between X and Y is connected between X and Y.

[0060] In the following embodiments, "ON" used in relation to the state of an element can represent the valid state of an element, and "OFF" can represent the ineffective state of an element. "ON" used in relation to a signal received by an element can represent a signal that activates an element, and "OFF" can represent a signal that disables an element. An element can be activated by a high level voltage or a low level voltage. As an example, a P-channel transistor (e.g., a P-type transistor) can be activated by a low level voltage, and an N-channel transistor (e.g., an N-type transistor) can be activated by a high level voltage. Therefore, it should be understood that the "ON" voltage for a P-type transistor and an N-type transistor is an opposite (low to high) voltage level.

[0061] In the following embodiments, the x-axis direction, the y-axis direction, and the z-axis direction are not limited to the directions along the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis direction, the y-axis direction, and the z-axis direction can be perpendicular to each other, or can represent different orientations that are not perpendicular to each other.

[0062] The display device according to the embodiment can be used as a display screen for various products, including televisions, notebook computers, monitors, billboards, Internet of Things (IoT) devices, and portable electronic devices, including mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notepads, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs). For example, the display device according to the embodiment can be used in wearable devices, including smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). For example, in an embodiment, the display device can be applied to a dashboard for a car, a display screen for a central dashboard of a car or a central information display (CID) arranged on a dashboard, an interior mirror display instead of a side mirror of a car, and a display of an entertainment system for rear seat passengers arranged on the rear side of the front seats in a car. For example, the display device can be a flexible device.

[0063] Figure 1A and Figure 1B is a schematic diagram of a display device 10 according to an embodiment. Figure 2 is a schematic diagram of a display device 10 according to an embodiment. Figure 3A and Figure 3Bis used to explain how to drive the display device 10 (see Figure 2 ) is a schematic diagram of the method.

[0064] Reference Figure 1A and Figure 1B , the display device 10 may include a display area DA displaying an image and a peripheral area PA outside the display area DA. The display area DA may be surrounded (eg, completely surrounded) by the peripheral area PA.

[0065] In a plan view, the display area DA may have a rectangular shape. In another embodiment, the display area DA may have other polygonal shapes (such as a triangle, a pentagon, and a hexagon, etc.), a circular shape, an elliptical shape, or an irregular shape, etc. The corner portion of the edge portion of the display area DA may have a rounded shape. In an embodiment, the display device 10 may have a Figure 1A In another embodiment, the display device 10 may have a display area DA having a shape in which the length in the x-axis direction is greater than the length in the y-axis direction. Figure 1B The display area DA has a shape in which the length in the y-axis direction is greater than the length in the x-axis direction as shown in FIG. The z-axis direction may be substantially perpendicular to a plane defined by the x-axis direction and the y-axis direction.

[0066] Reference Figure 2 , also refer to Figure 1A and Figure 4 The display device 10 according to the embodiment may include a pixel region 11 , a gate driving circuit 13 , a data driving circuit 15 , a power supply circuit 17 , and a controller 19 .

[0067] The pixel area 11 may be disposed in the display area DA. Various wires for transmitting electrical signals to be applied to the display area DA, external circuits electrically connected to the pixel circuits, and pads to which a printed circuit board or a driver integrated circuit (IC) chip is attached may be located in the peripheral area PA. As an example, a gate drive circuit 13, a data drive circuit 15, a power supply circuit 17, and a controller 19 may be disposed in the peripheral area PA.

[0068] like Figure 2 As shown in FIG. 1 , the gate lines GL, the data lines DL, and the pixels PX connected to the gate lines GL and the data lines DL may be arranged in the display area DA. The pixels PX may be arranged in various configurations / patterns (such as stripe configurations / patterns, The pixel PX may be a pixel circuit that can be configured to display an image. Each pixel PX may include an organic light emitting diode OLED as a display element (or light emitting element), and the organic light emitting diode OLED may be connected to a pixel circuit. The pixel circuit may include a transistor and at least one capacitor. The pixel PX may emit, for example, red light, green light, blue light, or white light from the organic light emitting diode OLED. Each pixel PX may be connected to at least one corresponding gate line among the gate lines GL and a corresponding data line among the data lines DL.

[0069] The gate lines GL may each extend in the x-axis direction (e.g., the row direction) and be connected to the pixels PX arranged in the same row. The gate lines GL may each transmit a gate signal to the pixels PX in the same row. The data lines DL may each extend in the y-axis direction (e.g., the column direction) and be connected to the pixels PX arranged in the same column. The data lines DL may each transmit a data signal to the pixels PX in the same column in synchronization with the gate signal.

[0070] In an embodiment, the peripheral area PA may be a non-display area in which the pixels PX are not arranged. In another embodiment, the pixels PX may be arranged in a portion of the peripheral area PA. As an example, the pixels PX may be arranged in at least one corner portion of the peripheral area PA to overlap with the gate drive circuit 13. Therefore, the dead area may be reduced, and the display area DA may be expanded.

[0071] The gate drive circuit 13 may be connected to the gate line GL, generate a gate signal GS according to a control signal GCS from the controller 19, and sequentially supply the gate signal GS to the gate line GL. The gate line GL may be connected to the gate of the transistor included in the pixel PX. The gate signal may be a gate control signal for controlling the on operation and the off operation of the transistor whose gate is connected to the gate line GL. The gate signal may be a signal including an on voltage (or on voltage) by which the transistor may be turned on and an off voltage (or off voltage) by which the transistor may be turned off.

[0072] Despite Figure 2 , the case where the pixel PX is connected to one gate line GL is shown, but this is an example. The pixel PX may be connected to two or more gate lines, and the gate driving circuit 13 may supply two or more gate signals having different timings at which a turn-on voltage is applied to the corresponding gate lines.

[0073] The data driving circuit 15 may be connected to the data line DL and supply a data signal to the data line DL according to a control signal DCS from the controller 19. The data signal supplied to the data line DL may be supplied to the pixel PX supplied with the gate signal. The data driving circuit 15 may convert the input image data DATA into a data signal in a voltage form or a current form. For example, the input image data DATA may have a gray scale and is input from the controller 19. Figure 2 An example is shown in which the data driving circuit 15 outputs the data signal Vdata in the form of a voltage.

[0074] The power supply circuit 17 may generate a voltage required to drive the pixel PX according to a control signal PCS from the controller 19. The power supply circuit 17 may generate a first driving voltage ELVDD and a second driving voltage ELVSS, and supply the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PX. The first driving voltage ELVDD may be a high level voltage provided to a terminal of a driving transistor connected to a first electrode (e.g., a pixel electrode or an anode) of a display element included in the pixel PX. The second driving voltage ELVSS may be a low level voltage provided to a second electrode (e.g., a counter electrode or a cathode) of a display element included in the pixel PX.

[0075] The controller 19 may generate control signals GCS, DCS, and PCS based on signals input from the outside, and supply them to the gate drive circuit 13, the data drive circuit 15, and the power supply circuit 17. The control signal GCS output to the gate drive circuit 13 may include a clock signal and a gate start signal. The control signal DCS output to the data drive circuit 15 may include a data start signal and a clock signal.

[0076] The display device 10 may include a display panel, and the display panel may include a substrate. The pixel PX may be arranged in a display area DA of the substrate. During the process of forming a transistor of a pixel circuit in the display area DA of the substrate, a portion or all of the gate drive circuit 13 may be formed (e.g., directly formed) in the peripheral area PA of the substrate. The data drive circuit 15, the power supply circuit 17, and the controller 19 may be formed as separate integrated circuit chips or as one integrated circuit chip, respectively, and may be arranged on a flexible printed circuit board (FPCB) electrically connected to a pad arranged on one side of the substrate. In another embodiment, the data drive circuit 15, the power supply circuit 17, and the controller 19 may be arranged (e.g., directly arranged) on the substrate by a chip on glass (COG) method or a chip on plastic (COP) method.

[0077] The display device 10 may support a variable refresh rate (VRR). The refresh rate may be the frequency at which a data signal is substantially written to a driving transistor of a pixel PX, and may also be referred to as a screen scan rate or a screen reproduction rate. The refresh rate may represent the number of image frames reproduced in one second. In an embodiment, the refresh rate may be the output frequency of a gate drive circuit 13 and / or a data drive circuit 15. The frequency corresponding to the refresh rate may be a driving frequency. The display device 10 may adjust the output frequency of a gate drive circuit 13 and the output frequency of a data drive circuit 15 corresponding thereto according to the driving frequency. The display device 10 supporting VRR may operate by changing the driving frequency within a range between a maximum driving frequency and a minimum driving frequency. As an example, in the case where the refresh rate is about 60 hertz (Hz), a gate signal for writing a data signal from a gate drive circuit 13 may be supplied to each horizontal line (each horizontal row) 60 times per second. The display device 10 may display an image while changing the driving frequency according to the refresh rate.

[0078] According to the driving frequency, one frame 1F may include the first scanning period AS, or may include the first scanning period AS and one or more second scanning periods SS. Figure 3A As shown in FIG. 1 , in a display device 10 operating at a driving frequency of about A Hz, one frame 1F may include one first scanning period AS. Figure 3B As shown in FIG. 1 , in a display device 10 operated at a driving frequency of B Hz less than a driving frequency of A Hz, one frame 1F may include one first scanning period AS and one or more second scanning periods SS. In the case where the driving frequency is low, the length of one frame 1F may be increased. In an embodiment, Figure 3A A Hz in can be a driving frequency of about 120 Hz, and Figure 3B The B Hz in may be a driving frequency lower than 120 Hz (such as a driving frequency of 10 Hz).

[0079] The first scanning period AS may be defined as an address scanning period in which a data signal is written into the pixel PX according to the first gate signal GW, and accordingly, the pixel PX emits light. The operation in which the data signal is written into the pixel PX from the data line DL may be referred to as a data programming operation. The second scanning period SS may be defined as a self-scanning period in which the first gate signal GW is not applied to the pixel PX and the data signal is not written. During the second scanning period SS, the data signal written during the first scanning period AS is maintained, and the pixel PX may emit light according to the data signal written during the first scanning period AS. The length of the second scanning period SS may be equal to the length of the first scanning period AS.

[0080] Figure 4 is a schematic diagram of an equivalent circuit of a pixel PX according to an embodiment.

[0081] Reference Figure 4 , also refer to Figure 2 , the pixel PX may include a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. For example, the pixel circuit PC may be connected to the gate line GL and the data line DL. In an embodiment, the gate line GL may include a first gate line GWL, a second gate line GIL, a third gate line GRL, a fourth gate line EML, and a fifth gate line EMBL.

[0082] The pixel PX may be connected to a first gate line GWL transmitting a first gate signal GW, a second gate line GIL transmitting a second gate signal GI, a third gate line GRL transmitting a third gate signal GR, a fourth gate line EML transmitting a fourth gate signal EM, a fifth gate line EMBL transmitting a fifth gate signal EMB, and a data line DL transmitting a data signal Vdata. Because light emission of the pixel PX is controlled by the fourth gate signal EM and the fifth gate signal EMB, the fourth gate signal EM and the fifth gate signal EMB may be referred to as emission control signals, and the fourth gate line EML and the fifth gate line EMBL may also be referred to as emission control lines.

[0083] For example, the pixel PX may be connected to a driving voltage line PL transmitting the first driving voltage ELVDD, a reference voltage line VRL transmitting the reference voltage Vref, and an initialization voltage line VL transmitting the initialization voltage Vint.

[0084] The first to fifth gate lines GWL to EMBL may be arranged at Figure 2 , and the gate driving circuit 13 can apply the first gate signal GW, the second gate signal GI, the third gate signal GR, the fourth gate signal EM and the fifth gate signal EMB to the first gate line GWL, the second gate line GIL, the third gate line GRL, the fourth gate line EML and the fifth gate line EMBL respectively. The power supply circuit 17 can generate a reference voltage Vref and an initialization voltage Vint and supply them to the pixel PX.

[0085] The voltage level of the first driving voltage ELVDD may be greater than the voltage level of the second driving voltage ELVSS. The voltage level of the reference voltage Vref may be less than the voltage level of the first driving voltage ELVDD. The voltage level of the initialization voltage Vint may be less than the voltage level of the second driving voltage ELVSS.

[0086] In an embodiment, the transistor included in the pixel circuit PC may be an N-type oxide thin film transistor. The oxide thin film transistor may be a low temperature polycrystalline oxide (LTPO) thin film transistor in which the active pattern (e.g., semiconductor) includes an oxide. However, this is an example, and the N-type transistor is not limited thereto. As an example, the active pattern (e.g., semiconductor) included in the N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon and polycrystalline silicon) or an organic semiconductor, etc.

[0087] The pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, and a first capacitor C1 and a second capacitor C2. The first transistor T1 may be a driving transistor that outputs a driving current corresponding to a data signal, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a switching transistor that transmits a signal. The first terminal (e.g., the first electrode) and the second terminal (e.g., the second electrode) of each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a source or a drain according to the voltage of the first terminal and the second terminal. As an example, according to the voltage of the first terminal and the second terminal, the first terminal may be a drain and the second terminal may be a source, or the first terminal may be a source and the second terminal may be a drain. The node to which the first gate of the first transistor T1 is connected may be defined as a first node N1, and the node to which the second terminal of the first transistor T1 is connected may be defined as a second node N2.

[0088] The first transistor T1 may be connected between the driving voltage line PL and the second node N2. The first transistor T1 may include a gate, a first terminal, and a second terminal connected to the second node N2. The gate of the first transistor T1 may include a first gate connected to the first node N1 and a second gate connected to the second terminal of the first transistor T1. The first gate and the second gate of the first transistor T1 may be arranged on different layers to face each other. As an example, the first gate and the second gate of the first transistor T1 may be arranged to face each other with a semiconductor layer interposed between the first gate and the second gate.

[0089] The first gate of the first transistor T1 may be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the first capacitor C1. The second gate of the first transistor T1 may be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1 may be connected to the driving voltage line PL through the fifth transistor T5, and the second terminal of the first transistor T1 may be connected to the pixel electrode of the organic light emitting diode OLED through the sixth transistor T6. The first terminal of the first transistor T1 may be connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 may be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first transistor T1 may receive the data signal Vdata according to the switching operation of the second transistor T2, and control the amount of driving current flowing through the organic light emitting diode OLED.

[0090] The second transistor T2 (e.g., a write transistor) may be connected between the data line DL and the first gate of the first transistor T1. The second transistor T2 may include a gate, a first terminal, and a second terminal. For example, the gate of the second transistor T2 may be connected to the first gate line GWL, the first terminal of the second transistor T2 may be connected to the data line DL, and the second terminal of the second transistor T2 may be connected to the first node N1. The second terminal of the second transistor T2 may be connected to the first gate of the first transistor T1, the first terminal of the third transistor T3, and the first capacitor C1. The second transistor T2 may be turned on according to the first gate signal GW transmitted to the first gate line GWL to electrically connect the data line DL to the first node N1, and transmit the data signal Vdata transmitted through the data line DL to the first node N1.

[0091] The third transistor T3 (e.g., the first initialization transistor) may be connected between the first gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a gate, a first terminal, and a second terminal. For example, the gate of the third transistor T3 may be connected to the third gate line GRL, the first terminal of the third transistor T3 may be connected to the first node N1, and the second terminal of the third transistor T3 may be connected to the reference voltage line VRL. The first terminal of the third transistor T3 may be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first capacitor C1. The third transistor T3 may be turned on according to the third gate signal GR transmitted to the third gate line GRL, and the reference voltage Vref transmitted through the reference voltage line VRL may be transmitted to the first node N1.

[0092] The fourth transistor T4 (for example, the second initialization transistor or the reset transistor) may be connected between the sixth transistor T6 and the initialization voltage line VL. The fourth transistor T4 may be connected between the organic light emitting diode OLED and the initialization voltage line VL. The fourth transistor T4 includes a gate, a first terminal, and a second terminal. For example, the gate of the fourth transistor T4 may be connected to the second gate line GIL, the first terminal of the fourth transistor T4 may be connected to the third node N3, and the second terminal of the fourth transistor T4 may be connected to the initialization voltage line VL. The first terminal of the fourth transistor T4 may be connected to the second terminal of the sixth transistor T6 and the organic light emitting diode OLED. The fourth transistor T4 may be turned on according to the second gate signal GI transmitted to the second gate line GIL, and the initialization voltage Vint transmitted through the initialization voltage line VL may be transmitted to the third node N3.

[0093] The fifth transistor T5 (e.g., the first emission control transistor) may be connected between the driving voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate, a first terminal, and a second terminal. For example, the gate of the fifth transistor T5 may be connected to the fourth gate line EML, the first terminal of the fifth transistor T5 may be connected to the driving voltage line PL, and the second terminal of the fifth transistor T5 may be connected to the first terminal of the first transistor T1. The fifth transistor T5 may be turned on or off according to a fourth gate signal EM transmitted through the fourth gate line EML.

[0094] The sixth transistor T6 (for example, the second emission control transistor) may be connected between the first transistor T1 and the organic light emitting diode OLED. The sixth transistor T6 may be connected between the second node N2 and the third node N3. The sixth transistor T6 may include a gate, a first terminal, and a second terminal. For example, the gate of the sixth transistor T6 may be connected to the fifth gate line EMBL, the first terminal of the sixth transistor T6 may be connected to the second node N2, and the second terminal of the sixth transistor T6 may be connected to the third node N3. The first terminal of the sixth transistor T6 may be connected to the second terminal of the first transistor T1, the first capacitor C1, and the second capacitor C2. The second terminal of the sixth transistor T6 may be connected to the first terminal of the fourth transistor T4 and the pixel electrode of the organic light emitting diode OLED. The sixth transistor T6 may be turned on or off according to the fifth gate signal EMB transmitted through the fifth gate line EMBL.

[0095] The first capacitor C1 may be connected between the first gate of the first transistor T1 and the second terminal of the first transistor T1. The first electrode of the first capacitor C1 may be connected to the first node N1, and the second electrode of the first capacitor C1 may be connected to the second node N2. The first electrode of the first capacitor C1 may be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the first capacitor C1 may be connected to the second terminal and the second gate of the first transistor T1, the second terminal of the second capacitor C2, and the first terminal of the sixth transistor T6. The first capacitor C1 may be a storage capacitor, and may store the threshold voltage of the first transistor T1 and the voltage corresponding to the data signal Vdata.

[0096] The second capacitor C2 may be connected between the driving voltage line PL and the second node N2. The first electrode of the second capacitor C2 may be connected to the driving voltage line PL. The second electrode of the second capacitor C2 may be connected to the second terminal and the second gate of the first transistor T1, the second terminal of the first capacitor C1, and the first terminal of the sixth transistor T6. The capacitance of the first capacitor C1 may be greater than the capacitance of the second capacitor C2.

[0097] The organic light emitting diode OLED may be connected to the first transistor T1 through the sixth transistor T6. The organic light emitting diode OLED may include a pixel electrode (e.g., an anode) and a counter electrode (e.g., a cathode). For example, the pixel electrode may be connected to the third node N3, and the counter electrode may face the pixel electrode and may be supplied with the second driving voltage ELVSS. The counter electrode may be a common electrode shared by the pixel PX.

[0098] Figure 5 is a view of a signal supplied to a pixel during a first scanning period AS according to an embodiment. Figure 6 yes Figure 5 An enlarged view of a portion of the first scanning period AS. Figure 7 is a view of a signal supplied to a pixel during a second scanning period SS according to an embodiment.

[0099] Reference Figures 5 to 7 , the first gate signal GW, the second gate signal GI, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB may each have a high level voltage (e.g., a first level voltage) in a partial period, and have a low level voltage (e.g., a second level voltage) in a partial period. Here, the high level voltage may be a gate-on voltage for turning on the transistor, and the low level voltage may be a gate-off voltage for turning off the transistor.

[0100] Reference Figures 5 to 7 , also refer to Figures 1A to 4 Each of the first scanning period AS and the second scanning period SS may include a non-emission period in which the pixel PX does not emit light and an emission period in which the pixel PX emits light. Each of the first scanning period AS and the second scanning period SS may include a non-emission period and an emission period.

[0101] The non-emission period NEP1 of the first scanning period AS may include a first non-emission period NEP11, a second non-emission period NEP12, a third non-emission period NEP13, and a fourth non-emission period NEP14. The emission period EP1 of the first scanning period AS may include a first emission period EP11, a second emission period EP12, a third emission period EP13, and a fourth emission period EP14.

[0102] The first emission period EP11 can be arranged between the first non-emission period NEP11 and the second non-emission period NEP12, the second emission period EP12 can be arranged between the second non-emission period NEP12 and the third non-emission period NEP13, the third emission period EP13 can be arranged between the third non-emission period NEP13 and the fourth non-emission period NEP14, and the fourth emission period EP14 can be arranged after the fourth non-emission period NEP14.

[0103] The first non-emission period NEP11 may include a first period P1, a second period P2, a third period P3, and a fourth period P4.

[0104] The first period P1 may be a first initialization period (e.g., a reset period) for initializing a voltage of a first node N1 to which a gate (e.g., a first gate) of the first transistor T1 is connected and a voltage of a third node N3 to which a pixel electrode of the organic light emitting diode OLED is connected. During the first period P1, the gate driving circuit 13 may output (or supply) a second gate signal GI of a gate-on voltage to the second gate line GIL, a fifth gate signal EMB of a gate-on voltage to the fifth gate line EMBL, and a third gate signal GR of a gate-on voltage to the third gate line GRL. The gate driving circuit 13 may output a first gate signal GW and a fourth gate signal EM of a gate-off voltage.

[0105] The sixth transistor T6 may be turned on according to the fifth gate signal EMB, the fourth transistor T4 may be turned on according to the second gate signal GI, and the third transistor T3 may be turned on according to the third gate signal GR. The voltages of the second node N2 and the third node N3 may be initialized to the initialization voltage Vint by the turned-on sixth transistor T6 and the fourth transistor T4. The voltage of the first node N1 (e.g., the first gate of the first transistor T1) may be initialized to the reference voltage Vref by the turned-on third transistor T3.

[0106] The second period P2 may be a compensation period for compensating the threshold voltage of the first transistor T1. During the second period P2, the gate drive circuit 13 may output the third gate signal GR of the gate-on voltage to the third gate line GRL, and output the fourth gate signal EM of the gate-on voltage to the fourth gate line EML. The gate drive circuit 13 may output the first gate signal GW of the gate-off voltage, the second gate signal GI, and the fifth gate signal EMB.

[0107] The third transistor T3 may be turned on by the third gate signal GR, and the fifth transistor T5 may be turned on by the fourth gate signal EM. Therefore, the reference voltage Vref may be supplied to the first node N1, and the first drive voltage ELVDD may be supplied to the first terminal of the first transistor T1, and therefore, the first transistor T1 may be turned on. In the case where the voltage of the second terminal of the first transistor T1 reaches (or becomes) the difference (Vref-Vth) between the reference voltage Vref and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 may be turned off. For example, since a voltage corresponding to the threshold voltage (Vth) of the first transistor T1 may be stored in the first capacitor C1, the threshold voltage (Vth) of the first transistor T1 may be compensated.

[0108] The third period P3 may be a writing period in which a data signal is supplied to the pixel. During the third period P3, the gate drive circuit 13 may output the first gate signal GW of the gate-on voltage to the first gate line GWL. The gate drive circuit 13 may output the second gate signal GI of the gate-off voltage, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB.

[0109] The second transistor T2 can be turned on according to the first gate signal GW, and the turned-on second transistor T2 can transmit the data signal Vdata from the data line DL to the first node N1 (for example, the first gate of the first transistor T1). Therefore, the voltage of the first node N1 can be changed from the reference voltage Vref to a voltage corresponding to the data signal Vdata. In this case, the voltage of the second node N2 can also change in response to the amount of voltage change of the first node N1. The voltage of the second node N2 can be changed to a voltage (Vref-Vth+α×(Vdata-Vref)) that changes according to the capacitance ratio (α=C1 / (C1+C2)) of the first capacitor C1 and the second capacitor C2. Therefore, the first capacitor C1 can be charged with a voltage corresponding to the data signal Vdata of the first transistor T1.

[0110] The fourth period P4 may be a second initialization period after writing data and before the emission period EP1, in which the voltage of the second node N2 connected to the second terminal of the first transistor T1 and the voltage of the third node N3 connected to the pixel electrode of the organic light emitting diode OLED are initialized. During the fourth period P4, the gate driving circuit 13 may output the second gate signal GI of the gate-on voltage to the second gate line GIL, and output the fifth gate signal EMB of the gate-on voltage to the fifth gate line EMBL. The gate driving circuit 13 may output the first gate signal GW of the gate-off voltage, the third gate signal GR, and the fourth gate signal EM.

[0111] During the fourth period P4, before the fourth gate signal EM is changed from the gate-off voltage to the gate-on voltage, the fourth gate signal EM of the gate-off voltage may overlap at least a portion of the second gate signal GI of the gate-on voltage and the fifth gate signal EMB of the gate-on voltage. The fourth transistor T4 may be turned on according to the second gate signal GI, and the initialization voltage Vint may be transmitted to the pixel electrode of the organic light emitting diode OLED through the turned-on fourth transistor T4. Subsequently, the sixth transistor T6 may be turned on according to the fifth gate signal EMB, and the second node N2 and the third node N3 may share charges due to the turned-on sixth transistor T6 and the fourth transistor T4.

[0112] During the second non-emission period NEP12, in the case where the fourth gate signal EM of the gate-off voltage is supplied to the fourth gate line EML, the fifth gate signal EMB of the gate-on voltage may be supplied to the fifth gate line EMBL. The fifth transistor T5 may be turned off according to the fourth gate signal EM, and the organic light emitting diode OLED may be configured not to emit light. Since the sixth transistor T6 is maintained in the on state in the emission period EP1 due to the fifth gate signal EMB during the third non-emission period NEP13, the voltage of the pixel electrode of the organic light emitting diode OLED in the emission period EP1 may be maintained during the third non-emission period NEP13.

[0113] The third non-emission period NEP13 may include a fifth period P5.

[0114] The fifth period P5 may be a third initialization period for initializing the voltage of the third node N3 to which the pixel electrode of the organic light emitting diode OLED is connected. During the fifth period P5, the gate driving circuit 13 may output the second gate signal GI of the gate-on voltage to the second gate line GIL. The gate driving circuit 13 may output the first gate signal GW of the gate-off voltage, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB.

[0115] The fourth transistor T4 may be turned on according to the second gate signal GI. A voltage of the third node N3 (eg, a pixel electrode of the organic light emitting diode OLED) may be initialized to an initialization voltage Vint through the fourth transistor T4.

[0116] The period SW3 during which the second gate signal GI in the third non-emission period NEP13 is maintained at the gate-on voltage (hereinafter referred to as "gate-on voltage period SW3") (for example, signal width) may be greater than the gate-on voltage periods SW1 and SW2 of the second gate signal GI in the first non-emission period NEP11. In an embodiment, the gate-on voltage period SW3 of the second gate signal GI in the third non-emission period NEP13 may be approximately a period from a time point ta at which the first period P1 starts to a time point tb at which the fourth period P4 ends, and within a period in which the fourth gate signal EM is maintained at the gate-off voltage in the third non-emission period NEP13 (hereinafter referred to as "gate-off voltage period").

[0117] The emission period EP1 may be a period during which the organic light emitting diode OLED emits light. During the emission period EP1, the gate driving circuit 13 may output a fourth gate signal EM of a gate-on voltage to the fourth gate line EML, and output a fifth gate signal EMB of a gate-on voltage to the fifth gate line EMBL. The gate driving circuit 13 may output a first gate signal GW of a gate-off voltage, a second gate signal GI, and a third gate signal GR.

[0118] During the emission period EP1, the fifth transistor T5 may be turned on according to the fourth gate signal EM, and the first driving voltage ELVDD may be supplied to the first terminal of the first transistor T1 through the turned-on fifth transistor T5. The first transistor T1 may output a driving current (Id∝(Vgs-Vth) 2 ), and the driving current may flow through the organic light emitting diode OLED via the sixth transistor T6 turned on according to the fifth gate signal EMB, and the organic light emitting diode OLED may emit light at a brightness corresponding to the driving current. For example, the driving current may correspond to a voltage corresponding to the data signal Vdata stored in the first capacitor C1, such as a voltage (Vgs-Vth) obtained by subtracting a threshold voltage (Vth) of the first transistor T1 from a gate-source voltage (Vgs) of the first transistor T1.

[0119] Before the first emission period EP11 starts and the third emission period EP13 starts, in the case of outputting the fourth gate signal EM of the gate-off voltage, the gate drive circuit 13 may output the second gate signal GI of the gate-on voltage and the fifth gate signal EMB of the gate-on voltage. In this case, the second gate signal GI of the gate-on voltage may be output first, and then, the fifth gate signal EMB of the gate-on voltage may be output. In an embodiment, the second gate signal GI of the gate-on voltage and the fifth gate signal EMB of the gate-on voltage may overlap each other at least partially. In another embodiment, the second gate signal GI of the gate-on voltage and the fifth gate signal EMB of the gate-on voltage may not overlap each other.

[0120] During the period Δt1 in which the second gate signal GI of the gate-on voltage and the fifth gate signal EMB of the gate-on voltage overlap each other, the fourth transistor T4 and the sixth transistor T6 may be turned on according to the second gate signal GI and the fifth gate signal EMB, and the second node N2 and the third node N3 may be electrically connected to each other through the turned-on fourth transistor T4 and the sixth transistor T6 to share charges. Since the fourth transistor T4 and the sixth transistor T6 are first turned on before the fifth transistor T5 is turned on, the voltage of the third node N3 (e.g., the voltage of the pixel electrode of the organic light emitting diode OLED) may be stabilized.

[0121] During the third non-emission period NEP13, before the second gate signal GI is converted from the gate-off voltage to the gate-on voltage to output the gate-on voltage, the gate drive circuit 13 may convert the fifth gate signal EMB from the gate-on voltage to the gate-off voltage to output the gate-off voltage. As an example, during the boundary period Δt2 between the second emission period EP12 and the third non-emission period NEP13, before the fourth gate signal EM is converted from the gate-on voltage to the gate-off voltage to output the gate-off voltage, the gate drive circuit 13 may convert the fifth gate signal EMB from the gate-on voltage to the gate-off voltage to output the gate-off voltage. In this case, the second gate signal GI may be the gate-off voltage. Therefore, the sixth transistor T6 may be turned off, and then the fifth transistor T5 may be turned off. After the sixth transistor T6 and the fifth transistor T5 are turned off, the gate drive circuit 13 may convert the second gate signal GI from the gate-off voltage to the gate-on voltage to output the gate-on voltage, and the fourth transistor T4 may be turned on. Therefore, the voltage of the third node N3 (for example, the voltage of the pixel electrode of the organic light emitting diode OLED) may be initialized. During the third non-emission period NEP13, the gate-on voltage period SW3 of the second gate signal GI may be greater than the first period P1 and the fourth period P4. Therefore, when the fifth transistor T5 is turned off, the voltage drop of the first driving voltage ELVDD may be reduced, and when the fifth transistor T5 and the sixth transistor T6 are turned off, the brightness variation of the organic light emitting diode OLED caused by the leakage current may be reduced.

[0122] The non-emission period NEP2 of the second scanning period SS may include a first non-emission period NEP21, a second non-emission period NEP22, a third non-emission period NEP23, and a fourth non-emission period NEP24. The emission period EP2 of the second scanning period SS may include a first emission period EP21, a second emission period EP22, a third emission period EP23, and a fourth emission period EP24.

[0123] The first emission period EP21 can be arranged between the first non-emission period NEP21 and the second non-emission period NEP22, the second emission period EP22 can be arranged between the second non-emission period NEP22 and the third non-emission period NEP23, the third emission period EP23 can be arranged between the third non-emission period NEP23 and the fourth non-emission period NEP24, and the fourth emission period EP24 can be arranged after the fourth non-emission period NEP24.

[0124] The first non-emission period NEP21 may not include the compensation period and the writing period included in the first non-emission period NEP11 of the first scanning period AS, and may include a sixth period P6 corresponding to the fourth period P4 as the initialization period.

[0125] The sixth period P6 may be a fourth initialization period for initializing the voltage of the third node N3 to which the pixel electrode of the organic light emitting diode OLED is connected. During the sixth period P6, the gate driving circuit 13 may output the second gate signal GI of the gate-on voltage to the second gate line GIL. The gate driving circuit 13 may output the first gate signal GW, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB of the gate-off voltage. The fourth transistor T4 may be turned on according to the second gate signal GI. The voltage of the third node N3 (e.g., the pixel electrode of the organic light emitting diode OLED) may be initialized to the initialization voltage Vint by the fourth transistor T4.

[0126] Because the output of the gate drive circuit 13 and the operation of the pixel during the second non-emission period NEP22 and the fourth non-emission period NEP24 are respectively the same as the output of the gate drive circuit 13 and the operation of the pixel during the second non-emission period NEP12 and the fourth non-emission period NEP14 of the first scanning period AS, their redundant description is omitted for the convenience of description.

[0127] The third non-emission period NEP23 may include a seventh period P7.

[0128] The seventh period P7 may be a fifth initialization period for initializing the voltage of the third node N3 to which the pixel electrode of the organic light emitting diode OLED is connected. During the seventh period P7, the gate driving circuit 13 may output the second gate signal GI of the gate-on voltage to the second gate line GIL. The gate driving circuit 13 may output the first gate signal GW, the third gate signal GR, the fourth gate signal EM, and the fifth gate signal EMB of the gate-off voltage. The fourth transistor T4 may be turned on according to the second gate signal GI. The voltage of the third node N3 (e.g., the pixel electrode of the organic light emitting diode OLED) may be initialized to the initialization voltage Vint by the fourth transistor T4.

[0129] The gate-on voltage period SW4 of the second gate signal GI during the first non-emission period NEP21 may be the same as the gate-on voltage period SW5 of the second gate signal GI during the third non-emission period NEP23. The gate-on voltage period SW4 of the second gate signal GI during the first non-emission period NEP21 and the gate-on voltage period SW5 of the second gate signal GI during the third non-emission period NEP23 may be the same as the gate-on voltage period SW3 of the second gate signal GI during the third non-emission period NEP13 of the first scan period AS.

[0130] The emission period EP2 may be a period during which the organic light emitting diode OLED emits light. The drive current output by the first transistor T1 during the emission period EP2 may be a current corresponding to the data signal Vdata supplied to the pixel during the write period of the first scanning period AS and stored and held in the first capacitor C1. Since the output of the gate drive circuit 13 and the operation of the pixel during the emission period EP2 are the same as the output of the gate drive circuit 13 and the operation of the pixel during the emission period EP1 of the first scanning period AS, the redundant description thereof is omitted for convenience of description.

[0131] Before the first emission period EP21 starts and the third emission period EP23 starts, during the period Δt3 in which the second gate signal GI of the gate-on voltage and the fifth gate signal EMB of the gate-on voltage overlap each other, the fourth transistor T4 and the sixth transistor T6 may be turned on according to the second gate signal GI and the fifth gate signal EMB, and the second node N2 and the third node N3 may be electrically connected to each other through the turned-on fourth transistor T4 and the sixth transistor T6 to share charges. Because the fourth transistor T4 and the sixth transistor T6 are turned on first before the fifth transistor T5 is turned on, the voltage of the third node N3 (e.g., the voltage of the pixel electrode of the organic light emitting diode OLED) may be stabilized.

[0132] During the first non-emission period NEP21 and the third non-emission period NEP23, the gate drive circuit 13 may cause the fifth gate signal EMB to change from the gate-on voltage to the gate-off voltage to output the gate-off voltage, and then cause the second gate signal GI to change from the gate-off voltage to the gate-on voltage to output the gate-on voltage. As an example, during the boundary period Δt4 between the fourth emission period EP24 and the first non-emission period NEP21 and the boundary period Δt4 between the second emission period EP22 and the third non-emission period NEP23, before the fourth gate signal EM changes from the gate-on voltage to the gate-off voltage, the fifth gate signal EMB may first change from the gate-on voltage to the gate-off voltage. In this case, the second gate signal GI may be the gate-off voltage. Therefore, the sixth transistor T6 may be turned off, and then the fifth transistor T5 may be turned off. After both the sixth transistor T6 and the fifth transistor T5 are turned off, the second gate signal GI may change from the gate-off voltage to the gate-on voltage, and the fourth transistor T4 may be turned on. Therefore, the voltage of the third node N3 (for example, the voltage of the pixel electrode of the organic light emitting diode OLED) may be initialized. Then, during the third non-emission period NEP23, the gate-on voltage period SW5 of the second gate signal GI may be maintained longer than the first period P1 and the fourth period P4. Therefore, when the fifth transistor T5 is turned off, the voltage drop of the first driving voltage ELVDD may be reduced, and when the fifth transistor T5 and the sixth transistor T6 are turned off, the brightness variation of the organic light emitting diode OLED caused by the leakage current may be reduced.

[0133] In an embodiment, Figure 3A As shown in FIG. 1 , when the display device 10 is driven at about A Hz (eg, about 120 Hz), one frame may include Figure 5 , and one frame may include four non-transmission periods and four transmission periods.

[0134] Among the four non-emission periods, the first non-emission period (e.g., the first non-emission period NEP11) may include a first period P1, a second period P2, a third period P3, and a fourth period P4. Among the four non-emission periods, during the even non-emission period (e.g., the second non-emission period NEP12 and the fourth non-emission period NEP14), the fifth transistor T5 may be turned off according to the fourth gate signal EM of the gate-off voltage, and the sixth transistor T6 may be turned on according to the fifth gate signal EMB of the gate-on voltage. Among the four non-emission periods, during the odd non-emission period (e.g., the first non-emission period NEP11 and the third non-emission period NEP13), the fourth transistor T4 may be turned on according to the second gate signal GI of the gate-on voltage. The period during which the fourth transistor T4 in the third non-emission period NEP13 is turned on may be longer than the period during which the fourth transistor T4 in the first non-emission period NEP11 is turned on (e.g., the gate-on voltage period of the second gate signal GI). In a portion of a period during which the fourth transistor T4 in each of the odd-numbered non-emission periods is turned on, the fifth transistor T5 may be turned off, and the sixth transistor T6 may be turned on.

[0135] Among the four non-emission periods, during an odd non-emission period (e.g., the third non-emission period NEP13) other than the first non-emission period NEP11, after the fifth gate signal EMB is changed from the gate-on voltage to the gate-off voltage and the fifth transistor T5 is switched from the on state to the off state, the second gate signal GI is changed from the gate-off voltage to the gate-on voltage, and therefore, the fourth transistor T4 can be switched from the off state to the on state. More specifically, among the four emission periods, during a boundary period between an even emission period and a non-emission period after the even emission period (e.g., a boundary period Δt2 between the second emission period EP12 and the third non-emission period NEP13), before the fourth gate signal EM is changed from the gate-on voltage to the gate-off voltage and the fifth transistor T5 is switched from the on state to the off state, the fifth gate signal EMB is changed from the gate-on voltage to the gate-off voltage, and therefore, the sixth transistor T6 can be switched from the on state to the off state. After the fifth transistor T5 is switched from the on state to the off state, the second gate signal GI is transformed from the gate-off voltage to the gate-on voltage, and thus, the fourth transistor T4 may be switched from the off state to the on state.

[0136] In an embodiment, Figure 3B As shown in FIG. 1 , when the display device 10 is driven at about B Hz, a frame may include Figure 5 A first scanning period AS shown in FIG. Figure 7In the case where one frame includes two or more second scanning periods SS, Figure 7 The non-emission period NEP2 and the emission period EP2 of the second scanning period SS may be repeated alternately. Therefore, the first non-emission period NEP21 of the second scanning period SS may be after the fourth emission period EP24 of the second scanning period SS.

[0137] A frame may include eight or more non-emission time periods (for example, the first non-emission time period NEP11, the second non-emission time period NEP12, the third non-emission time period NEP13 and the fourth non-emission time period NEP14 of the first scanning time period AS and the first non-emission time period NEP21, the second non-emission time period NEP22, the third non-emission time period NEP23 and the fourth non-emission time period NEP24 of the second scanning time period SS) and eight or more transmission time periods (for example, the first transmission time period EP11, the second transmission time period EP12, the third transmission time period EP13 and the fourth transmission time period EP14 of the first scanning time period AS and the first transmission time period EP21, the second transmission time period EP22, the third transmission time period EP23 and the fourth transmission time period EP24 of the second scanning time period SS).

[0138] Among the eight or more non-emission periods, the first non-emission period (e.g., the first non-emission period NEP11 of the first scanning period AS) may include a first period P1, a second period P2, a third period P3, and a fourth period P4. Among the eight or more non-emission periods, during the even non-emission periods (e.g., the second non-emission period NEP12 and the fourth non-emission period NEP14 of the first scanning period AS and the second non-emission period NEP22 and the fourth non-emission period NEP24 of the second scanning period SS), the fifth transistor T5 may be turned off according to the fourth gate signal EM of the gate-off voltage, and the sixth transistor T6 may be turned on according to the fifth gate signal EMB of the gate-on voltage. Among the eight or more non-emission periods, during the odd non-emission periods (e.g., the first non-emission period NEP11 and the third non-emission period NEP13 of the first scanning period AS and the first non-emission period NEP21 and the third non-emission period NEP23 of the second scanning period SS), the fourth transistor T4 may be turned on according to the second gate signal GI of the gate-on voltage. The period during which the fourth transistor T4 is turned on in the remaining odd-numbered non-emission periods (e.g., the third non-emission period NEP13 of the first scanning period AS and the first non-emission period NEP21 and the third non-emission period NEP23 of the second scanning period SS) may be longer than the period during which the fourth transistor T4 is turned on in the first non-emission period NEP11 (e.g., the gate-on voltage period of the second gate signal GI). In a portion of the period during which the fourth transistor T4 is turned on in each of the odd-numbered non-emission periods, the fifth transistor T5 may be turned off, and the sixth transistor T6 may be turned on.

[0139] Among eight or more non-emission periods, during odd-numbered non-emission periods other than the first non-emission period NEP11 (for example, the third non-emission period NEP13 of the first scanning period AS and the first non-emission period NEP21 and the third non-emission period NEP23 of the second scanning period SS), after the fifth gate signal EMB is changed from the gate-on voltage to the gate-off voltage and the fifth transistor T5 is switched from the on state to the off state, the second gate signal GI is changed from the gate-off voltage to the gate-on voltage, and therefore, the fourth transistor T4 can be switched from the off state to the on state. More specifically, among eight or more emission periods, during a boundary period between an even-numbered emission period and a non-emission period after the even-numbered emission period (e.g., a boundary period Δt2 between a second emission period EP12 and a third non-emission period NEP13 of the first scanning period AS, a boundary period Δt4 between a fourth emission period EP14 of the first scanning period AS and a first non-emission period NEP21 of the second scanning period SS, and a boundary period Δt4 between a fourth emission period EP24 and a first non-emission period NEP21 of the second scanning period SS, and a boundary period Δt4 between a second emission period EP22 and a third non-emission period NEP23 of the second scanning period SS), before the fourth gate signal EM is changed from the gate-on voltage to the gate-off voltage and the fifth transistor T5 is switched from the on state to the off state, the fifth gate signal EMB is changed from the gate-on voltage to the gate-off voltage, and therefore, the sixth transistor T6 can be switched from the on state to the off state. After the fifth transistor T5 is switched from the on state to the off state, the second gate signal GI is changed from the gate-off voltage to the gate-on voltage, and therefore, the fourth transistor T4 can be switched from the off state to the on state.

[0140] Figure 8 and Fig. 9 is a view of signals supplied to pixels during a first scanning period AS′ and a second scanning period SS′ according to a comparative example.

[0141] Reference Figure 8 , the non-emission period NEP1' of the first scanning period AS' according to the comparative example may include a first non-emission period NEP11', a second non-emission period NEP12', a third non-emission period NEP13' and a fourth non-emission period NEP14'. The emission period EP1' of the first scanning period AS' may include a first emission period EP11', a second emission period EP12', a third emission period EP13' and a fourth emission period EP14'.

[0142] Reference Fig. 9, the non-emission period NEP2' of the second scanning period SS' according to the comparative example may include a first non-emission period NEP21', a second non-emission period NEP22', a third non-emission period NEP23' and a fourth non-emission period NEP24'. The emission period EP2' of the second scanning period SS' may include a first emission period EP21', a second emission period EP22', a third emission period EP23' and a fourth emission period EP24'.

[0143] The non-emission period NEP1' of the first scanning period AS' according to the comparative example may include a first period P1', a second period P2', a third period P3' and a fourth period P4'. The first period P1', the second period P2', the third period P3' and the fourth period P4' of the first scanning period AS' may correspond to the first period P1, the second period P2, the third period P3 and the fourth period P4 according to the embodiment, respectively.

[0144] Each of the first and third non-emission periods NEP11' and NEP13' of the first scanning period AS' and each of the first and third non-emission periods NEP21' and NEP23' of the second scanning period SS' according to the comparative example may include first and fourth periods P1' and P4' as initialization periods.

[0145] During each of the first non-emission period NEP11', the second non-emission period NEP12', the third non-emission period NEP13' and the fourth non-emission period NEP14' of the first scanning period AS' according to the comparative example and each of the first non-emission period NEP21', the second non-emission period NEP22', the third non-emission period NEP23' and the fourth non-emission period NEP24' of the second scanning period SS', the fourth gate signal EM may be supplied in the order of the gate-off voltage, the gate-on voltage and the gate-off voltage, and the fifth gate signal EMB may be supplied in the order of the gate-on voltage, the gate-off voltage and the gate-on voltage.

[0146] Fig.10 It is shown in Figure 4 2 is a diagram showing a difference in flicker characteristics for each frequency in a case where a pixel PX shown in FIG. 1 is operated according to a comparative example. Fig.11 It is shown in Figure 4 0 is a diagram showing a change in driving voltage when the pixel PX shown in FIG. 1 is operated according to a comparative example. Fig.12 It is shown in Figure 4 FIG. 4 is a diagram showing a difference in flicker characteristics for each frequency in a case where a pixel PX shown in FIG. 4 operates according to an embodiment. Fig.13 It is shown in Figure 41 is a view of brightness changes in a portion of an image in the case where the pixel PX shown in FIG. 1 operates according to the embodiment and the comparative example. Fig.13 The horizontal axis of represents the position of a pixel line (eg, pixel row), and the vertical axis represents brightness. Fig.14A is a view showing a mura effect (visual unevenness or irregularity) occurring in a portion of an image according to a comparative example. Fig. 14B is a view of an image according to an embodiment showing a state in which a stain effect is prevented. Fig.14A and Fig. 14B The arrows in the Fig.13 The horizontal axis corresponds to the direction of the pixel line.

[0147] Reference Figures 10 to 14B , also refer to Figure 4 ,like Fig.10 As shown in FIG. , in the pixel PX according to Figure 8 and Fig. 9 In the case of operating in the first scanning period AS' and the second scanning period SS' shown in , according to the frequency analysis of the image signal using a fast Fourier transform (FFT), there is a difference in flicker characteristics between operation at a high frequency (e.g., about 120 Hz) and operation at a low frequency (e.g., about 10 Hz). Flicker (or power line flicker) can be understood as a visible change in the brightness of a pixel due to rapid fluctuations in the power supply voltage.

[0148] For example, Fig.11 As shown in FIG. 1 , during each of the first scanning period AS′ and the second scanning period SS′, since the second gate signal GI is supplied to the pixel PX with a period of 2 cycles, the change of the first driving voltage ELVDD measured for the entire panel occurs twice. Fig.13 As shown in FIG. 1 , in the comparative example, since each pixel PX is affected by the rise and fall of the first driving voltage ELVDD according to its operation state and luminance degradation occurs in a portion of the image, the following may occur: Fig.14A The streak effect is in the shape of the horizontal lines shown in .

[0149] On the contrary, Fig.12 As shown in Figure 5 and Figure 7 In the case of operating in the first scanning period AS and the second scanning period SS shown in , according to the frequency analysis of the image signal using the fast Fourier transform (FFT), the difference in flicker characteristics between the operation at a high frequency (e.g., about 120 Hz) and the operation at a low frequency (e.g., about 10 Hz) is similar. Fig.13As shown in FIG. 1 , in the case where the pixel PX operates according to the embodiment, since the luminance degradation in a part of the image is reduced compared with the comparative example, as shown in FIG. Fig. 14B As shown in , the streak effect of the horizontal line shape can be reduced.

[0150] Fig.15 is a view of a signal supplied to a pixel during a first scanning period AS according to an embodiment. Fig.16 is a diagram of a signal supplied to a pixel during a second scanning period SS according to an embodiment. Figures 5 to 7 The difference between the first scanning period AS and the second scanning period SS is shown in FIG.

[0151] Reference Fig.15 and Fig.16 , also refer to Figure 2 and Figure 4 , the brightness of the display device can be adjusted according to the emission ratio (or, the active matrix organic light emitting diode (AMOLED) cutoff ratio (AOR)). As an example, when the AMOLED cutoff ratio (AOR) increases, the brightness of the display device can be reduced. The controller 19 (see Figure 2 ) can supply the control signal GCS to the gate drive circuit 13. For example, the control signal GCS can correspond to a dimming mode of the display device. The dimming mode can be a mode for adjusting the brightness of the display device. The gate drive circuit 13 can change the gate-on voltage period and the gate-off voltage period of the fourth gate signal EM according to the AMOLED cutoff ratio (AOR) of the dimming mode in response to the control signal GCS. As the AMOLED cutoff ratio (AOR) increases, the gate-off voltage period of the fourth gate signal EM can increase, and the gate-on voltage period can decrease. Therefore, the emission period can be reduced, and the non-emission period can be increased. As the emission period decreases, the brightness of the organic light emitting diode OLED can decrease.

[0152] like Fig.15 and Fig.16As shown in, the first emission period EP31, the second emission period EP32, the third emission period EP33 and the fourth emission period EP34 of the first scanning period AS and the first emission period EP41, the second emission period EP42, the third emission period EP43 and the fourth emission period EP44 of the second scanning period SS can be adjusted according to the AMOLED cutoff ratio (AOR). For example, the first non-emission period NEP31, the second non-emission period NEP32, the third non-emission period NEP33 and the fourth non-emission period NEP34 of the first scanning period AS and the first non-emission period NEP41, the second non-emission period NEP42, the third non-emission period NEP43 and the fourth non-emission period NEP44 of the second scanning period SS can be adjusted according to the AMOLED cutoff ratio (AOR).

[0153] Even in the case where the emission period is reduced due to the increase of the AMOLED cutoff ratio (AOR), the supply timing relationship of the gate-on voltage and the gate-off voltage of the gate signal during the first scanning period AS and the second scanning period SS is as follows: Figures 5 to 7 as shown in .

[0154] For example, during the second non-emission period NEP32 and the fourth non-emission period NEP34 of the first scanning period AS and the second non-emission period NEP42 and the fourth non-emission period NEP44 of the second scanning period SS, when the fourth gate signal EM of the gate-off voltage is supplied to the fourth gate line EML, the fifth gate signal EMB of the gate-on voltage can be supplied to the fifth gate line EMBL.

[0155] For example, the gate-on voltage period of the second gate signal GI in the third non-emission period NEP33 of the first scanning period AS and the gate-on voltage period of the second gate signal GI in the third non-emission period NEP43 of the second scanning period SS can be roughly the period from the time point at the beginning of the first period of the first scanning period AS to the time point at the end of the fourth period, and within the gate-off voltage period of the fourth gate signal EM.

[0156] For example, before the first emission periods EP31 and EP41 start and the third emission periods EP33 and EP43 start, the second gate signal GI of the gate-on voltage and the fifth gate signal EMB of the gate-on voltage may be supplied while the fourth gate signal EM of the gate-off voltage is supplied.

[0157] For example, during the boundary period between the second emission period EP32 and the third non-emission period NEP33 and the boundary period between the second emission period EP42 and the third non-emission period NEP43, before the fourth gate signal EM changes from the gate-on voltage to the gate-off voltage, the fifth gate signal EMB first changes from the gate-on voltage to the gate-off voltage, and after both the sixth transistor T6 and the fifth transistor T5 are turned off, the second gate signal GI can be changed from the gate-off voltage to the gate-on voltage.

[0158] Embodiments can improve image quality by adjusting the driving timing of a pixel including an N-type oxide thin film transistor. The pixel may include a transistor (eg, Figure 4 a fourth transistor T4 in the circuit), a transistor (eg, a transistor between a driving voltage line supplying the first driving voltage ELVDD and the driving transistor) Figure 4 The fifth transistor T5 in the embodiment of the present invention) and the transistor between the driving transistor and the organic light emitting diode OLED (for example, Figure 4 The fifth transistor T5 and the sixth transistor T6 may be independently turned on and off according to different gate signals.

[0159] In an embodiment, before the gate signal supplied to the fifth transistor T5 changes from the gate-off voltage to the gate-on voltage, the gate signal of the gate-on voltage may be supplied to the fourth transistor T4 and the sixth transistor T6. Therefore, before the fifth transistor T5 is turned on, the voltage of the pixel electrode may be stabilized.

[0160] In an embodiment, when a gate signal of a gate-off voltage is supplied to the fifth transistor T5, a gate signal of a gate-on voltage may be supplied to the gate of the sixth transistor T6. Therefore, when the fifth transistor T5 is turned off, the voltage of the pixel electrode may be maintained.

[0161] In an embodiment, before the gate signal supplied to the fifth transistor T5 is changed from the gate-on voltage to the gate-off voltage, the gate signal supplied to the sixth transistor T6 is first changed from the gate-on voltage to the gate-off voltage, and after both the fifth transistor T5 and the sixth transistor T6 are turned off, the gate signal supplied to the fourth transistor T4 can be changed from the gate-off voltage to the gate-on voltage. Then, when the fifth transistor T5 is turned off, the fourth transistor T4 can be turned off. Therefore, when the fifth transistor T5 is turned off, the voltage drop of the first driving voltage ELVDD can be reduced, and then, when both the fifth transistor T5 and the sixth transistor T6 are turned off, the brightness change caused by the leakage current can be reduced.

[0162] Fig.17 is a schematic cross-sectional view of a structure of a display element according to an embodiment. FIG. 18A to FIG. 19B is a schematic cross-sectional view of a structure of a display element according to an embodiment.

[0163] Reference Figures 17 to 18D , also refer to Figure 1A and Figure 4 , an organic light emitting diode OLED as a display element according to an embodiment may include a pixel electrode 211, a counter electrode 215, and an intermediate layer 213 between the pixel electrode 211 (eg, a first electrode; eg, an anode) and the counter electrode 215 (eg, a second electrode; eg, a cathode).

[0164] The pixel electrode 211 may include a light-transmitting conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) or aluminum zinc oxide (AZO). The pixel electrode 211 may include a reflective layer, and the reflective layer includes silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. As an example, the pixel electrode 211 may have a three-layer structure of ITO / Ag / ITO.

[0165] The counter electrode 215 may be disposed on the intermediate layer 213. The counter electrode 215 may include a metal, an alloy, a conductive compound, or any combination thereof having a low work function. As an example, the counter electrode 215 may include lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The counter electrode 215 may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0166] The intermediate layer 213 may include a polymer organic material or a low molecular weight organic material that emits light having a selected color. In addition to various organic materials, the intermediate layer 213 may also include a metal-containing compound such as an organic metal compound, an inorganic material such as a quantum dot, and the like.

[0167] In an embodiment, the intermediate layer 213 may include an emission layer and a first functional layer and a second functional layer below and above the emission layer, respectively. The first functional layer may include, for example, a hole transport layer (HTL), or include an HTL and a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). In another example, the first functional layer or the second functional layer may be omitted. Each of the first functional layer and the second functional layer may be integrally formed to correspond to the organic light emitting diode OLED included in the display area DA.

[0168] In an embodiment, the intermediate layer 213 may include two or more emission units and a charge generation layer CGL disposed between the two emission units. For example, two or more emission units may be sequentially stacked between the pixel electrode 211 and the counter electrode 215. In the case where the intermediate layer 213 includes the emission unit and the charge generation layer CGL, the organic light emitting diode OLED may be a tandem light emitting element. The organic light emitting diode OLED may improve color purity and light emission efficiency by having a stacked structure of emission units.

[0169] The emission unit may include an emission layer and a first functional layer and a second functional layer respectively below and above the emission layer. The charge generation layer CGL may include a negative charge generation layer and a positive charge generation layer. The light emission efficiency of the organic light emitting diode OLED as a tandem light emitting element including an emission layer may be further enhanced by the negative charge generation layer and the positive charge generation layer.

[0170] The negative charge generation layer may be an N-type charge generation layer. The negative charge generation layer may supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a P-type charge generation layer. The positive charge generation layer may supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0171] In an embodiment, Fig.18AAs shown in , the organic light emitting diode OLED may include a first emission unit EU1 and a second emission unit EU2 stacked sequentially. For example, the first emission unit EU1 may include a first emission layer EML1, and the second emission unit EU2 may include a second emission layer EML2. The charge generation layer CGL may be disposed between the first emission unit EU1 and the second emission unit EU2. As an example, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a charge generation layer CGL, a second emission layer EML2, and a counter electrode 215 stacked sequentially. The first functional layer and the second functional layer may be disposed below and above the first emission layer EML1. The first functional layer and the second functional layer may be disposed below and above the second emission layer EML2. The first emission layer EML1 may be a blue emission layer, and the second emission layer EML2 may be a yellow emission layer.

[0172] In an embodiment, Fig.18B As shown in , the organic light emitting diode OLED may include a first emission unit EU1, a second emission unit EU2, and a third emission unit EU3 stacked sequentially. For example, the first emission unit EU1 and the third emission unit EU3 may each include a first emission layer EML1, and the second emission unit EU2 may include a second emission layer EML2. The first charge generation layer CGL1 may be disposed between the first emission unit EU1 and the second emission unit EU2, and the second charge generation layer CGL2 may be disposed between the second emission unit EU2 and the third emission unit EU3. As an example, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1, and a counter electrode 215 stacked sequentially. The first functional layer and the second functional layer may be disposed below and above the first emission layer EML1. The first functional layer and the second functional layer may be disposed below and above the second emission layer EML2. The first emission layer EML1 may be a blue emission layer, and the second emission layer EML2 may be a yellow emission layer.

[0173] In an embodiment, Fig. 18C and Fig.18DAs shown in, in the organic light emitting diode OLED, in addition to the second emission layer EML2, the second emission unit EU2 may also include a third emission layer EML3 below the second emission layer EML2 in contact with the second emission layer EML2 (e.g., in direct contact with the second emission layer EML2) and / or a fourth emission layer EML4 above the second emission layer EML2 in contact with the second emission layer EML2 (e.g., in direct contact with the second emission layer EML2). Here, "direct contact" may mean that another layer is not provided between the second emission layer EML2 and the third emission layer EML3 and / or between the second emission layer EML2 and the fourth emission layer EML4. The third emission layer EML3 may be a red emission layer, and the fourth emission layer EML4 may be a green emission layer.

[0174] As an example, Fig. 18C As shown in , the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a second charge generation layer CGL2, a first emission layer EML1, and a counter electrode 215 stacked sequentially. In another embodiment, as Fig.18D As shown in the figure, the organic light emitting diode OLED may include a pixel electrode 211, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a fourth emission layer EML4, a second charge generation layer CGL2, a first emission layer EML1 and a counter electrode 215 stacked sequentially.

[0175] Fig.19A It is shown Fig. 18C A schematic cross-sectional view of an example of an organic light emitting diode, and Fig.19B It is shown Fig.18D Schematic cross-sectional view of an example of an organic light emitting diode.

[0176] Reference Fig.19A , also refer to Figure 4 , the organic light emitting diode OLED may include a first emission unit EU1, a second emission unit EU2, and a third emission unit EU3 stacked sequentially. The first charge generation layer CGL1 may be disposed between the first emission unit EU1 and the second emission unit EU2, and the second charge generation layer CGL2 may be disposed between the second emission unit EU2 and the third emission unit EU3. Each of the first charge generation layer CGL1 and the second charge generation layer CGL2 may include a negative charge generation layer nCGL and a positive charge generation layer pCGL.

[0177] The first emission unit EU1 may include a blue emission layer BEML. The first emission unit EU1 may further include a hole injection layer HIL and a hole transport layer HTL between the pixel electrode 211 and the blue emission layer BEML. In an embodiment, a P-doped layer may be further disposed between the hole injection layer HIL and the hole transport layer HTL. The P-doped layer may be formed by doping the hole injection layer HIL with a P-type dopant. In an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further disposed between the blue emission layer BEML and the hole transport layer HTL. The blue light auxiliary layer may enhance the light emission efficiency of the blue emission layer BEML. The blue light auxiliary layer may enhance the light emission efficiency of the blue emission layer BEML by adjusting the hole charge balance. The electron blocking layer may prevent electrons from being injected into the hole transport layer HTL. The buffer layer may compensate for the resonance distance according to the wavelength of light emitted from the emission layer.

[0178] The second emission unit EU2 may include a yellow emission layer YEML and a red emission layer REML below the yellow emission layer YEML, the red emission layer REML being in contact with the yellow emission layer YEML (e.g., in direct contact with the yellow emission layer YEML). The second emission unit EU2 may also include a hole transport layer HTL between the red emission layer REML and the positive charge generation layer pCGL of the first charge generation layer CGL1, and an electron transport layer ETL between the yellow emission layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0179] The third emission unit EU3 may include a blue emission layer BEML. The third emission unit EU3 may also include a hole transport layer HTL between the blue emission layer BEML and the positive charge generation layer pCGL of the second charge generation layer CGL2. The third emission unit EU3 may also include an electron transport layer ETL and an electron injection layer EIL between the blue emission layer BEML and the counter electrode 215. The electron transport layer ETL may include a single layer or multiple layers. In an embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may be further disposed between the blue emission layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may be further disposed between the blue emission layer BEML and the electron transport layer ETL. The hole blocking layer may prevent holes from being injected into the electron transport layer ETL.

[0180] Fig.19B The organic light emitting diode OLED shown in Fig.19A The organic light emitting diode OLED shown in FIG. 1 is different in the stacking structure of the second emission unit EU2, and the other configurations are the same as each other. Fig.19B, the second emission unit EU2 may include a yellow emission layer YEML, a red emission layer REML below the yellow emission layer YEML and in contact with the yellow emission layer YEML (e.g., in direct contact with the yellow emission layer YEML), and a green emission layer GEML above the yellow emission layer YEML and in contact with the yellow emission layer YEML (e.g., in direct contact with the yellow emission layer YEML). The second emission unit EU2 may also include a hole transport layer HTL between the red emission layer REML and the positive charge generation layer pCGL of the first charge generation layer CGL1, and also include an electron transport layer ETL between the green emission layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0181] Fig. 20 is a schematic cross-sectional view of a structure of a pixel of a display device according to an embodiment.

[0182] Reference Fig. 20 , also refer to Figure 4 , the display device may include pixels. The pixels may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may each include a pixel electrode 211, a counter electrode 215, and an intermediate layer 213. In an embodiment, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. Here, the pixel may include an organic light emitting diode OLED as a display element, and the organic light emitting diode OLED of each pixel may be electrically connected to the pixel circuit.

[0183] The pixel electrode 211 may be independently provided to each of the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 .

[0184] The intermediate layer 213 of the organic light emitting diode OLED of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first emission unit EU1, a second emission unit EU2, and a charge generation layer CGL between the first emission unit EU1 and the second emission unit EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed throughout the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0185] The first emission unit EU1 of the first pixel PX1 may include a hole injection layer HIL, a hole transport layer HTL, a red emission layer REML, and an electron transport layer ETL sequentially stacked on the pixel electrode 211. The first emission unit EU1 of the second pixel PX2 may include a hole injection layer HIL, a hole transport layer HTL, a green emission layer GEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 211. The first emission unit EU1 of the third pixel PX3 may include a hole injection layer HIL, a hole transport layer HTL, a blue emission layer BEML, and an electron transport layer ETL sequentially stacked on the pixel electrode 211. Each of the hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL of the first emission unit EU1 may be a common layer continuously formed throughout the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0186] The second emission unit EU2 of the first pixel PX1 may include a hole transport layer HTL, an auxiliary layer AXL, a red emission layer REML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emission unit EU2 of the second pixel PX2 may include a hole transport layer HTL, a green emission layer GEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. The second emission unit EU2 of the third pixel PX3 may include a hole transport layer HTL, a blue emission layer BEML, and an electron transport layer ETL sequentially stacked on the charge generation layer CGL. Each of the hole transport layer HTL and the electron transport layer ETL of the second emission unit EU2 may be a common layer continuously formed throughout the first pixel PX1, the second pixel PX2, and the third pixel PX3. In an embodiment, the second emission unit EU2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may also include at least one of a hole blocking layer and a buffer layer between the emission layer and the electron transport layer ETL.

[0187] The thickness H1 of the red emission layer REML, the thickness H2 of the green emission layer GEML, and the thickness H3 of the blue emission layer BEML may be determined according to the resonance distance. The auxiliary layer AXL is a layer added to adjust the resonance distance and may include a resonance auxiliary material. As an example, the auxiliary layer AXL and the hole transport layer HTL may include the same material.

[0188] Despite Fig. 20 , the auxiliary layer AXL is provided only to the first pixel PX1, but the embodiment is not limited thereto. As an example, the auxiliary layer AXL may be provided to at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 to adjust the resonance distance of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0189] The display device may further include a capping layer 217 disposed on the outer surface of the counter electrode 215. The capping layer 217 may improve light emission efficiency based on the principle of constructive interference. Thus, the light extraction efficiency of the organic light emitting diode OLED is improved, and thus, the light emission efficiency of the organic light emitting diode OLED may be improved.

[0190] According to the embodiment, a display device with improved display quality can be provided. However, the scope of the present disclosure is not limited by this effect.

[0191] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the embodiments without departing substantially from the principles, spirit and scope of the present disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A pixel, wherein The pixels include: Light emitting element; A first transistor connected between a first voltage line and the light emitting element; a second transistor connected between the first voltage line and the first transistor; A third transistor connected between the first transistor and the light emitting element; and A fourth transistor is connected between the light emitting element and the second voltage line, wherein: The pixel is configured to emit light in a plurality of emission periods between a plurality of non-emission periods during one frame, and In a plurality of even-numbered non-emission periods among the plurality of non-emission periods, the second transistor is turned off, and the third transistor is turned on.

2. The pixel according to claim 1, wherein: The pixel is configured to emit light in at least four emission periods among the plurality of emission periods during the one frame.

3. The pixel according to claim 1, wherein: The fourth transistor is turned on in a plurality of odd-numbered non-emission periods among the plurality of non-emission periods, and Among the plurality of odd non-emission periods, a period during which the fourth transistor is turned on in each of the odd non-emission periods except a first non-emission period is greater than a period during which the fourth transistor is turned on in the first non-emission period.

4. The pixel according to claim 3, wherein: In a portion of the period during each of the plurality of odd-numbered non-emitting periods in which the fourth transistor is turned on, The second transistor is turned off, and the third transistor is turned on.

5. The pixel according to claim 3, wherein: During the odd-numbered non-transmission time periods other than the first non-transmission time period among the plurality of odd-numbered non-transmission time periods, After the third transistor is switched from the on state to the off state, the fourth transistor is switched from the off state to the on state.

6. The pixel according to claim 3, wherein: The first non-transmission period includes: a writing period in which a data signal is supplied to the pixel; a first period, before the writing period, during which the fourth transistor is turned on; and a second period, after the writing period, the fourth transistor is turned on in the second period, and During a portion of the second period, the second transistor is turned off and the third transistor is turned on.

7. The pixel according to claim 6, wherein: During the first period, the second transistor is turned off, and the third transistor is turned on.

8. The pixel according to claim 6, wherein: The pixel also includes: a fifth transistor connected between the third voltage line and the gate of the first transistor, wherein: The first non-emission period also includes a third period between the first period and the writing period, and The fifth transistor is turned on during the first period and the third period.

9. The pixel according to claim 8, wherein: During the third period, the second transistor is turned on, and the third transistor is turned off.

10. The pixel according to claim 1, wherein: The pixel also includes: a first capacitor connected between a gate of the first transistor and a node to which the first transistor and the third transistor are connected; and The second capacitor is connected between the first voltage line and the node.

11. A display device, wherein: The display device comprises: A plurality of pixels; and A driving circuit outputs a gate signal to the plurality of pixels, wherein: Each of the plurality of pixels comprises: Light emitting element; A first transistor connected between a first voltage line and the light emitting element; a second transistor connected between the first voltage line and the first transistor; A third transistor connected between the first transistor and the light emitting element; and a fourth transistor connected between the light emitting element and the second voltage line, The plurality of pixels are configured to emit light in a plurality of emission periods between a plurality of non-emission periods during one frame, and The driving circuit is configured to output a first gate signal of a gate-off voltage to the second transistor and a second gate signal of a gate-on voltage to the third transistor in a plurality of even-numbered non-emission periods among the plurality of non-emission periods.

12. The display device according to claim 11, wherein: The plurality of pixels are configured to emit light in at least four emission periods among the plurality of emission periods during the one frame.

13. The display device according to claim 11, wherein: The driving circuit is configured to output a third gate signal of a gate-on voltage to the fourth transistor in a plurality of odd-numbered non-emission periods among the plurality of non-emission periods, and Among the plurality of odd non-emission periods, a period during which the third gate signal is a gate-on voltage in each of the odd non-emission periods except a first non-emission period is greater than a period during which the third gate signal is a gate-on voltage in the first non-emission period.

14. The display device according to claim 13, wherein: The driving circuit is configured to output the first gate signal of the gate-off voltage and the second gate signal of the gate-on voltage in a portion of the period in which the third gate signal during each of the plurality of odd-numbered non-emission periods is a gate-on voltage.

15. The display device according to claim 13, wherein: The driving circuit is configured to: during the odd non-emission periods among the multiple odd non-emission periods except the first non-emission period, change the second gate signal from the gate-on voltage to the gate-off voltage and output the second gate signal, and then change the third gate signal from the gate-off voltage to the gate-on voltage and output the third gate signal.

16. The display device according to claim 13, wherein: The first non-emission period includes a writing period, a first period before the writing period, and a second period after the writing period, a data signal is supplied to the plurality of pixels during the writing period, the third gate signal is a gate-on voltage during the first period, the third gate signal is a gate-on voltage during the second period, and The driving circuit is configured to output the first gate signal of a gate-off voltage and the second gate signal of a gate-on voltage in a portion of the second period.

17. The display device according to claim 16, wherein: The driving circuit is configured to output the first gate signal of a gate-off voltage and the second gate signal of a gate-on voltage during the first period.

18. The display device according to claim 16, wherein: Each of the plurality of pixels further includes a fifth transistor connected between a third voltage line and a gate of the first transistor, The first non-emission period also includes a third period between the first period and the writing period, and The driving circuit is configured to output a fourth gate signal of a gate-on voltage to the fifth transistor during the first period and the third period.

19. The display device according to claim 18, wherein: The driving circuit is configured to output the first gate signal of a gate-on voltage and the second gate signal of a gate-off voltage during the third period.

20. The display device according to claim 11, wherein The driving circuit is configured to change a period during which the first gate signal is a gate-on voltage and a period during which the first gate signal is a gate-off voltage based on an emission ratio.

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