Display device

Abstract

The application provides a display device, comprising a display panel, the display panel comprising a multi-stage cascaded driving circuit, the driving circuit comprising a gate driving signal sub-circuit, an initialization signal sub-circuit and a reference signal sub-circuit. The gate driving signal sub-circuit, the initialization signal sub-circuit and the reference signal sub-circuit each comprise a plurality of oxide semiconductor transistors, wherein the bottom gate of an oxide semiconductor transistor prone to a negative bias effect is electrically connected to a potential control signal input end. By applying a negative voltage signal not higher than-5 volts to the bottom gate of the transistor, the threshold voltage of the transistor can be effectively adjusted, the generation of the negative bias effect can be prevented, the forward conduction characteristic of the transistor is not affected, and the narrow frame characteristic of the display device is maintained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device. BACKGROUND

[0002] In an organic electroluminescent display panel (OLED, Organic Light-Emitting Diode), in order to ensure the accurate control of each pixel light emission and avoid uneven light emission, an internal compensation circuit needs to be used. Since the internal compensation circuit has a high requirement on the characteristics of a thin film transistor (TFT, Thin Film Transistor) device, low temperature poly-silicon (LTPS, Low Temperature Poly-Silicon) is usually used as the semiconductor material of the TFT device.

[0003] However, the production cost of the LTPS TFT device is high, which leads to a high cost of the display panel product using the LTPS TFT device. In contrast, the production cost of the oxide semiconductor TFT device is low, but the device characteristics and stability are not as good as those of the LTPS TFT device, and it is difficult to simultaneously achieve high mobility and high stability characteristics.

[0004] In order to solve the above problems, the traditional organic electroluminescent display panel uses a hybrid process: using indium gallium zinc oxide (IGZO) material with good stability but low mobility in the pixel circuit to meet the internal compensation requirement of the pixel circuit; using high mobility oxide material in the driving circuit (GOA, Gate-driver On Array) to improve the driving ability of the circuit and meet the requirement of high refresh rate. However, in order to realize the internal compensation function of the pixel and meet the narrow frame requirement, at least three groups of driving sub-circuits need to be arranged in the driving circuit of the traditional organic electroluminescent display panel to output at least three groups of signals to the pixel. This requires the driving sub-circuit to use a simplified circuit architecture. Since the high mobility oxide material is prone to negative bias effect, the organic electroluminescent display panel using the simplified circuit architecture has a high risk of lighting and reliability. SUMMARY

[0005] The present application aims to provide a display device to solve the technical problem that the simplified driving circuit in the prior art is prone to negative bias effect.

[0006] An embodiment of the present application provides a display device, including a display panel, wherein the display panel includes a multi-stage cascaded driving circuit, the driving circuit includes a gate driving signal subcircuit, an initialization signal subcircuit and a reference signal subcircuit; wherein the gate driving signal subcircuit, the initialization signal subcircuit and the reference signal subcircuit each include a plurality of oxide semiconductor transistors, the bottom gates of at least a portion of the oxide semiconductor transistors in the gate driving signal subcircuit are electrically connected to a potential control signal input terminal, the bottom gates of at least a portion of the oxide semiconductor transistors in the initialization signal subcircuit are electrically connected to the potential control signal input terminal, and the bottom gates of at least a portion of the oxide semiconductor transistors in the reference signal subcircuit are electrically connected to the potential control signal input terminal.

[0007] In the above display device, the bottom gates of at least three oxide semiconductor transistors in the gate drive signal sub-circuit are electrically connected to the potential control signal input terminal.

[0008] In the above-mentioned display device, the gate drive signal subcircuit includes: a first transistor, the top gate of the first transistor is electrically connected to the post-stage initialization signal input terminal, the drain of the first transistor is electrically connected to the first node, the source of the first transistor is electrically connected to the first low-level power signal input terminal, and the bottom gate of the first transistor is electrically connected to the potential control signal input terminal; a second transistor, the top gate of the second transistor is electrically connected to the start signal input terminal, the drain of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the first low-level power signal input terminal, and the bottom gate of the second transistor is electrically connected to the potential control signal input terminal; and a third transistor, the source of the third transistor is electrically connected to the first low-level power signal input terminal, the drain of the third transistor is electrically connected to the first node, the top gate of the third transistor is electrically connected to the second node, and the bottom gate of the third transistor is electrically connected to the potential control signal input terminal.

[0009] In the above-mentioned display device, the gate drive signal subcircuit further includes: a fourth transistor, the top gate of the fourth transistor is electrically connected to the previous stage initialization signal input terminal, the source of the fourth transistor is electrically connected to the high-level power signal input terminal, and the drain of the fourth transistor is electrically connected to the first node; a fifth transistor, the source of the fifth transistor is electrically connected to the clock signal input terminal, the top gate of the fifth transistor is electrically connected to the first node, and the drain of the fifth transistor is electrically connected to the gate drive signal output terminal; a sixth transistor, the top gate of the sixth transistor is electrically connected to the second node, the source of the sixth transistor is electrically connected to the first low-level power signal input terminal, and the drain of the sixth transistor is electrically connected to the gate drive signal output terminal; a seventh transistor, the top gate and source of the seventh transistor are both electrically connected to the high-level power signal input terminal; an eighth a transistor, the top gate of the eighth transistor is electrically connected to the high-level power signal input terminal, the source of the eighth transistor is electrically connected to the drain of the seventh transistor, and the drain of the eighth transistor is electrically connected to the second node; a ninth transistor, the top gate of the ninth transistor is electrically connected to the first node, the drain of the ninth transistor is electrically connected to the second node, and the source of the ninth transistor is electrically connected to the first low-level power signal input terminal; a tenth transistor, the top gate of the tenth transistor is electrically connected to the previous-stage initialization signal input terminal, the drain of the tenth transistor is electrically connected to the second node, and the source of the tenth transistor is electrically connected to the first low-level power signal input terminal; and a first capacitor, the first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the gate drive signal output terminal.

[0010] In the above display device, the bottom gates of at least three oxide semiconductor transistors in the initialization signal sub-circuit are electrically connected to the potential control signal input terminal.

[0011] In the above-mentioned display device, the initialization signal subcircuit includes: an eleventh transistor, the top gate of the eleventh transistor is electrically connected to the subsequent initialization signal input terminal, the drain of the eleventh transistor is electrically connected to the third node, the source of the eleventh transistor is electrically connected to the first low-level power signal input terminal, and the bottom gate of the eleventh transistor is electrically connected to the potential control signal input terminal; a twelfth transistor, the top gate of the twelfth transistor is electrically connected to the start signal input terminal, the drain of the twelfth transistor is electrically connected to the third node, the source of the twelfth transistor is electrically connected to the first low-level power signal input terminal, and the bottom gate of the twelfth transistor is electrically connected to the potential control signal input terminal; and a thirteenth transistor, the source of the thirteenth transistor is electrically connected to the first low-level power signal input terminal, the top gate of the thirteenth transistor is electrically connected to the fourth node, the drain of the thirteenth transistor is electrically connected to the third node, and the bottom gate of the thirteenth transistor is electrically connected to the potential control signal input terminal.

[0012] In the above-mentioned display device, the initialization signal subcircuit further includes: a fourteenth transistor, the top gate of the fourteenth transistor is electrically connected to the previous stage initialization signal input terminal, the source of the fourteenth transistor is electrically connected to the high-level power signal input terminal, and the drain of the fourteenth transistor is electrically connected to the third node; a fifteenth transistor, the source of the fifteenth transistor is electrically connected to the clock signal input terminal, the top gate of the fifteenth transistor is electrically connected to the third node, and the drain of the fifteenth transistor is electrically connected to the initialization signal output terminal; a sixteenth transistor, the top gate of the sixteenth transistor is electrically connected to the fourth node, the source of the sixteenth transistor is electrically connected to the first low-level power signal input terminal, and the drain of the sixteenth transistor is electrically connected to the initialization signal output terminal; a seventeenth transistor, the top gate and source of the seventeenth transistor are both electrically connected to the high-level power signal input terminal; an eight transistor, the top gate of the eighteenth transistor being electrically connected to the high-level power signal input terminal, the source of the eighteenth transistor being electrically connected to the drain of the seventeenth transistor, and the drain of the eighteenth transistor being electrically connected to the fourth node; a nineteenth transistor, the top gate of the nineteenth transistor being electrically connected to the third node, the drain of the nineteenth transistor being electrically connected to the fourth node, and the source of the nineteenth transistor being electrically connected to the first low-level power signal input terminal; a twentieth transistor, the top gate of the twentieth transistor being electrically connected to the previous-stage initialization signal input terminal, the drain of the twentieth transistor being electrically connected to the fourth node, and the source of the twentieth transistor being electrically connected to the first low-level power signal input terminal; and a second capacitor, the first plate of the second capacitor being electrically connected to the third node, and the second plate of the second capacitor being electrically connected to the initialization signal output terminal.

[0013] In the above display device, the bottom gates of at least four oxide semiconductor transistors in the reference signal sub-circuit are electrically connected to the potential control signal input terminal.

[0014] In the above-mentioned display device, the reference signal subcircuit includes: a twenty-first transistor, the top gate of the twenty-first transistor is electrically connected to the gate drive signal output terminal of the current stage, the source of the twenty-first transistor is electrically connected to the first low-level power supply signal input terminal, the drain of the twenty-first transistor is electrically connected to the fifth node, and the bottom gate of the twenty-first transistor is electrically connected to the potential control signal input terminal; a twenty-second transistor, the top gate of the twenty-second transistor is electrically connected to the gate drive signal output terminal of the current stage, the drain of the twenty-second transistor is electrically connected to the seventh node, the source of the twenty-second transistor is electrically connected to the gate drive signal output terminal of the current stage, and the bottom gate of the twenty-second transistor is electrically connected to the potential control signal input terminal. a twenty-third transistor, the top gate of the twenty-third transistor is electrically connected to the initialization signal input terminal of this stage, the drain of the twenty-third transistor is electrically connected to the seventh node, the source of the twenty-third transistor is electrically connected to the first low-level power supply signal input terminal, and the bottom gate of the twenty-third transistor is electrically connected to the potential control signal input terminal; and a twenty-fourth transistor, the source of the twenty-fourth transistor is electrically connected to the first low-level power supply signal input terminal, the drain of the twenty-fourth transistor is electrically connected to the fifth node, the top gate of the twenty-fourth transistor is electrically connected to the sixth node, and the bottom gate of the twenty-fourth transistor is electrically connected to the potential control signal input terminal.

[0015] In the above-mentioned display device, the reference signal sub-circuit further includes: a twenty-fifth transistor, the top gate of the twenty-fifth transistor is electrically connected to the current-stage initialization signal input terminal, the source of the twenty-fifth transistor is electrically connected to the high-level power signal input terminal, and the drain of the twenty-fifth transistor is electrically connected to the fifth node; a twenty-sixth transistor, the source of the twenty-sixth transistor is electrically connected to the second high-level power signal input terminal, the top gate of the twenty-sixth transistor is electrically connected to the fifth node, and the drain of the twenty-sixth transistor is electrically connected to the reference signal output terminal; a twenty-seventh transistor, the top gate of the twenty-seventh transistor is electrically connected to the sixth node, the source of the twenty-seventh transistor is electrically connected to the second low-level power signal input terminal, and the drain of the twenty-seventh transistor is electrically connected to the reference signal output terminal; a twenty-eighth transistor, the drain of the twenty-eighth transistor is electrically connected to the sixth node, and the source of the twenty-eighth transistor is electrically connected to the sixth node. a first plate of the third capacitor is electrically connected to the fifth node, and a second plate of the third capacitor is electrically connected to the reference signal output terminal; and a fourth capacitor, a first plate of the fourth capacitor is electrically connected to the sixth node, and a second plate of the fourth capacitor is electrically connected to the seventh node.

[0016] In the above display device, the voltage value of the signal input to the potential control signal input terminal is not higher than -5V.

[0017] The display device provided by the present application is based on the existing simplified driving circuit. By electrically connecting the bottom gate of the oxide semiconductor transistor that is prone to negative bias effect in the gate drive signal subcircuit, the initialization signal subcircuit and the reference signal subcircuit to the potential control signal input terminal, a negative voltage signal is applied to the bottom gate of these oxide semiconductor transistors that are prone to negative bias effect to effectively adjust the threshold voltage of these transistors, thereby preventing them from generating a negative bias effect. Specifically, when a negative voltage signal is applied to the bottom gate, the carrier concentration in the channel region of the transistor can be reduced, thereby increasing the threshold voltage of the transistor and keeping it within a suitable adjustable range. This method of controlling the bottom gate voltage solves the technical problem that the simplified gate drive circuit in the prior art is prone to negative bias effect, and does not affect the forward conduction characteristics of the transistor. Therefore, the normal working performance of the transistor can be maintained while preventing the negative bias effect, thereby improving the reliability and stability of the display device.

[0018] The technical solution of this application does not require the addition of additional negative bias protection circuit units, thus not significantly increasing the circuit area. This allows the display device provided by this application to effectively address the negative bias issue that high-mobility oxide semiconductor transistors are prone to while maintaining narrow bezel characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of a display device provided in an embodiment of the present application.

[0020] Figure 2 4 is a circuit diagram of a gate drive signal subcircuit in a display device provided by an embodiment of the present application.

[0021] Figure 3 4 is a circuit diagram of an initialization signal sub-circuit in a display device provided by an embodiment of the present application.

[0022] Figure 4 4 is a circuit diagram of a reference signal subcircuit in a display device provided by an embodiment of the present application.

[0023] Figure 5 Schematic diagram of some transistors of a gate drive signal subcircuit, an initialization signal subcircuit, and a reference signal subcircuit in a display device provided by an embodiment of the present application.

[0024] Figure 6 Schematic diagram of the change trend of the threshold voltage of the high-mobility oxide transistor under different bottom gate voltages.

[0025] Figure 7 Schematic diagram of the correlation between the slope a and the intercept b in the threshold voltage and bottom gate voltage relationship curve y=ax+b and the threshold voltage. DETAILED DESCRIPTION

[0026] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0027] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0028] The embodiments of the present application may be combined with each other.

[0029] The display device provided in the embodiments of the present application may be, for example, an OLED display device, a Mini-LED display device, or a Micro-LED display device. The embodiments of the present application are described using an OLED display device as an example.

[0030] like Figure 1 As shown, the display device provided in the embodiment of the present application includes a display panel, a timing controller, a source driving circuit and a power management chip (the power management chip and the timing controller can be integrated into the same chip). The display panel is an organic light emitting diode display panel.

[0031] The display panel includes a display area and a non-display area. The display area is provided with m×n pixel units PX arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange drive circuits and various signal lines. The display panel also includes multiple gate drive signal lines Gout[n], multiple initialization signal lines INI[n], multiple reference signal lines REF[n], multiple data lines DATA, and a gate drive circuit. The multiple gate drive signal lines Gout[n], multiple initialization signal lines INI[n], and multiple reference signal lines REF[n] extend along a first direction and are arranged along a second direction, and the multiple data lines DATA extend along the second direction and are arranged along the first direction, with the first direction being perpendicular to the second direction. The gate drive circuit is provided in the non-display area and is electrically connected to the multiple gate drive signal lines Gout[n], multiple initialization signal lines INI[n], and multiple reference signal lines REF[n]. The source drive circuit is electrically connected to the multiple data lines DATA via a flexible printed circuit board. The timing controller is electrically connected to the gate driving circuit and the source driving circuit respectively.

[0032] The display panel includes an organic light-emitting diode array substrate and an encapsulation layer. The organic light-emitting diode array substrate includes a base substrate, a buffer layer disposed on the base substrate, an active layer disposed on the buffer layer, a gate insulating layer disposed on the active layer, a first metal layer disposed on the gate insulating layer, an interlayer insulating layer disposed on the first metal layer, a second metal layer disposed on the interlayer insulating layer, a planarization layer disposed on the second metal layer, a first electrode layer disposed on the planarization layer, a pixel defining layer disposed on the first electrode layer, an organic light-emitting layer disposed within an opening defined by the pixel defining layer, and a second electrode layer disposed on the organic light-emitting layer. The first metal layer includes gate drive signal lines Gout[n], initialization signal lines INI[n], reference signal lines REF[n], a gate electrode, etc. The second metal layer includes data lines DATA, a source electrode, a drain electrode, etc. The encapsulation layer is sealed to the organic light-emitting diode array substrate to prevent moisture and oxygen from invading the organic light-emitting layer.

[0033] Each pixel unit PX includes a pixel driving circuit and an organic light-emitting diode OLED (light-emitting device). The pixel driving circuit includes at least two thin-film transistors and a storage capacitor. One of the thin-film transistors serves as a switching transistor, with its gate electrically connected to the corresponding scan line and its source electrically connected to the corresponding data line; the other thin-film transistor serves as a driving transistor, with its gate electrically connected to the drain of the switching transistor, its source electrically connected to the first power supply voltage line, and its drain electrically connected to the anode of the organic light-emitting diode OLED. One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end is electrically connected to the source or drain of the driving transistor. The cathode of the organic light-emitting diode OLED is electrically connected to the second power supply voltage line.

[0034] The gate drive circuit includes n cascaded gate drive units, each of which is electrically connected to a scan line. Under the control of the timing controller, the gate drive unit sequentially outputs scan signals to scan each row of pixel units PX in the display area line by line. Under the control of the timing controller, the source drive circuit generates and outputs data signals based on image data. The timing controller is used to receive and process external image data and timing signals, generate control signals, and transmit image data to the source drive circuit. The power management chip is used to provide operating voltages for various parts of the display device, including providing a second power supply voltage VSS to the cathode of the organic light-emitting diode OLED, providing a first power supply voltage VDD to the first power supply voltage line, and providing a gate drive voltage VGH / VGL to the gate drive circuit.

[0035] The present application provides a display device, which includes a display panel, and the display panel includes a multi-stage cascade drive circuit. In order to drive the pixel circuit of the 4T1C structure in the display panel, the drive circuit needs to output a gate drive signal Gout[n], an initialization signal INI[n] and a reference signal REF[n] to the pixel circuit of the 4T1C structure. To this end, the drive circuit includes a gate drive signal subcircuit (such as Figure 2 As shown), initialization signal sub-circuit (as shown Figure 3 ) and the reference signal subcircuit (as shown Figure 4 shown).

[0036] The pixel driving circuit of the 4T1C structure includes a driving transistor, a switching transistor, an initialization transistor, a compensation transistor, and a storage capacitor. The gate of the driving transistor is electrically connected to the first plate of the storage capacitor, the source of the driving transistor is electrically connected to the first power supply voltage line VDD, and the drain of the driving transistor is electrically connected to the anode of the organic light-emitting diode OLED; the gate of the switching transistor is electrically connected to the gate driving signal input terminal Gout[n], the source of the switching transistor is electrically connected to the data line DATA, and the drain of the switching transistor is electrically connected to the gate of the driving transistor; the gate of the initialization transistor is electrically connected to the initialization signal input terminal INI[n], the source of the initialization transistor is electrically connected to the initialization voltage terminal, and the drain of the initialization transistor is electrically connected to the anode of the organic light-emitting diode OLED; the gate of the compensation transistor is electrically connected to the reference signal input terminal REF[n], the source of the compensation transistor is electrically connected to the reference voltage input terminal, and the drain of the compensation transistor is electrically connected to the gate of the driving transistor; the second plate of the storage capacitor is electrically connected to the drain of the driving transistor; and the cathode of the organic light-emitting diode OLED is electrically connected to the second power supply voltage line VSS. The pixel driving circuit of the 4T1C structure does not use a light emitting control signal to control the light emitting of the organic light emitting diode OLED, but controls the on or off of the driving transistor itself to realize the on and off of the current path of the organic light emitting diode OLED.

[0037] To meet the narrow bezel requirements of display panels, the gate drive signal subcircuit and initialization signal subcircuit both utilize a minimalist 10T1C (10 transistors and 1 capacitor) circuit architecture, while the reference signal subcircuit utilizes a minimalist 10T2C (10 transistors and 2 capacitors) circuit architecture. These three subcircuits require 14 input signals, including 8 clock signals (CK), 2 high-level power signals (VGH), 2 low-level power signals (VGL), 1 start signal (STV), and 1 vertical synchronization signal (VST).

[0038] In order to meet the driving capability requirements and achieve miniaturization of transistor size, the transistors in these sub-circuits are all top-gate transistors, and their semiconductor layers use high-mobility oxide materials. The high-mobility oxide material refers to a material with a mobility higher than that of indium gallium zinc oxide (IGZO) material. Specifically, the high-mobility oxide material can be selected from the following materials: In-Sn-O (ITO) material, In-WO (IWO) material, In-Zn-WO (IZWO) material, In-Ti-O (ITiO) material. Using high-mobility oxide material as the semiconductor layer can meet the driving capability requirements and achieve miniaturization of transistor size.

[0039] However, high-mobility oxide materials are prone to negative bias effects, which leads to a higher risk of failure in traditional minimalist circuit architectures. Specifically, in the gate drive signal subcircuit and initialization signal subcircuit, transistors T42_1, TrQ_1, and T41_1, as well as transistors T42_2, TrQ_2, and T41_2 are prone to negative bias effects; in the reference signal subcircuit, transistors T41_3, T51_3, T51A_3, and T42_3 are also prone to negative bias effects. The negative bias effect of these transistors can cause the threshold voltage (Vth) to decrease, making it impossible for the transistor to be completely turned off when it should be turned off, thereby affecting the normal operation of the display panel.

[0040] In order to solve this problem, the present application electrically connects the bottom gates of the transistors that are prone to negative bias effects to the potential control signal input terminal LS.

[0041] Specifically, if Figure 5 As shown, each transistor includes a top gate GE, a source, and a drain. The top gate GE is located above the semiconductor layer Active, with a gate insulating layer GI disposed between the top gate GE and the semiconductor layer. The transistors in these sub-circuits that are prone to negative bias also include a bottom gate LS, which is located below the semiconductor layer Active. The bottom gate LS is composed of a light shield layer (light shield), which not only has a light-shielding function but also serves as the bottom gate (second gate) of the transistor.

[0042] like Figure 6As shown in the figure, the threshold voltage (Vth) change trend of high-mobility oxide transistors under different LS (light shielding layer, which acts as the bottom gate of the transistor) voltages is shown. Under the premise of ensuring that the product frame is not lost, by adjusting the voltage of the bottom gate of the high-mobility oxide transistor with a top gate structure, the threshold voltage of these transistors that are prone to negative bias effects can be adjusted so that they are within the adjustment range (Vth Margin) of the threshold voltage of the transistor. The figure contains test data from 5 different test points (990B0-C2, 996C0-B1, 990B0-A2, 990B0-B1, 990B0-F1). The horizontal axis is the LS voltage, ranging from -11 volts to 0 volts; the vertical axis is the threshold voltage Vth, ranging from 0 volts to 8 volts. Through experimental research, it was found that when a negative voltage of no more than -5 volts is input to the potential control signal input terminal LS, these transistors can be effectively prevented from generating negative bias effects. Experimental data show that within the potential control signal input range of -12V to 2V, there is a good linear relationship between the threshold voltage of the transistor and the potential control signal, with a correlation coefficient R 2 Reached 0.999.

[0043] Specifically, at these five different test points, as the LS voltage increases from -12 volts to 0 volts, the threshold voltage Vth of the transistor shows a linear downward trend. When the LS voltage is -12 volts, the threshold voltage Vth of each test point is between 5.0 volts and 6.2 volts; when the LS voltage is 0 volts, the threshold voltage Vth of each test point drops to between 0.5 volts and 1.5 volts. The threshold voltage Vth of all test points shows a linear relationship with the LS voltage of y = ax + b, where a is the slope and b is the intercept. This consistent linear change trend confirms that the threshold voltage Vth of high-mobility oxide transistors can be effectively controlled by adjusting the LS voltage.

[0044] like Figure 7 As shown, the figure shows the correlation between the slope a and intercept b in the Vth-LS voltage relationship curve y=ax+b and the threshold voltage Vth. The figure contains two sets of data: the red dot represents the slope (Slope), and the blue dot represents the intercept (Intercept). The horizontal axis is the threshold voltage Vth, ranging from 0.4 volts to 1.6 volts; the vertical axis on the left is the slope, ranging from -0.42 to -0.24; the vertical axis on the right is the intercept, ranging from 0.2 volts to 1.6 volts. Further research found that the slope a of different test points is similar, fluctuating between -0.40 and -0.35, indicating that the response characteristics of different points to the LS voltage are similar. The intercept b and the threshold voltage Vth (that is, the threshold voltage when the LS voltage is 0 volts) show a good linear correlation, and the correlation coefficient R 2Reaching 0.99. This means that the required LS voltage value can be predicted by measuring the threshold voltage Vth, thereby accurately controlling the threshold voltage Vth of the transistor. For example, when the threshold voltage Vth = 0 volts, by giving the LS a negative bias of -4 volts, Vth can be adjusted to above 1.5 volts. In addition, after adjusting the Vth of the high-mobility oxide transistor by negatively biasing the LS, the forward bias stability (ΔVth) did not deteriorate significantly and remained at basically the same level, indicating that this solution has a low risk to the reliability of the driving circuit.

[0045] More importantly, the solution of the present application for preventing the negative bias effect by controlling the bottom gate voltage will not affect the forward bias stability of the transistor.

[0046]

[0047] Table 1

[0048] Table 1 shows the trend of the forward bias stability (ΔVth) under different LS voltages. In Table 1, the threshold voltage changes of the transistor in the linear region (Vth-lin) and saturation region (Vth-sat) were tested under three voltage conditions: LS = 0 volts, LS = -4 volts, and LS = -8 volts. Vth-lin refers to the threshold voltage measured when the transistor operates in the linear region (i.e., the voltage VDS between the drain and source is small, and the drain current ID has a linear relationship with VDS). Vth-sat refers to the threshold voltage measured when the transistor operates in the saturation region (i.e., the voltage VDS between the drain and source is large, and the drain current ID tends to saturation as VDS increases).

[0049] Experimental data shows that at 0 seconds, as the LS voltage increases (from 0V to -8V), the threshold voltage Vth of the transistor shows an upward trend. For example, in the linear region, the threshold voltage Vth is 1.71V when LS = 0V, rises to 2.36V when LS = -4V, and further rises to 3.90V when LS = -8V. This trend also shows a similar pattern in the saturation region.

[0050] After 3600 seconds of positive bias stress testing, the threshold voltage Vth under each condition increased, but ΔVth (i.e., the difference between Vth at 3600 seconds and Vth at 0 seconds) did not deteriorate with the increase of LS voltage. Specifically, in the linear region, when LS = 0 volts, ΔVth is 1.43 volts, when LS = -4 volts, ΔVth is 1.39 volts, and when LS = -8 volts, ΔVth is 1.29 volts; in the saturation region, when LS = 0 volts, ΔVth is 1.29 volts, when LS = -4 volts, ΔVth is 0.94 volts, and when LS = -8 volts, ΔVth is 1.09 volts. This result is in sharp contrast to the phenomenon in traditional technical solutions that the larger the LS voltage, the easier it is to deteriorate ΔVth, confirming that the technical solution proposed in this application does not affect the stability of the device while adjusting the threshold voltage Vth.

[0051] Based on the above research results, this application provides the following technical solutions.

[0052] The gate drive signal sub-circuit, the initialization signal sub-circuit and the reference signal sub-circuit each include a plurality of oxide semiconductor transistors, the bottom gates of at least a portion of the oxide semiconductor transistors in the gate drive signal sub-circuit are electrically connected to the potential control signal input terminal LS, the bottom gates of at least a portion of the oxide semiconductor transistors in the initialization signal sub-circuit are electrically connected to the potential control signal input terminal LS, and the bottom gates of at least a portion of the oxide semiconductor transistors in the reference signal sub-circuit are electrically connected to the potential control signal input terminal LS.

[0053] The voltage value of the signal input to the potential control signal input terminal LS is not higher than -5V.

[0054] like Figure 2As shown, the gate drive signal subcircuit includes first to tenth transistors and a first capacitor C1. The bottom gates of at least three oxide semiconductor transistors in the gate drive signal subcircuit are electrically connected to the potential control signal input terminal LS. Specifically, the bottom gates of the first transistor T41_1, the second transistor TrQ_1 and the third transistor T42_1 are all electrically connected to the bottom gate control signal input terminal LS. Specifically, the gate drive signal subcircuit includes a first transistor T41_1, a second transistor TrQ_1 and a third transistor T42_1; the top gate of the first transistor T41_1 is electrically connected to the post-stage initialization signal input terminal INI[n+2], the drain of the first transistor T41_1 is electrically connected to the first node Q[n]_1, the source of the first transistor T41_1 is electrically connected to the first low-level power supply signal input terminal VGL1, and the bottom gate of the first transistor T41_1 is electrically connected to the potential control signal input terminal LS; the top gate of the second transistor TrQ_1 is electrically connected to the start signal input terminal VST, and the second transistor T42_1 is electrically connected to the start signal input terminal VST. The drain of the body transistor TrQ_1 is electrically connected to the first node Q[n]_1, the source of the second transistor TrQ_1 is electrically connected to the first low-level power signal input terminal VGL1, and the bottom gate of the second transistor TrQ_1 is electrically connected to the potential control signal input terminal LS; the source of the third transistor T42_1 is electrically connected to the first low-level power signal input terminal VGL1, the drain of the third transistor T42_1 is electrically connected to the first node Q[n]_1, the top gate of the third transistor T42_1 is electrically connected to the second node K[n]_1, and the bottom gate of the third transistor T42_1 is electrically connected to the potential control signal input terminal LS.

[0055] These three transistors form a pull-down unit, which is used to pull the first node Q[n]_1 to a low level when the gate drive signal output needs to be turned off. By applying a negative voltage to the bottom gates of these transistors, their threshold voltage Vth can be prevented from decreasing (increasing the threshold voltage), ensuring that they are completely cut off when turned off.

[0056] The gate drive signal sub-circuit further includes a fourth transistor T11_1 , a fifth transistor T21_1 , a sixth transistor T31_1 , a seventh transistor T51_1 , an eighth transistor T511_1 , a ninth transistor T52_1 , a tenth transistor T54_1 , and a first capacitor C1 .

[0057] The top gate of the fourth transistor T11_1 is electrically connected to the previous stage initialization signal INI[n-2], the source is electrically connected to the first high-level power supply signal input terminal VGH1, and the drain is electrically connected to the first node Q[n]_1. The fourth transistor T11_1 is used to transmit the first high-level power supply signal VGH1 to the first node Q[n]_1 under the control of the previous stage initialization signal INI[n-2]. The source of the fifth transistor T21_1 is electrically connected to the clock signal input terminal CK, the top gate is electrically connected to the first node Q[n]_1, and the drain is electrically connected to the gate drive signal output terminal Gout[n]. The fifth transistor T21_1 is electrically connected to the first node Q[n]_1. The clock signal CK is transmitted to the gate drive signal output terminal Gout[n] under the control of the point Q[n]_1; the top gate of the sixth transistor T31_1 is electrically connected to the second node K[n]_1, the source is electrically connected to the first low-level power signal input terminal VGL1, and the drain is electrically connected to the gate drive signal output terminal Gout[n]. The sixth transistor T31_1 transmits the first low-level power signal VGL1 to the gate drive signal output terminal Gout[n] under the control of the second node K[n]_1; the seventh transistor T51_1 and the eighth transistor T511_1 form a dual-transistor structure, wherein the seventh transistor T51_1 The top gate and source of the eighth transistor T511_1 are both electrically connected to the first high-level power signal input terminal VGH1, the top gate of the eighth transistor T511_1 is electrically connected to the first high-level power signal input terminal VGH1, the source of the eighth transistor T511_1 is electrically connected to the drain of the seventh transistor T51_1, the drain of the eighth transistor T511_1 is electrically connected to the second node K[n]_1, and the seventh transistor T51_1 and the eighth transistor T511_1 are used to control the level of the second node K[n]_1; the top gate of the ninth transistor T52_1 is electrically connected to the first node Q[n]_1, the drain is electrically connected to the second node K[n]_1, and the source is electrically connected to the first node Q[n]_1. A low-level power signal input terminal VGL1 is electrically connected, the top gate of the tenth transistor T54_1 is electrically connected to the previous-stage initialization signal INI[n-2], the drain is electrically connected to the second node K[n]_1, and the source is electrically connected to the first low-level power signal input terminal VGL1. The ninth transistor T52_1 and the tenth transistor T54_1 are used to pull the second node K[n]_1 to a low level at a specific moment; the first plate of the first capacitor C1 is electrically connected to the first node Q[n]_1, and the second plate is electrically connected to the gate drive signal output terminal Gout[n]. The first capacitor C1 is used to maintain the level of the first node Q[n]_1.

[0058] like Figure 4As shown, the initialization signal sub-circuit includes the eleventh transistor T41_2 to the twentieth transistor T54_2 and the second capacitor C2, and the bottom gates of at least three oxide semiconductor transistors in the initialization signal sub-circuit are electrically connected to the potential control signal input end LS. Specifically, the bottom gates of the eleventh transistor T41_2, the twelfth transistor TrQ_2 and the thirteenth transistor T42_2 are electrically connected to the bottom gate control signal input end LS. The three transistors also constitute a pull-down unit, and the negative bias effect is prevented by bottom gate voltage control.

[0059] Specifically, the initialization signal sub-circuit includes the eleventh transistor T41_2, the twelfth transistor TrQ_2, the thirteenth transistor T42_2, the fourteenth transistor T11_2, the fifteenth transistor T21_2, the sixteenth transistor T31_2, the seventeenth transistor T51_2, the eighteenth transistor T511_2, the nineteenth transistor T52_2, the twentieth transistor T54_2 and the second capacitor C2. The top gate of the eleventh transistor T41_2 is electrically connected to the subsequent initialization signal input end INI[n+2], the drain of the eleventh transistor T41_2 is electrically connected to the third node Q[n]_2, the source of the eleventh transistor T41_2 is electrically connected to the first low-level power signal input end VGL1, and the bottom gate of the eleventh transistor T41_2 is electrically connected to the potential control signal input end LS; the top gate of the twelfth transistor TrQ_2 is electrically connected to the start signal input end VST, the drain of the twelfth transistor TrQ_2 is electrically connected to the third node Q[n]_2, the source of the twelfth transistor TrQ_2 is electrically connected to the first low-level power signal input end VGL1, and the bottom gate of the twelfth transistor TrQ_2 is electrically connected to the potential control signal input end LS; the source of the thirteenth transistor T42_2 is electrically connected to the first low-level power signal input end VGL1, the top gate of the thirteenth transistor T42_2 is electrically connected to the fourth node K[n]_2, the drain of the thirteenth transistor T42_2 is electrically connected to the third node Q[n]_2, and the bottom gate of the thirteenth transistor T42_2 is electrically connected to the potential control signal input end LS.

[0060] The top gate of the fourteenth transistor T11_2 is electrically connected to the previous stage initialization signal input terminal INI[n-2], the source of the fourteenth transistor T11_2 is electrically connected to the high level power signal input terminal VGH, and the drain of the fourteenth transistor T11_2 is electrically connected to the third node Q[n]_2; the source of the fifteenth transistor T21_2 is electrically connected to the clock signal input terminal CK, the top gate of the fifteenth transistor T21_2 is electrically connected to the third node Q[n]_2, and the drain of the fifteenth transistor T21_2 is electrically connected to the third node Q[n]_2. The drain of the sixteenth transistor T31_2 is electrically connected to the initialization signal output terminal INI[n]; the top gate of the sixteenth transistor T31_2 is electrically connected to the fourth node K[n]_2, the source of the sixteenth transistor T31_2 is electrically connected to the first low-level power signal input terminal VGL1, and the drain of the sixteenth transistor T31_2 is electrically connected to the initialization signal output terminal INI[n]; the top gate and source of the seventeenth transistor T51_2 are both electrically connected to the high-level power signal input terminal VGH; the top gate of the eighteenth transistor T511_2 is electrically connected to the fourth node K[n]_2, the source of the sixteenth transistor T31_2 is electrically connected to the first low-level power signal input terminal VGL1, and the drain of the sixteenth transistor T31_2 is electrically connected to the initialization signal output terminal INI[n]; the top gate and source of the seventeenth transistor T51_2 are both electrically connected to the high-level power signal input terminal VGH; The top gate of the eighteenth transistor T511_2 is electrically connected to the high-level power signal input terminal VGH, the source of the eighteenth transistor T511_2 is electrically connected to the drain of the seventeenth transistor T51_2, and the drain of the eighteenth transistor T511_2 is electrically connected to the fourth node K[n]_2; the top gate of the nineteenth transistor T52_2 is electrically connected to the third node Q[n]_2, the drain of the nineteenth transistor T52_2 is electrically connected to the fourth node K[n]_2, and the source of the nineteenth transistor T52_2 is electrically connected to the first low-level power signal input terminal VGH. The top gate of the twentieth transistor T54_2 is electrically connected to the previous-stage initialization signal input terminal INI[n-2], the drain of the twentieth transistor T54_2 is electrically connected to the fourth node K[n]_2, and the source of the twentieth transistor T54_2 is electrically connected to the first low-level power supply signal input terminal VGL1; the first plate of the second capacitor C2 is electrically connected to the third node Q[n]_2, and the second plate of the second capacitor C2 is electrically connected to the initialization signal output terminal INI[n].

[0061] like Figure 4As shown, the reference signal subcircuit includes the 21st transistor T41_3 to the 30th transistor T56_3 and the third and fourth capacitors C3 and C4. The bottom gates of at least four oxide semiconductor transistors in the reference signal subcircuit are electrically connected to the potential control signal input terminal LS. Specifically, the bottom gates of the 21st transistor T41_3, the 22nd transistor T51_3, the 23rd transistor T51A_3, and the 24th transistor T42_3 are all electrically connected to the bottom gate control signal input terminal LS. These four transistors also prevent negative bias effects by controlling the bottom gate voltage. The reference signal sub-circuit adopts a 10T2C structure. Specifically, the reference signal sub-circuit includes a twenty-first transistor T41_3, a twenty-second transistor T51_3, a twenty-third transistor T51A_3, a twenty-fourth transistor T42_3, a twenty-fifth transistor T11_3, a twenty-sixth transistor T21_3, a twenty-seventh transistor T31_3, a twenty-eighth transistor T52_3, a twenty-ninth transistor T54_3, a thirtieth transistor T56_3, a third capacitor C3, and a fourth capacitor C4. The top gate of the twenty-first transistor T41_3 is electrically connected to the gate drive signal output terminal Gout[n] of the current stage, the source of the twenty-first transistor T41_3 is electrically connected to the first low-level power supply signal input terminal VGL1, the drain of the twenty-first transistor T41_3 is electrically connected to the fifth node Q[n]_3, and the bottom gate of the twenty-first transistor T41_3 is electrically connected to the potential control signal input terminal LS; the top gate of the twenty-second transistor T51_3 is electrically connected to the gate drive signal output terminal Gout[n] of the current stage, the drain of the twenty-second transistor T51_3 is electrically connected to the seventh node T[n], the source of the twenty-second transistor T51_3 is electrically connected to the gate drive signal output terminal Gout[n] of the current stage, and the bottom gate of the twenty-second transistor T51_3 is electrically connected to the potential control signal input terminal LS. The top gate of the twenty-third transistor T51A_3 is electrically connected to the initialization signal input terminal INI[n] of the current stage, the drain of the twenty-third transistor T51A_3 is electrically connected to the seventh node T[n], the source of the twenty-third transistor T51A_3 is electrically connected to the first low-level power signal input terminal VGL1, and the bottom gate of the twenty-third transistor T51A_3 is electrically connected to the potential control signal input terminal LS; the source of the twenty-fourth transistor T42_3 is electrically connected to the first low-level power signal input terminal VGL1, the drain of the twenty-fourth transistor T42_3 is electrically connected to the fifth node Q[n]_3, the top gate of the twenty-fourth transistor T42_3 is electrically connected to the sixth node K[n]_3, and the bottom gate of the twenty-fourth transistor T42_3 is electrically connected to the potential control signal input terminal LS;The top gate of the twenty-fifth transistor T11_3 is electrically connected to the initialization signal input terminal INI[n] of the current stage, the source of the twenty-fifth transistor T11_3 is electrically connected to the high-level power signal input terminal VGH, and the drain of the twenty-fifth transistor T11_3 is electrically connected to the fifth node Q[n]_3; the source of the twenty-sixth transistor T21_3 is electrically connected to the second high-level power signal input terminal VGH2, the top gate of the twenty-sixth transistor T21_3 is electrically connected to the fifth node Q[n]_3, and the drain of the twenty-sixth transistor T11_3 is electrically connected to the fifth node Q[n]_3. The drain of the twenty-seventh transistor T21_3 is electrically connected to the reference signal output terminal REF[n]; the top gate of the twenty-seventh transistor T31_3 is electrically connected to the sixth node K[n]_3, the source of the twenty-seventh transistor T31_3 is electrically connected to the second low-level power signal input terminal VGL2, and the drain of the twenty-seventh transistor T31_3 is electrically connected to the reference signal output terminal REF[n]; the drain of the twenty-eighth transistor T52_3 is electrically connected to the sixth node K[n]_3, and the source of the twenty-eighth transistor T52_3 is electrically connected to the first low-level power signal input terminal VGL2. The top gate of the twenty-eighth transistor T52_3 is electrically connected to the high-level power signal input terminal VGL1, the top gate of the twenty-eighth transistor T52_3 is electrically connected to the fifth node Q[n]_3; the source of the twenty-ninth transistor T54_3 is electrically connected to the high-level power signal input terminal VGH, the drain of the twenty-ninth transistor T54_3 is electrically connected to the sixth node K[n]_3, and the top gate of the twenty-ninth transistor T54_3 is electrically connected to the seventh node T[n]; the top gate of the thirtieth transistor T56_3 is electrically connected to the initialization signal input terminal INI[n] of this stage The source of the 30th transistor T56_3 is electrically connected to the first low-level power signal input terminal VGL1, and the drain of the 30th transistor T56_3 is electrically connected to the sixth node K[n]_3. The first plate of the third capacitor C3 is electrically connected to the fifth node Q[n]_3, and the second plate of the third capacitor C3 is electrically connected to the reference signal output terminal REF[n]. The first plate of the fourth capacitor C4 is electrically connected to the sixth node K[n]_3, and the second plate of the fourth capacitor C4 is electrically connected to the seventh node T[n].

[0062] Through this improved technical solution, the present application can optimize the threshold voltage adjustment range (Vth Margin) from the original 0.5 to 5.4 volts to -2.2 to 5.4 volts, significantly widening the adjustable range of the threshold voltage. This optimization enables the driver circuit to better adapt to the characteristics of high-mobility oxide transistors, greatly improving the feasibility of the circuit. More importantly, this improvement does not significantly increase the border width of the display panel, maintaining the narrow border characteristics of the product.

[0063] In a specific implementation, the voltage of the bottom gate control signal input terminal LS is not higher than -5 V, and preferably can be adjusted within the range of -12 V to -5 V. For example, the specific voltage values ​​that can be selected include but are not limited to:

[0064] -12 volts, -11 volts, -10 volts, -9 volts, -8 volts, -7 volts, -6 volts, -5 volts. By adjusting the voltage of the bottom gate control signal input end LS, the threshold voltage of each transistor can be accurately controlled, thereby ensuring the normal operation of the driving circuit.

[0065] Experimental data show that when the voltage of the bottom gate control signal input end LS is -4 volts, the threshold voltage of the transistor can be adjusted to 1.5 volts or more, which is sufficient to prevent the generation of negative bias effect. At the same time, at this voltage value, the positive bias stability (△Vth) of the transistor does not deteriorate significantly. For example, in the linear region, when LS = 0 volts, △Vth is 1.43 volts, when LS = -4 volts, △Vth is 1.39 volts, and when LS = -8 volts, △Vth is 1.29 volts; in the saturation region, when LS = 0 volts, △Vth is 1.29 volts, when LS = -4 volts, △Vth is 0.94 volts, and when LS = -8 volts, △Vth is 1.09 volts. This shows that the technical solution proposed in the present application not only effectively prevents negative bias effect, but also does not affect the positive bias stability of the transistor, thereby ensuring the reliability and stability of the display device.

[0066] Through the above technical solution, the display device provided by the present application successfully solves the technical problem that the simplified driving circuit in the prior art is prone to negative bias effect. This scheme not only effectively prevents negative bias effect, but also does not affect the positive bias stability of the transistor, while maintaining the narrow frame feature of the display device. This scheme is particularly suitable for OLED display panels that require narrow frame design.

[0067] The embodiments of the present application are described in detail above, and the content of the specification should not be understood as limiting the scope of protection of the present application.

Claims

1. A display device, characterized in that: The display panel includes a multi-stage cascaded driving circuit, wherein the driving circuit includes a gate driving signal subcircuit, an initialization signal subcircuit, and a reference signal subcircuit; The gate drive signal subcircuit, the initialization signal subcircuit, and the reference signal subcircuit each include a plurality of oxide semiconductor transistors, the bottom gates of at least a portion of the oxide semiconductor transistors in the gate drive signal subcircuit are electrically connected to a potential control signal input terminal, the bottom gates of at least a portion of the oxide semiconductor transistors in the initialization signal subcircuit are electrically connected to the potential control signal input terminal, and the bottom gates of at least a portion of the oxide semiconductor transistors in the reference signal subcircuit are electrically connected to the potential control signal input terminal; The bottom gates of at least three oxide semiconductor transistors in the gate drive signal subcircuit are electrically connected to the potential control signal input terminal; The gate drive signal sub-circuit includes: a first transistor, wherein a top gate of the first transistor is electrically connected to the subsequent stage initialization signal input terminal, a drain of the first transistor is electrically connected to the first node, a source of the first transistor is electrically connected to the first low-level power signal input terminal, and a bottom gate of the first transistor is electrically connected to the potential control signal input terminal; a second transistor, wherein a top gate of the second transistor is electrically connected to the start signal input terminal, a drain of the second transistor is electrically connected to the first node, a source of the second transistor is electrically connected to the first low-level power signal input terminal, and a bottom gate of the second transistor is electrically connected to the potential control signal input terminal; and a third transistor, wherein the source of the third transistor is electrically connected to the first low-level power supply signal input terminal, the drain of the third transistor is electrically connected to the first node, the top gate of the third transistor is electrically connected to the second node, and the bottom gate of the third transistor is electrically connected to the potential control signal input terminal.

2. The display device according to claim 1, wherein The gate drive signal sub-circuit further includes: a fourth transistor, wherein a top gate of the fourth transistor is electrically connected to the previous stage initialization signal input terminal, a source of the fourth transistor is electrically connected to the high-level power signal input terminal, and a drain of the fourth transistor is electrically connected to the first node; a fifth transistor, wherein a source of the fifth transistor is electrically connected to the clock signal input terminal, a top gate of the fifth transistor is electrically connected to the first node, and a drain of the fifth transistor is electrically connected to the gate drive signal output terminal; a sixth transistor, wherein a top gate of the sixth transistor is electrically connected to the second node, a source of the sixth transistor is electrically connected to the first low-level power signal input terminal, and a drain of the sixth transistor is electrically connected to the gate drive signal output terminal; a seventh transistor, wherein a top gate and a source of the seventh transistor are both electrically connected to the high-level power signal input terminal; an eighth transistor, wherein a top gate of the eighth transistor is electrically connected to the high-level power signal input terminal, a source of the eighth transistor is electrically connected to the drain of the seventh transistor, and a drain of the eighth transistor is electrically connected to the second node; a ninth transistor, wherein a top gate of the ninth transistor is electrically connected to the first node, a drain of the ninth transistor is electrically connected to the second node, and a source of the ninth transistor is electrically connected to the first low-level power signal input terminal; a tenth transistor, a top gate of the tenth transistor being electrically connected to the previous-stage initialization signal input terminal, a drain of the tenth transistor being electrically connected to the second node, and a source of the tenth transistor being electrically connected to the first low-level power signal input terminal; and A first capacitor, wherein a first plate of the first capacitor is electrically connected to the first node, and a second plate of the first capacitor is electrically connected to the gate drive signal output terminal.

3. The display device according to claim 1, wherein The bottom gates of at least three oxide semiconductor transistors in the initialization signal sub-circuit are electrically connected to the potential control signal input terminal.

4. The display device according to claim 1 or 3, characterized in that The initialization signal sub-circuit includes: an eleventh transistor, wherein a top gate of the eleventh transistor is electrically connected to the subsequent stage initialization signal input terminal, a drain of the eleventh transistor is electrically connected to the third node, a source of the eleventh transistor is electrically connected to the first low-level power signal input terminal, and a bottom gate of the eleventh transistor is electrically connected to the potential control signal input terminal; a twelfth transistor, wherein a top gate of the twelfth transistor is electrically connected to the start signal input terminal, a drain of the twelfth transistor is electrically connected to the third node, a source of the twelfth transistor is electrically connected to the first low-level power signal input terminal, and a bottom gate of the twelfth transistor is electrically connected to the potential control signal input terminal; and a thirteenth transistor, wherein the source of the thirteenth transistor is electrically connected to the first low-level power supply signal input terminal, the top gate of the thirteenth transistor is electrically connected to the fourth node, the drain of the thirteenth transistor is electrically connected to the third node, and the bottom gate of the thirteenth transistor is electrically connected to the potential control signal input terminal.

5. The display device according to claim 4, wherein: The initialization signal sub-circuit further includes: a fourteenth transistor, wherein a top gate of the fourteenth transistor is electrically connected to the previous stage initialization signal input terminal, a source of the fourteenth transistor is electrically connected to the high-level power signal input terminal, and a drain of the fourteenth transistor is electrically connected to the third node; a fifteenth transistor, wherein a source of the fifteenth transistor is electrically connected to the clock signal input terminal, a top gate of the fifteenth transistor is electrically connected to the third node, and a drain of the fifteenth transistor is electrically connected to the initialization signal output terminal; a sixteenth transistor, wherein a top gate of the sixteenth transistor is electrically connected to the fourth node, a source of the sixteenth transistor is electrically connected to the first low-level power signal input terminal, and a drain of the sixteenth transistor is electrically connected to the initialization signal output terminal; a seventeenth transistor, wherein a top gate and a source of the seventeenth transistor are both electrically connected to the high-level power signal input terminal; an eighteenth transistor, wherein a top gate of the eighteenth transistor is electrically connected to the high-level power signal input terminal, a source of the eighteenth transistor is electrically connected to the drain of the seventeenth transistor, and a drain of the eighteenth transistor is electrically connected to the fourth node; a nineteenth transistor, wherein a top gate of the nineteenth transistor is electrically connected to the third node, a drain of the nineteenth transistor is electrically connected to the fourth node, and a source of the nineteenth transistor is electrically connected to the first low-level power signal input terminal; a twentieth transistor, wherein a top gate of the twentieth transistor is electrically connected to the previous stage initialization signal input terminal, a drain of the twentieth transistor is electrically connected to the fourth node, and a source of the twentieth transistor is electrically connected to the first low-level power signal input terminal; and A second capacitor, wherein a first plate of the second capacitor is electrically connected to the third node, and a second plate of the second capacitor is electrically connected to the initialization signal output terminal.

6. The display device according to claim 1, wherein The bottom gates of at least four oxide semiconductor transistors in the reference signal sub-circuit are electrically connected to the potential control signal input terminal.

7. The display device according to claim 1 or 6, characterized in that: The reference signal subcircuit comprises: a twenty-first transistor, wherein a top gate of the twenty-first transistor is electrically connected to the gate drive signal output terminal of the current stage, a source of the twenty-first transistor is electrically connected to the first low-level power supply signal input terminal, a drain of the twenty-first transistor is electrically connected to the fifth node, and a bottom gate of the twenty-first transistor is electrically connected to the potential control signal input terminal; a twenty-second transistor, wherein a top gate of the twenty-second transistor is electrically connected to the current-stage gate drive signal output terminal, a drain of the twenty-second transistor is electrically connected to the seventh node, a source of the twenty-second transistor is electrically connected to the current-stage gate drive signal output terminal, and a bottom gate of the twenty-second transistor is electrically connected to the potential control signal input terminal; a twenty-third transistor, wherein a top gate of the twenty-third transistor is electrically connected to the current-stage initialization signal input terminal, a drain of the twenty-third transistor is electrically connected to the seventh node, a source of the twenty-third transistor is electrically connected to the first low-level power supply signal input terminal, and a bottom gate of the twenty-third transistor is electrically connected to the potential control signal input terminal; and a twenty-fourth transistor, the source of the twenty-fourth transistor is electrically connected to the first low-level power supply signal input terminal, the drain of the twenty-fourth transistor is electrically connected to the fifth node, the top gate of the twenty-fourth transistor is electrically connected to the sixth node, and the bottom gate of the twenty-fourth transistor is electrically connected to the potential control signal input terminal.

8. The display device according to claim 7, wherein: The reference signal subcircuit further includes: a twenty-fifth transistor, wherein a top gate of the twenty-fifth transistor is electrically connected to the current-stage initialization signal input terminal, a source of the twenty-fifth transistor is electrically connected to the high-level power signal input terminal, and a drain of the twenty-fifth transistor is electrically connected to the fifth node; a twenty-sixth transistor, wherein a source of the twenty-sixth transistor is electrically connected to the second high-level power signal input terminal, a top gate of the twenty-sixth transistor is electrically connected to the fifth node, and a drain of the twenty-sixth transistor is electrically connected to the reference signal output terminal; a twenty-seventh transistor, wherein a top gate of the twenty-seventh transistor is electrically connected to the sixth node, a source of the twenty-seventh transistor is electrically connected to the second low-level power signal input terminal, and a drain of the twenty-seventh transistor is electrically connected to the reference signal output terminal; a twenty-eighth transistor, wherein a drain of the twenty-eighth transistor is electrically connected to the sixth node, a source of the twenty-eighth transistor is electrically connected to the first low-level power signal input terminal, and a top gate of the twenty-eighth transistor is electrically connected to the fifth node; a twenty-ninth transistor, wherein a source of the twenty-ninth transistor is electrically connected to the high-level power signal input terminal, a drain of the twenty-ninth transistor is electrically connected to the sixth node, and a top gate of the twenty-ninth transistor is electrically connected to the seventh node; a 30th transistor, wherein a top gate of the 30th transistor is electrically connected to the current-stage initialization signal input terminal, a source of the 30th transistor is electrically connected to the first low-level power signal input terminal, and a drain of the 30th transistor is electrically connected to the sixth node; a third capacitor, wherein a first plate of the third capacitor is electrically connected to the fifth node, and a second plate of the third capacitor is electrically connected to the reference signal output terminal; and A fourth capacitor, wherein a first plate of the fourth capacitor is electrically connected to the sixth node, and a second plate of the fourth capacitor is electrically connected to the seventh node.

9. The display device according to claim 1, wherein The voltage value of the signal inputted by the potential control signal input terminal is not higher than -5V.

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