Storage value modification method and nonvolatile memory chip

Abstract

The storage value modification method comprises the steps that a control module obtains a target storage value corresponding to a target storage unit and calculates a target current value according to the target storage value; reading a first current value flowing through the target storage unit; calculating a first difference value between the target current value and the first current value, and calculating an electrical parameter according to the first difference value; the electrical parameters comprise an erasing voltage value (or an erasing current value) and a first duration (or a second duration); and the control module generates a corresponding erasing voltage (or erasing current) according to the erasing voltage value (or erasing current value), and applies the erasing voltage (or erasing current) to the target storage unit according to the first duration (or second duration). Therefore, when the storage value in the target storage unit is just started to be modified, the modification amount of the storage value is relatively large, and the modification amount of the storage value becomes smaller and smaller along with the more and more modification times of the storage value, so that the erasing efficiency of the nonvolatile storage unit can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and in particular to a storage value modification method and a non-volatile memory chip. Background Art

[0002] Memories can generally be classified into volatile memories and non-volatile memories. Volatile memories (such as DRAM, SRAM, etc.) will lose stored data when power is lost. On the contrary, non-volatile memories (such as FLASH memory, EEPROM, EPROM, RRAM memory, PCM memory, etc.) can retain stored data when power is lost.

[0003] The non-volatile memory includes a memory cell array, which is composed of a plurality of memory cells connected together. The memory cell can be divided into a single-level cell (SLC) and a multi-level cell (MLC). A single-level cell can only store 1 bit of data, while a multi-level cell can store multiple bits of data. For example, if a multi-valued memory cell can store 2 bits of data, the corresponding storage value range is 0-3, if a multi-valued memory cell can store 3 bits of data, the corresponding storage value range is 0-7, and if a multi-valued memory cell can store 8 bits of data, the corresponding storage value range is 0-255. Since the current value flowing through the multi-valued memory cell is used to characterize the storage value in the multi-valued memory cell, by applying an erase voltage or erase current for a certain period of time to the multi-valued memory cell, the magnitude of the current flowing through the multi-valued memory cell can be changed, that is, the storage value in the multi-valued memory cell can be changed. Specifically, the storage value can be increased or decreased.

[0004] In the related art, the incremental step pulse program (ISPP) method is usually used to modify the storage value in the multi-valued storage cell. However, the existing ISSP method requires a large number of modifications when modifying the storage value in the multi-valued storage cell, and there is a technical problem of low erasing efficiency.

[0005] Therefore, how to improve the erasing and writing efficiency of non-volatile memory cells is a technical problem that urgently needs to be solved. Summary of the invention

[0006] The present application provides a storage value modification method and a non-volatile memory chip, which can generate electrical parameters according to the difference between the target current value and the current current value, and modify the storage value in the target storage unit according to the electrical parameters. In this way, when the difference between the target current value and the current current value is large, the modification amount of the storage value is large, and when the difference between the target current value and the current current value becomes smaller and smaller, the modification amount of the storage value also becomes smaller and smaller. Compared with the technical solution in the prior art that can only change the storage value in the storage unit by a constant small value each time, the present application can improve the erasing efficiency of the non-volatile storage unit.

[0007] In a first aspect, the present application provides a storage value modification method, which is applied to a non-volatile memory chip, wherein the non-volatile memory chip includes a storage cell array and a control module; the storage cell array includes at least one storage cell, and the storage cell is a multi-value storage cell; the control module is electrically connected to the storage cell array; the method includes: the control module obtains a target storage value corresponding to the target storage cell, and calculates a target current value according to the target storage value; reads a first current value flowing through the target storage cell; calculates a first difference between the target current value and the first current value, and calculates a first electrical parameter according to the first difference; the first electrical parameter includes a first erase voltage value and a first duration, or a first erase current value and a second duration; the control module generates a corresponding first erase voltage according to the first erase voltage value, and applies the first erase voltage to the target memory cell according to the first duration; the current change induced by the first erase voltage in the target memory cell is positively correlated with the absolute value of the first difference; or, the control module generates a corresponding first erase current according to the first erase current value, and applies the first erase current to the target memory cell according to the second duration; the current change induced by the first erase current in the target memory cell is positively correlated with the absolute value of the first difference.

[0008] In this way, when the storage value in the target storage unit is first modified, the modification amount of the storage value is large. As the number of storage value modifications increases, the modification amount of the storage value also becomes smaller and smaller. Therefore, the modification accuracy and modification speed of the storage value can be taken into account. Compared with the technical solution in the prior art that can only change the storage value in the storage unit by a constant small value each time, the present application can reduce the number of modifications to the storage value in the storage unit, that is, it can improve the erasing efficiency of the non-volatile storage unit.

[0009] In a possible implementation, the storage value modification method also includes: the control module reads the second current value flowing through the target storage unit, calculates the second difference between the target current value and the second current value, and calculates the second electrical parameter based on the second difference; the second electrical parameter includes the value of the second erase voltage and the third duration, or the second erase current value and the fourth duration; the control module calculates the actual difference between the second current value and the first current value, and determines whether the actual difference is within the first interval of the expected current change; if the actual difference is not within the first interval of the expected current change, the control module adjusts the second electrical parameter; the control module applies the corresponding erase voltage or erase current to the target storage unit based on the adjusted second electrical parameter.

[0010] In this way, the present application can determine whether the actual difference is within the first interval of the expected change in current. If not, it indicates that the change in current value caused by the erase voltage or erase current applied last time (the Nth time) is too large or too small. By adaptively adjusting the second electrical parameter and applying the corresponding erase voltage or erase current to the target storage unit according to the adjusted second electrical parameter, the problem of the current value change caused by the erase voltage or erase current applied this time (the N+1th time) being too small or too large can be avoided.

[0011] In a possible implementation, the storage value modification method further includes: if the actual difference is within a first interval of expected current change, the control module applies a corresponding erase voltage or erase current to the target storage unit according to the second electrical parameter.

[0012] In this way, the present application can determine whether the actual difference is within the first interval of the expected current change. If so, it indicates that the current value change caused by the erase voltage or erase current applied last time (Nth time) is appropriate. Therefore, there is no need to adjust the second electrical parameter. The control module generates the corresponding N+1th erase voltage or erase current according to the second electrical parameter, and applies it to the target storage unit, so that the erase voltage or erase current applied this time (N+1th time) can produce a suitable current value change.

[0013] In a possible implementation, the control module calculates the actual difference between the second current value and the first current value, and determines whether the actual difference is within the first interval of the expected current change, specifically including: the control module determines the first interval of the current difference to which the absolute value of the second difference belongs; the first interval of the current difference is one of multiple current difference intervals, and the multiple current difference intervals jointly cover the range from zero to the maximum current value in the target storage unit; the control module determines the first interval of the expected current change corresponding to the first interval of the current difference; the first interval of the expected current change is one of multiple intervals of expected current change, and multiple intervals of expected current change have a one-to-one correspondence with multiple current difference intervals respectively; the control module calculates the actual difference between the second current value and the first current value, and determines whether the actual difference is within the first interval of the expected current change. In this way, the control module can accurately determine whether the actual difference between the second current value and the first current value is too large or too small.

[0014] The memory cell array is a flash memory cell array, an erasable programmable read-only memory cell array, an electrically erasable programmable read-only memory cell array, a variable resistance memory cell array or a phase change memory cell array. The present application can be applied to a variety of non-volatile memory chips.

[0015] In a possible implementation, the memory cell array is a variable resistance memory cell array; the first electrical parameter includes a current limit value, a first erase voltage value, and a first duration; the control module generates a corresponding first erase voltage according to the first erase voltage value, and applies the first erase voltage to the target memory cell according to the first duration, specifically including: the control module generates a corresponding first erase voltage according to the first erase voltage value, and applies the first erase voltage to the target memory cell according to the first duration, while limiting the current flowing through the target memory cell to below the current limit value. In this way, the present application can increase and modify the storage value in the variable resistance memory cell.

[0016] In a possible implementation, calculating the first difference between the target current value and the first current value, and calculating the first electrical parameter according to the first difference, specifically includes: calculating the first difference between the target current value and the first current value; determining whether the absolute value of the first difference is greater than a preset current value; if greater than the preset current value, calculating the first electrical parameter according to the first difference. In this way, the present application can determine whether the current stored value needs to be modified by comparing the absolute value of the first difference with the preset current value.

[0017] In a possible implementation, calculating the first difference between the target current value and the first current value, and calculating the first electrical parameter according to the first difference, specifically includes: calculating the first difference between the target current value and the first current value; judging whether the number of erasures and writes to the target storage unit is less than a preset number; if less than the preset number, calculating the first electrical parameter according to the first difference. In this way, the present application can avoid falling into an invalid modification process of the stored value and improve the modification efficiency of the stored value.

[0018] In a second aspect, the present application provides a non-volatile memory chip, comprising: a control module for executing the method described in the first aspect or any possible implementation of the first aspect; a storage cell array for storing data; the storage cell array comprises at least one storage cell, and the storage cell is a multi-value storage cell.

[0019] In a possible implementation, the memory cell array is a flash memory cell array, an erasable programmable read-only memory cell array, a charged erasable programmable read-only memory cell array, a variable resistance memory cell array, or a phase change memory cell array.

[0020] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of the architecture of a non-volatile memory chip provided in an embodiment of the present application;

[0022] Figure 2 is a structural diagram of a Flash storage unit in an embodiment of the present application;

[0023] Figure 3 is a structural schematic diagram of a Flash storage cell array in an embodiment of the present application;

[0024] Figure 4 is a detailed schematic diagram of the architecture of a non-volatile memory chip provided in an embodiment of the present application;

[0025] Figure 5 is a schematic diagram of the structure of a row decoder in an embodiment of the present application;

[0026] Figure 6 is a schematic diagram of the structure of a switching decoder in an embodiment of the present application;

[0027] Figure 7 is a structural schematic diagram of an RRAM memory cell array or a PCM memory cell array in an embodiment of the present application;

[0028] Figure 8It is a flowchart of a method for modifying a storage value of a non-volatile memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The term "and / or" in this article is a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The symbol " / " in this article indicates that the associated objects are in an or relationship, for example, A / B means A or B.

[0030] The terms "first" and "second" in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of the objects. For example, a first response message and a second response message are used to distinguish different response messages rather than to describe a specific order of the response messages.

[0031] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0032] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more than two. For example, multiple processing units refer to two or more processing units, etc.; multiple elements refer to two or more elements, etc.

[0033] The current storage cells can be divided into single-value storage cells and multi-value storage cells. In the related art, the ISPP method can be used to modify the storage value in the multi-value storage cell. However, when the ISSP method is used to modify the storage value in the multi-value storage cell, a large number of modifications are required, and there is a technical problem of low erase efficiency. It should be noted that erase is the collective name for erase and program. The erase operation refers to the operation of increasing the storage value in the storage cell, and the program operation refers to the operation of decreasing the storage value in the storage cell, and the program operation is also called a write operation.

[0034] For example, a Flash multi-valued storage cell can store 8-bit data, and the current storage value in the multi-valued storage cell is 200. When the storage value in the multi-valued storage cell needs to be changed to 50, a programming voltage needs to be applied to perform a programming operation on the multi-valued storage cell. Specifically, when the current ISPP method is adopted, by applying the first programming voltage to the multi-valued storage cell, the storage value can be changed from 200 to 199, and by applying the second programming voltage, the storage value can be changed from 199 to 198, and so on. It is necessary to perform 150 programming operations to change the storage value to 50. The number of programming operations is large, which shows that the ISSP method has a low efficiency in modifying the storage value. Similarly, if the current storage value of the target storage cell is 50, 150 erase operations are required to modify the storage value to the target storage value 200. It can be seen that the erasing efficiency of the existing ISSP method is low.

[0035] In view of this, an embodiment of the present application provides a storage value modification scheme. The scheme can calculate the erase voltage (or erase current) and its duration according to the difference between the target current value and the current value of the target storage unit. When performing the calculation, by making the current change caused by the erase voltage (or erase current) in the target storage unit positively correlated with the absolute value of the aforementioned difference, the modification amount of the storage value can be large when the storage value in the target storage unit is just started to be modified. As the number of storage value modifications increases, the modification amount of the storage value also becomes smaller and smaller. Therefore, compared with the technical scheme in the prior art that can only change the storage value in the storage unit by a constant small value (usually 1) each time, this scheme can reduce the number of modifications to the storage value and improve the erasing efficiency of the non-volatile storage unit.

[0036] Next, the storage value modification solution provided in the embodiment of the present application is introduced.

[0037] Figure 1 FIG. 1 shows a schematic diagram of the architecture of a non-volatile memory chip provided by an embodiment of the present application. Figure 1 As shown, the nonvolatile memory chip 1 may include a control module 11 and a memory cell array 12, wherein the control module 11 is electrically connected to the memory cell array 12. The memory cell array 12 may include at least one multi-value memory cell, each of which may store multi-bit data.

[0038] The control module 11 may be provided with a communication interface, and the control module 11 may receive data to be stored from an external module (such as a central processing unit CPU, an arithmetic logic unit ALU or other modules connected to the bus) via the communication interface, and then determine the target storage value corresponding to the target storage cell in the storage cell array 12 according to the data to be stored, and calculate the target current value corresponding to the target storage value. It can be understood that the target storage cell can be any storage cell in the storage cell array.

[0039] Next, in the current reading cycle, the control module 11 can read the current current value flowing through the target storage unit after power is supplied to the target storage unit, and calculate the difference between the target current value and the current current value (referred to as the first difference). Furthermore, in the erase cycle, the control module 11 can calculate the electrical parameters according to the aforementioned first difference. The control module 11 can generate a corresponding first erase voltage or first erase current according to the electrical parameters, and apply a first erase voltage with a duration of the first duration to the target storage unit, or the control module 11 can generate a first erase current with a duration of the second duration according to the electrical parameters, and apply a first erase current with a duration of the second duration to the target storage unit, so as to change the magnitude of the current flowing through the target storage unit, that is, to change the storage value in the target storage unit. The erase voltage is the collective name of the erase voltage and the programming voltage (also called the write voltage). By applying the erase voltage, the storage value can be increased, and by applying the programming voltage, the storage value can be reduced.

[0040] Since the current change caused by the first erase voltage or the first erase current applied to the target memory cell is positively correlated with the absolute value of the first difference, the larger the absolute value of the first difference is, the larger the current change caused by the first erase voltage or the first erase current in the target memory cell is.

[0041] This means that when the storage value in the target storage unit is first modified, due to the large absolute value of the first difference, the first erase voltage or the first erase current can make the change in the current value flowing through the target storage unit larger, that is, the change in the storage value in the target storage unit is larger, thereby accelerating the change speed of the storage value in the target storage unit. Then, as the number of times the storage value in the target storage unit is modified increases, the absolute value of the first difference becomes smaller and smaller. Correspondingly, the first erase voltage or the first erase current can make the change in the current value flowing through the target storage unit smaller and smaller, that is, the change in the storage value in the target storage unit is also smaller and smaller. In this way, the problem of poor modification accuracy caused by the large change in the storage value when the first difference is small (that is, when the current storage value is close to the target storage value) can be prevented, thereby ensuring the modification accuracy of the storage value in the target storage unit.

[0042] In short, when the storage value in the target storage unit is first modified, the modification amount of the storage value is large. As the number of modifications to the storage value increases, the modification amount of the storage value also becomes smaller and smaller. Therefore, the modification accuracy and modification speed of the storage value can be taken into account. Compared with the technical solution in the prior art that can only change the storage value in the storage unit by a constant small value each time, the embodiment of the present application can reduce the number of modifications to the storage value in the storage unit, that is, it can improve the erasing efficiency of the non-volatile storage unit.

[0043] There are many types of non-volatile memory. Specifically, in the embodiment of the present application, the memory cell array 12 can be a Flash memory cell array, an erasable programmable read only memory (EPROM) memory cell array, an electrically erasable programmable read only memory (EEPROM) memory cell array, a resistive random access memory (RRAM) memory cell array, or a phase change memory (PCM) memory cell array. When the types of memory cell arrays are different, the specific implementation methods of the embodiment of the present application also have certain differences. The following is a detailed description of the case where the memory cell array 12 is a Flash memory cell array.

[0044] First, the structure of the Flash storage cell array and the structure of the control module 11 are introduced in detail.

[0045] The memory cell array 12 can be either a NAND Flash memory cell array or a NOR Flash memory cell array, the main difference between which is the connection method of the memory cell. The Flash memory cell is a floating gate field effect transistor, which is a special metal oxide semiconductor field effect transistor (metal-oxide-semiconductor field-effect transistor, MOSFET). The floating gate field effect transistor is formed by adding a floating gate to an ordinary MOSFET. The floating gate field effect transistor can be formed by adding a floating gate based on an N-channel MOSFET, or by adding a floating gate based on a P-channel MOSFET.

[0046] Take the floating gate field effect transistor formed by adding a floating gate to an N-channel MOSFET as an example. Figure 2As shown in the figure, the floating gate field effect transistor has two gates formed by polysilicon, one of which is electrically connected to the outside and is called the control gate (CG); the other gate has no external leads and is composed of nitride sandwiched between two layers of silicon dioxide material. It is floating, so it is called a floating gate (FG). Since the floating gate is electrically insulated and independent, the electrons entering the floating gate will be trapped in the floating gate. Under normal conditions, the electrons will not escape for many years. This is also the principle that the data of the Flash memory will not be lost after power failure.

[0047] The basic structure and storage principle of the floating gate field effect transistor formed by adding a floating gate to a P-channel MOSFET are similar to those of the above-mentioned N-channel floating gate field effect transistor, and will not be described in detail here.

[0048] The current value flowing through the N channel of the floating gate field effect tube is used to characterize the storage value. The more electrons stored in the floating gate, the higher the threshold voltage Vth of the floating gate field effect tube, and the smaller the current value flowing through the N channel. The basic principle of changing the storage value in the floating gate field effect tube is that by applying an erase voltage to the floating gate field effect tube, the amount of charge stored in the floating gate (specifically the amount of electrons) can be changed, thereby changing the threshold voltage of the floating gate field effect tube. Furthermore, the magnitude of the current in the N channel of the floating gate field effect tube can be changed, that is, the storage value in the floating gate field effect tube can be changed. It can be understood that the threshold voltage of the floating gate field effect tube refers to the gate-source bias voltage value required to just form a conductive channel.

[0049] Specifically, by applying an erase voltage to the control gate, source, and drain of the floating gate field effect transistor, electrons can be "sucked out" from the floating gate into the N channel, thereby reducing the threshold voltage of the floating gate field effect transistor. By applying a programming voltage to the control gate, source, and drain of the floating gate field effect transistor, electrons can be injected from the N channel into the floating gate, thereby increasing the threshold voltage of the floating gate field effect transistor.

[0050] For example, Figure 3 The figure shows a Nor Flash memory cell array with 8 rows and 8 columns. Each memory cell can store 8 bits of data, that is, the range of the stored value in each memory cell is 0-255. The type of memory cell is an N-channel floating gate field effect transistor. It should be noted that in actual situations, the number of memory cells in the memory cell array is usually larger than Figure 3 The number shown in the figure is much larger, but the implementation principle of modifying the storage value in the target storage unit is the same.

[0051] The row select line can be Figure 3The word lines WL1-WL8 of the Flash memory cell array in the memory cell array can be electrically connected to the control gate of the memory cell. The column selection lines can be the bit lines BL1-BL8 of the Flash memory cell array, the bit lines can be electrically connected to the drain of the memory cell, and the source lines SL1-SL8 in the memory cell array 12 are electrically connected to the source of the memory cell.

[0052] like Figure 4 As shown, the control module 11 may include a processor 111, a voltage generator 112, a row decoder 113, a row decoder 114, a switching decoder 115, a column decoder 116 and a current reading module 117, wherein the voltage generator 112 here is used to generate an erase voltage under the control of the processor 111, all decoders play a multi-way selection role, and the current reading module 117 is used to read the current value flowing through the target storage unit.

[0053] The row decoder 113 , the row decoder 114 , and the column decoder 116 are all 3-8 decoders, which are respectively provided with a strobe port, a voltage input port, and a voltage output port.

[0054] like Figure 5 As shown, the row decoder 113 may include three selection ports, namely selection ports A2, A1 and A0, which are electrically connected to the processor 111 respectively. The voltage input port Vin1 may be electrically connected to the first voltage output terminal of the voltage generator 112. The voltage output port of the row decoder 113 may include eight output ports, namely B7-B0, which are electrically connected to the eight row selection lines WL8-WL1 of the memory cell array 12 respectively.

[0055] Similarly, the row decoder 114 has the same structure as the row decoder 113 , the voltage input port of the row decoder 114 is electrically connected to the second voltage output terminal of the voltage generator 112 , and the 8 output ports of the row decoder 114 are electrically connected to the 8 source lines SL8 - SL1 of the memory cell array 12 .

[0056] The column decoder 116 has the same structure as the row decoder 113 . The 8 output ports of the column decoder 116 are electrically connected to the 8 column selection lines BL8 - BL1 of the memory cell array 12 , respectively. The voltage input port of the column decoder 116 is connected to the first port P1 of the switching decoder 115 .

[0057] like Figure 6As shown, the switching decoder 115 may be provided with a strobe port A4, a first port P1, a second port P2 and a third port P3, and the strobe port A4 is electrically connected to the processor 111. The strobe signal received by the strobe port A4 determines whether the first port P1 is connected to the second port P2 or the third port P3. The second port P2 is electrically connected to the current reading module 117, and the third port P3 is electrically connected to the third voltage output terminal of the voltage generator 112.

[0058] In one example, during the current reading cycle, the processor 111 may send a low level signal (selection signal 0) to the select port A4 of the switching decoder 115, so that the first port P1 is connected to the second port P2, thereby facilitating the current reading module 117 to read the current value flowing through the target memory cell. During the erase cycle, the processor 111 sends a high level signal (selection signal 1) to the select port A4, and the first port P1 is connected to the third port P3, so that the voltage generated by the voltage generator 112 supplies power to the column selection line of the memory cell.

[0059] Based on the above description, with respect to the target storage cell in the Nor Flash storage cell array, the specific process of increasing the storage value in the target storage cell is described in detail below.

[0060] The processor 111 may be provided with a communication interface, and the processor 111 may receive data to be stored from an external module via the communication interface, determine a target storage value to be stored in a target storage cell in the storage cell array 12 according to the data to be stored, and calculate a target current value corresponding to the target storage value.

[0061] Exemplarily, the target storage cell is the storage cell in the 4th row and the 5th column in the storage cell array 12, that is, Figure 3 The target storage unit is within the circle. The target storage unit can store 8-bit data, and the corresponding storage value range is 0-255, wherein the current value corresponding to the maximum storage value 255 is 10uA, and the target storage value is 240, then the processor 111 can calculate the target current value corresponding to the target storage value as 10uA÷256×240=9.375uA.

[0062] Next, the processor 111 can calculate the corresponding voltage control parameter according to the size of the power supply voltage required for the current reading cycle, and send it to the voltage generator 112. The voltage generator 112 can generate the corresponding current reading cycle power supply voltage according to the voltage control parameter. The processor 111 can also send a selection signal 011 to the selection ports A2, A1 and A0 of the row decoder 113, send the same selection signal to the selection port of the row decoder 114, send a selection signal 0 to the selection port of the switching decoder 115, and send a selection signal 100 to the selection ports A5, A4 and A3 of the column decoder 116, so that the power supply voltage can be applied to the control gate and source of the target memory cell through the row selection line WL4 and the source line SL4. For example, the power supply voltage of the control gate and the source is 2.5V. At the same time, the drain of the target memory cell is electrically connected to the current reading module 117 through the column selection line BL5, the column decoder 116 and the switching decoder 115.

[0063] Then, the current reading module 117 can sample the current flowing through the target unit and perform analog-to-digital conversion, so as to obtain the current current value, for example, the current current value is 1.563uA, and send the current current value to the processor 111. Exemplarily, the current reading module 117 can be composed of an operational amplifier and an analog-to-digital converter, the operational amplifier can convert the current signal into a voltage signal, and the analog-to-digital converter can sample and perform analog-to-digital conversion on the voltage signal, so as to obtain the current current value flowing through the target storage unit.

[0064] In the erase (programm erase, PE) cycle, after receiving the current current value flowing through the target storage unit, the processor 111 can calculate the difference between the target current value and the current current value, and calculate the erase voltage parameter and the duration parameter based on the difference. The processor 111 can send the erase voltage parameter and the duration parameter to the voltage generator 112, and the voltage generator 112 can generate an erase voltage of a corresponding duration (recorded as the first duration) based on the parameter. Specifically, the erase voltage refers to the voltage 0V generated at the first voltage output terminal of the voltage generator 112, the floating state generated at the second voltage output terminal of the voltage generator 112, and the voltage V1 (V1 is greater than 0) generated at the third voltage output terminal of the voltage generator 112.

[0065] The processor 111 can send a strobe signal 011 to the strobe ports A2, A1 and A0 of the row decoder 113, electrically connecting the control gate of the target memory cell to the first voltage output terminal of the voltage generator 112, so that its control gate is grounded (0V). The processor 111 can send the same strobe signal to the strobe port of the row decoder 114, electrically connecting the source of the target memory cell to the second voltage output terminal of the voltage generator 112, so that the source of the target memory cell is suspended. The processor 111 can also send a strobe signal 1 to the strobe port of the switching decoder 115, and send a strobe signal 100 to the strobe ports A5, A4 and A3 of the column decoder 116, electrically connecting the drain of the target memory cell to the third voltage output terminal of the voltage generator 112, so that its drain is connected to the voltage V1. In this way, the electrons in the floating gate will be "sucked out" into the N channel, and the threshold voltage of the floating gate field effect transistor will become lower accordingly. Therefore, when the current is read next time, the current in the N channel of the floating gate field effect transistor will increase accordingly.

[0066] When the first duration is a constant value, the greater the value of the voltage V1, the greater the change in the stored value. Also, when the value of the voltage V1 is a constant value, the longer the first duration, the greater the change in the stored value. Therefore, the value of the voltage V1 and the first duration jointly determine the change in the stored value in the floating gate field effect transistor (here, the change is the increase).

[0067] In one implementation, the first duration can be set to a fixed value, and when the processor 111 calculates the value of the voltage V1, the value of the voltage V1 can be positively correlated with the absolute value of the first difference. This means that when the absolute value of the first difference is large, the value of the voltage V1 is also large, and correspondingly, the change in the storage value in the floating gate field effect transistor is also large. More specifically, the value of V1 can be calculated using the following formula: V1 = V_(D,era,min)+c*|I_n-I_target|, where I_n is the current current value, I_target is the target current value, V_(D,era,min) and c are both constants greater than 0, so that the value of V1 can be positively correlated with the absolute value of the first difference.

[0068] In another implementation, the voltage V1 can be set to a fixed value in advance, and when calculating the first duration, the first duration can be made positively correlated with the absolute value of the first difference. In this way, the larger the absolute value of the first difference, the longer the first duration, so that the more electrons are "sucked out" from the floating gate, and the greater the change in the storage value in the target storage unit. More specifically, the first duration can be positively proportional to the absolute value of the first difference.

[0069] In another implementation, the value of the voltage V1 and the first duration can be calculated simultaneously based on the absolute value of the first difference to adjust the size of the change in the storage value in the target storage unit. The embodiment of the present application does not limit the specific calculation method, as long as the calculation method can make the current change induced in the target storage unit positively correlated with the absolute value of the first difference.

[0070] The above describes a specific implementation method for increasing the storage value in the N-channel floating gate field effect transistor by using an erase voltage when the target storage value is greater than the current storage value. When the target storage value is less than the current storage value, it is necessary to use a programming voltage to decrease the storage value in the floating gate field effect transistor. The specific implementation method is different from the aforementioned method of increasing the storage value in the floating gate field effect transistor by using an erase voltage. The differences are described in detail below.

[0071] When the processor 111 determines that the difference between the target current value and the current current value (the first difference) is less than 0, a programming voltage parameter and a corresponding duration parameter can be generated according to the absolute value of the first difference, and the parameter can be sent to the voltage generator 112. The voltage generator 112 can generate a programming voltage of a corresponding duration (recorded as the first duration) according to the parameter.

[0072] Different from the aforementioned erase voltage, the programming voltage refers to the voltage V2 generated at the first voltage output terminal of the voltage generator 112, the voltage 0V generated at the second voltage output terminal of the voltage generator 112, and the voltage V3 (V3 is greater than 0 and less than V2) generated at the third voltage output terminal of the voltage generator 112.

[0073] The processor 111 uses the same method as above to perform gating control on the row decoder 113, the row decoder 114, the switching decoder 115 and the column decoder 116, so as to connect the control gate of the target memory cell to the voltage V2, the source to the ground (0V), and the drain to the voltage V3. In this way, a voltage difference is generated between the source and the drain of the target memory cell, thereby generating a large number of high-energy electrons in the N channel.

[0074] Due to the high electron density, some electrons can reach the silicon dioxide layer between the substrate and the floating gate (specifically Figure 2 Since the control gate of the target storage unit is connected to the voltage V2, and the voltage V2 is greater than the voltage V3, the high-energy electrons can pass through the tunneling layer to reach the floating gate, thereby increasing the electrons stored in the floating gate and increasing the threshold voltage of the floating gate field effect transistor. Therefore, the magnitude of the current in the N channel of the floating gate field effect transistor can be reduced, that is, the storage value in the floating gate field effect transistor can be reduced.

[0075] When the first duration is constant, the greater the values ​​of voltages V2 and V3, the greater the change in the stored value (here, the change is the decrease). Similarly, when the values ​​of the above voltages V2 and V3 are constant, the longer the first duration, the greater the change in the stored value. Therefore, the values ​​of voltages V2 and V3 and the first duration jointly determine the change in the stored value in the floating gate field effect transistor.

[0076] In one implementation, the first duration can be set to a fixed value, and when calculating the voltages V2 and V3, the values ​​of the voltages V2 and V1 can be positively correlated with the absolute value of the first difference. Therefore, when the absolute value of the first difference is large, the values ​​of the voltages V2 and V3 are also large, and accordingly, the change in the storage value in the floating gate field effect transistor is also large. As a specific implementation method, the first duration can be set as a constant in advance, and the values ​​of V2 and V3 can be calculated using the following formula: V2 = V_(G, pgm, min) + a*|I_n-I_target|, V3 = V_(D, pgm, min) + b*|I_n-I_target|, where I_n is the current current value, I_target is the target current value, V_(G, pgm, min), V_(D, pgm, min), a and b are all constants greater than 0, and V_(G, pgm, min) is greater than V_(D, pgm, min), and a is greater than b. In this way, the values ​​of V1 and V2 are positively correlated with the absolute value of the first difference.

[0077] In another implementation, the magnitudes of the voltages V2 and V3 may be set as constants in advance, and when calculating the first duration, the first duration may be made positively correlated with the absolute value of the first difference. In this way, the larger the absolute value of the first difference, the longer the first duration, so that the more electrons are injected into the floating gate, the greater the change in the storage value in the target storage unit. As a specific implementation, the first duration may be made positively proportional to the absolute value of the first difference.

[0078] In another implementation, the values ​​of voltages V2 and V3 and the first duration can be calculated simultaneously based on the absolute value of the first difference to adjust the size of the change in the storage value in the target storage unit. The embodiment of the present application does not limit the specific calculation method, as long as the calculation method can make the current change induced in the target storage unit positively correlated with the absolute value of the first difference.

[0079] The above describes in detail the scheme for modifying the storage value in the N-channel floating gate field effect transistor. When the memory cell array 12 is a P-channel floating gate field effect transistor array, an EEPROM memory cell array or an EPROM memory cell array, its implementation principle and implementation method are basically the same as the above scheme, and will not be described in detail here. However, when the memory cell array 12 is an RRAM memory cell array or a PCM memory cell array, when modifying the storage value in the memory cell, the specific method is different from the above scheme, and the following focuses on the detailed description of the differences.

[0080] The erase operation has different names in different types of memory cell arrays. For RRAM memory cells and PCM memory cells, the erase operation is called the set operation, and the programming operation is called the reset operation.

[0081] The RRAM memory cell array may include multiple RRAM memory cells interconnected by metal wires. RRAM is a new type of non-volatile memory device, also known as programmable resistive memory (Programmable Resistive Memory). The current value flowing through the RRAM memory cell represents the storage value in the memory cell. By applying a set voltage or a reset voltage to the RRAM memory cell, ions will move in the variable resistance material, changing the resistance value of the variable resistance material, and then changing the current value flowing through the memory cell during the current reading cycle (the current value can be read in the subsequent current reading cycle), that is, the storage value in the memory cell can be changed.

[0082] The following is an introduction to the basic structure of an RRAM memory cell. Each RRAM memory cell can be composed of the following parts: a bottom electrode (BE), a variable resistance material (VRM) layer, an insulating layer (Insulator) and a top electrode (TE). Among them, the bottom electrode serves as the bottom electrode of the memory cell, usually a thin-film metal electrode. The variable resistance material is usually an oxide, such as titanium oxide (TiO2), zirconium oxide (ZrO2) or silicon dioxide (SiO2). The insulating layer is used to isolate the top electrode and the variable resistance material, usually a layer of oxide or nitride. The top electrode serves as the top electrode of the memory cell, usually a thin-film metal electrode.

[0083] During the set operation of the RRAM memory cell, the upper electrode is connected to a high potential and the lower electrode is connected to a low potential, that is, the RRAM memory cell is forward biased, which can reduce the resistance of the memory cell, that is, increase the storage value of the memory cell; on the contrary, during the reset process of the RRAM memory cell, its upper electrode is connected to a low potential and the lower electrode is connected to a high potential, that is, the RRAM memory cell is reverse biased, which can increase the resistance of the memory cell, that is, reduce the storage value of the memory cell.

[0084] RRAM memory cell arrays are divided into two types. In the first type of RRAM memory cell array, each RRAM memory cell is connected in series with a gate MOSFET, and the gate MOSFET is used to control whether the RRAM memory cell is turned on, such as Figure 7 As shown. In this way, when a voltage is applied to a target memory cell, there is no other path that interferes with the target memory cell. In the second type of RRAM memory cell array, each RRAM memory cell is electrically connected to a diode or a selector, or the RRAM memory cell itself has a self-selection characteristic, which can also play the same gating role. Among them, the selector is a volatile memristor.

[0085] In the first type of RRAM memory cell array, each RRAM memory cell is connected in series with a gate MOSFET. In a more specific example, the lower electrode of an RRAM memory cell can be electrically connected to the drain of the gate MOSFET. In this way, Figure 7 WL1A-WL8A in is equivalent to Figure 3 WL1-WL8 in Figure 7 BL1A-BL8A in is equivalent to Figure 3 BL1-BL8 in Figure 7 SL1A-SL8A in is equivalent to Figure 3 The external connection relationship of the RRAM storage cell array can refer to the connection relationship between the Flash storage cell array and the outside, which will not be described in detail here.

[0086] In the embodiment of the present application, for the first type of RRAM memory cell array, the specific implementation method of increasing the storage value in the RRAM memory cell is as follows.

[0087] If the target memory cell is the memory cell in the 4th row and the 5th column, in the current reading cycle, the processor 111 can calculate the corresponding voltage control parameter according to the size of the power supply voltage required in the current reading cycle, and send it to the voltage generator 112. The voltage generator 112 can generate the corresponding current reading cycle power supply voltage according to the voltage control parameter. The processor 111 can also send a selection signal 011 to the selection ports A2, A1 and A0 of the row decoder 113, send the same selection signal to the selection port of the row decoder 114, send a selection signal 0 to the selection port of the switching decoder 115, and send a selection signal 100 to the selection ports A5, A4 and A3 of the column decoder 116, so that the power supply voltage can be applied to the upper electrode of the target memory cell through SL4A. At the same time, the lower electrode of the target memory cell is electrically connected to the current reading module 117 through the selection MOSFET in the on state, BL5A, the column decoder 116 and the switching decoder 115.

[0088] Then, the current reading module 117 can sample the current flowing through the target unit and perform analog-to-digital conversion to obtain a current current value, and send the current current value to the processor 111 .

[0089] After obtaining the first difference between the target current value and the current current value, the processor 111 can calculate the relevant parameters and send them to the voltage generator 112. Different from the above-mentioned embodiment, the voltage generator 112 here has a current limiting function. According to the relevant parameters, the voltage generator 112 can output a turn-on voltage Vs at the first voltage output terminal, output a voltage V4 (V4 is greater than 0) at the second voltage output terminal, and output a voltage of 0V at the third voltage output terminal, and turn on the current limiting function at the same time, so that the output current value does not exceed the current limiting value Ia, and Ia is less than the compliance current value Ic, which is different from the erase voltage applied in the above-mentioned embodiment. Among them, the compliance current value Ic is determined according to the characteristics of the RRAM storage unit itself.

[0090] The processor 111 can apply the voltage Vs to the gate of the gate MOSFET to turn it on by sending corresponding selection signals to the row decoder 113, the switching decoder 115, and the column decoder 116, so that the lower electrode of the target memory cell can be grounded (0V), and the voltage V4 of the first duration is applied to the upper electrode, while the magnitude of the set current flowing through the target memory cell is limited to less than Ia. In this way, the resistance value of the target memory cell can be reduced to increase the storage value in the target memory cell. The increase in the storage value is related to the magnitude of the voltage V4, the magnitude of the current limit Ia flowing through the target memory cell, and the first duration.

[0091] In one example, the first duration can be set to a constant value. When calculating the voltage V4 and the current limit value Ia, by making the voltage V4 within a preset range (0, V_SET], the current limit value Ia within a preset range (0, Ic], and at the same time making both of them positively correlated with the absolute value of the first difference, when the absolute value of the first difference is large, the modification amount of the storage value in the target storage unit is also large. Among them, V_SET is determined according to the characteristics of the RRAM storage unit itself.

[0092] In another example, the magnitude of the voltage V4 and the current limit value Ia can be set to fixed values. When calculating the first duration, the first duration is positively correlated with the absolute value of the first difference, so that when the absolute value of the first difference is large, the modification amount of the storage value in the target storage unit is also large. It can be understood that the first duration can be controlled by controlling the duration of the output voltage V4 of the voltage generator 112, or by controlling the duration of the first voltage output terminal outputting the conduction start voltage Vs. As a specific implementation method, the first duration can be adjusted by adjusting the number of voltage pulses.

[0093] In another embodiment, the voltage V4, the current limiting value Ia and the first duration can be calculated simultaneously according to the absolute value of the first difference, so as to ensure that when the absolute value of the first difference is large, the modification amount of the storage value is also large. The embodiment of the present application does not limit the specific calculation method, as long as the calculation method can make the current change induced in the target storage unit positively correlated with the absolute value of the first difference.

[0094] In the embodiment of the present application, for the first type of RRAM memory cell array, the specific implementation method of reducing the storage value in the RRAM memory cell is as follows.

[0095] After determining that the first difference is less than 0, the processor 111 can calculate relevant parameters based on the first difference and send them to the voltage generator 112. According to the relevant parameters, the voltage generator 112 can output a turn-on voltage Vs at the first voltage output terminal, output a voltage V5 (V5 is less than 0) at the second voltage output terminal, and output a voltage of 0V at the third voltage output terminal without turning on the current limiting function.

[0096] The processor 111 can apply the voltage Vs to the gate of the gate MOSFET to turn it on by sending corresponding selection signals to the row decoder 113, the switching decoder 115, and the column decoder 116, so that the lower electrode of the target memory cell can be grounded (0V) and the voltage V5 of the first duration can be applied to the upper electrode. In this way, the resistance value of the target memory cell can be increased to reduce the storage value in the target memory cell. The reduction amount of the storage value is related to the absolute value of the voltage V5 and the first duration.

[0097] In one example, the first duration can be set to a fixed value, and when calculating the voltage V5, by making the value of the voltage V5 within a preset range [V_RESET, 0), and its absolute value is positively correlated with the absolute value of the first difference, the modification amount of the storage value in the target storage unit is also large when the absolute value of the first difference is large. Among them, V_RESET is determined according to the characteristics of the RRAM storage unit itself.

[0098] In another example, the voltage V5 can be set to a constant value. When calculating the first duration, the first duration is positively correlated with the absolute value of the first difference. This means that when the absolute value of the first difference is larger, the modification amount to the storage value in the target storage unit is also larger.

[0099] In another embodiment, the value and duration of voltage V5 can be calculated simultaneously based on the absolute value of the first difference, so as to ensure that when the absolute value of the first difference is large, the modification amount of the storage value is also large. The embodiment of the present application does not limit the specific calculation method, as long as the calculation method can make the current change induced in the target storage unit positively correlated with the absolute value of the first difference.

[0100] For the second type RRAM memory cell array, there is no need to use a gate MOSFET to control the conduction state of the target memory cell. Accordingly, the second type RRAM memory cell array does not have WL1A-WL8A, and the control module 11 does not have a row decoder 113 .

[0101] In addition, the method of modifying the storage value in the second type RRAM memory cell is substantially the same as that of the first type RRAM memory cell, and will not be described in detail herein.

[0102] The following introduces the structure of the PCM storage cell array and the method of modifying the storage value.

[0103] The typical structure of a PCM storage cell is an upper electrode, a chalcogenide, a resistive heater, and a lower electrode. For example, the chalcogenide can be an alloy material called GST (Ge2Sb2Te5) composed of three elements: germanium, antimony, and tellurium. In the amorphous state, the molecular structure of the GST alloy is disordered, so the resistivity is also high. In contrast, in the crystalline state, the molecular structure of GST is neat and orderly, and the resistivity is relatively low.

[0104] By applying different forms of current pulses between the two electrodes of the memory cell, the chalcogenide is heated to change between the crystalline and amorphous states, thereby changing its resistance value to achieve a change in its current value (i.e., storage value). The state of PCM can be a variety of states between the fully polycrystalline state and the fully amorphous state, thereby achieving multi-value storage. The state of the PCM memory cell can remain unchanged after power failure, showing non-volatility.

[0105] The PCM memory cell is connected to the outside through the upper electrode and the lower electrode, which is the same as the RRAM memory cell. However, the specific operation method for modifying the storage value is different. When a relatively large current with a short duration is applied between the upper electrode and the lower electrode of the PCM memory cell, the chalcogenide compound will melt and form a high-resistance amorphous state, thereby increasing the resistance of the PCM memory cell and reducing the storage value in the PCM memory cell. This can be called a reset operation, which is equivalent to the aforementioned programming operation. When a relatively small current with a long duration is applied between the upper electrode and the lower electrode of the PCM memory cell, the chalcogenide compound will form a low-resistance crystalline state, thereby increasing the storage value in the PCM memory cell. This can be called a set operation, which is equivalent to the aforementioned erase operation.

[0106] The structure of PCM memory cell array is the same as that of RRAM memory cell array. The only difference is that the memory cell is PCM memory cell instead of RRAM memory cell. PCM memory cell array can also be divided into two types. The first type of PCM memory cell array is the same as the first type of RRAM memory cell array. The specific connection structure can be seen in Figure 7 In the second type of PCM memory cell array, each PCM memory cell is electrically connected to a diode or a selector, or the PCM memory cell itself has a self-selection characteristic.

[0107] The connection relationship between the first type of PCM memory cell array and the outside is the same as the connection relationship between the first type of RRAM memory cell array and the outside. The only difference is that in the embodiment of the present application, the voltage generator 112 in the aforementioned embodiment should be a voltage / current generator, the second voltage output terminal in the aforementioned embodiment should be a second voltage / current output terminal, and the third voltage output terminal in the aforementioned embodiment should be a third voltage output terminal or a third current input terminal.

[0108] In the embodiment of the present application, for the first type of PCM storage cell array, the specific implementation method of increasing the storage value in the target storage cell is as follows.

[0109] The way in which the processor 111 obtains the current value and the target current value in the target PCM storage unit is the same as the aforementioned way in which the current value and the target current value in the target RRAM storage unit are obtained, and will not be described in detail herein.

[0110] After obtaining the first difference between the target current value and the current current value, the processor 111 can calculate the relevant electrical parameters and send them to the voltage / current generator. The voltage / current generator outputs the current I_SET at the second voltage / current output terminal according to the relevant electrical parameters, and the duration (recorded as the second duration) is within the range of [t_min, A], which is different from the above embodiment. The processor 111 can make the set current flowing through the target storage unit I_SET by selecting and controlling the row decoder 113, the row decoder 114, the switching decoder 115 and the column decoder 116 (the specific implementation method is the same as the above content), and the current direction is from the upper electrode to the lower electrode, so that the resistance of the target storage unit is reduced, thereby increasing the storage value in the target storage unit. Among them, the values ​​of I_SET, t_min, and A are determined according to the characteristics of the PCM storage unit itself.

[0111] In the above process, the set current is a constant value I_SET, and the modification amount of the target storage value can be changed by adjusting the second duration. Specifically, when calculating the second duration, by making the second duration positively correlated with the absolute value of the first difference and within the preset range [t_min, A], when the absolute value of the first difference is large, the modification amount of the storage value in the target storage unit is also large.

[0112] In the embodiment of the present application, for the first type of PCM storage cell array, the specific implementation method of reducing the storage value in the target storage cell is as follows.

[0113] After obtaining the first difference between the target current value and the current current value, the processor 111 can calculate the relevant parameters and send them to the voltage / current generator. According to the relevant parameters, the voltage / current generator outputs a current I1 at the second voltage / current output terminal, and I1 is within the preset range [I_min, I_RESET), and the duration (recorded as the second duration) is a constant value B, which is different from the above embodiment. The processor 111 can make the reset current flowing through the target storage unit I1 by gating and controlling the row decoder 113, the row decoder 114, the switching decoder 115 and the column decoder 116 (whose specific implementation method is the same as the above content), and the current direction is from the upper electrode to the lower electrode, so that the resistance of the target storage unit increases, thereby reducing the storage value in the target storage unit. Among them, I_min, I_RESET, B are determined according to the characteristics of the PCM storage unit itself, and satisfy B< <t_min<A,I_SET<I_min<I_RESET。

[0114] In the second type of PCM memory cell array, there is no need to use a gate MOSFET to control the conduction state of the target memory cell. Accordingly, WL1A-WL8A does not exist, and the control module 11 does not store the row decoder 113 either.

[0115] In addition, the manner of modifying the storage value in the second type PCM storage unit is substantially the same as that of the first type PCM storage unit, and will not be described in detail herein.

[0116] In one embodiment of the present application, after calculating the first difference, the control module 11 can first determine whether the first difference between the target current value and the first current value flowing through the target storage is greater than the preset current value. If so, then generate a corresponding erase voltage or erase current according to the first difference to modify the storage value in the target storage unit, if not, then directly end.

[0117] Specifically, the preset current value is the current value corresponding to the maximum allowable error value. For example, the maximum allowable error value is 0.2, and the target storage unit can store 8 bits of data. The current value corresponding to the maximum storage value 255 is 10uA. Then, it can be determined that the current value corresponding to the maximum allowable error value is 10uA÷256×0.2=7.8nA. If the processor 111 determines that the first difference is less than 7.8nA, it indicates that the difference between the current storage value and the target storage value is less than the maximum allowable error value, and there is no need to modify the current storage value. Therefore, it can be ended directly without generating a corresponding erase voltage or erase current based on the first difference. On the contrary, if the first difference is greater than 7.8nA, it is necessary to generate a corresponding erase voltage or erase current based on the first difference to modify the current storage value.

[0118] After applying an erase voltage or erase current to the target storage unit, the second current value flowing through the target storage unit can be read in the current reading cycle, and the second difference between the target current value and the second current value flowing through the target storage unit is calculated to determine whether the second difference is greater than the preset current value. If so, it indicates that the difference between the current storage value and the target storage value is greater than the maximum allowable error value, so it is necessary to generate a corresponding erase voltage or erase current based on the second difference to modify the storage value in the target storage unit again. By looping through the above steps until the difference between the target current value and the actual current value flowing through the target storage unit is less than the preset current value, the modification of the storage value in the target storage unit can be finally completed.

[0119] Generally speaking, when modifying the storage value of a storage unit, the number of modifications is less than a specific number, and the specific number can be determined by counting the number of modifications to the storage value of the storage unit before. For example, if the number of modifications required to modify the current storage value to the target storage value is counted 1000 times, and the maximum value of all the modification times is 50 times, then the specific number can be considered to be 50 times. When the number of modifications exceeds 50 times, it indicates that the current storage value cannot be modified to the target storage value due to a fault (for example, damage to the target storage unit).

[0120] Therefore, in order to avoid falling into the process of invalid modification of the stored value and improve the modification efficiency of the stored value, in one embodiment of the present application, the control module 11 can accumulate and count the number of executions of applying the erase voltage or erase current, so as to obtain the total number of executions. Before calculating the electrical parameters according to the first difference each time, the control module can first compare the number of executions with the preset number of times (the preset number of times can be set according to the aforementioned specific number of times). If it is greater than or equal to the preset number of times, it will end directly and issue a corresponding alarm message to prompt relevant personnel to detect the cause of the fault. If it is less than the preset number of times, the electrical parameters are calculated according to the first difference.

[0121] The memory cell array includes multiple memory cells. Due to the inconsistency of the manufacturing process of different memory cells, each memory cell has certain differences in structure. This makes the change of the storage value in the memory cell different when the same erase voltage or erase current is applied to different memory cells. Taking the Flash memory chip as an example, since the thickness of the tunneling layer between the floating gate and the control gate in the Flash memory cell is not the same, the change of the current value in different memory cells is different when the same erase voltage is applied.

[0122] Therefore, due to the inconsistency of different storage cells, the actual change in current value caused by the erase voltage or erase current calculated in the embodiment of the present application in the target storage cell may be appropriate, or it may be too large or too small, which will cause the modification speed of the stored value to be too fast or too slow. In order to solve this problem, it is necessary to more accurately control the change in current value in the storage cell. Specifically, in one embodiment of the present application, the change in current value caused by the last erase voltage or erase current can be calculated, and according to whether the change in current value is too large or too small, the erase voltage value (or erase current value) calculated this time or its duration is adjusted to adjust the change in current value caused by the erase voltage or erase current this time.

[0123] Exemplarily, the control module 11 can perform a difference operation on the current value flowing through the target storage unit after reading the current value flowing through the target storage unit for the N+1th time (N is a positive integer greater than 0), and the difference represents the actual current value change caused by the Nth application of the erase voltage or erase current value. Then, the actual current value change can be compared with the expected current value change range (the expected current value change range is the range that meets the expected current value change, which can be determined according to the expected storage value modification speed) to determine whether the actual current change is too large or too small. When it is determined that the actual current change is too large (or too small), it indicates that the calculated Nth erase voltage value or erase current value is not suitable for the target storage unit.

[0124] Generally speaking, the calculation method used to calculate the N+1th erase voltage value or erase current value is the same as that of the Nth time. In order to avoid the same problem when applying the N+1th erase voltage or erase current, after calculating the N+1th erase voltage value or erase current value, it can be adaptively adjusted so that the N+1th erase voltage or erase current can produce a current value change that is more in line with the expected amount, that is, the current value change that can be generated by the N+1th erase voltage is within the expected current value change range.

[0125] In one example, the storage unit is a Flash storage unit. If the actual current change caused by the N-th erasing voltage is too large, the control module 11 can reduce the erasing voltage value after calculating the N+1-th erasing voltage value, so that the current value change caused by the N+1-th erasing voltage is also reduced accordingly, so as to solve the problem of the large current value change caused by the erasing voltage. It is understandable that the erasing voltage value can also be kept unchanged, and the current value change can be adjusted by reducing its duration. Of course, the erasing voltage value and its duration can also be adjusted at the same time to adjust the size of the storage value modification amount. When the storage unit is of other types, the adjustment method is similar and will not be repeated here.

[0126] In a more specific example, still taking the storage unit as a Flash storage unit as an example, the maximum storage value in the target storage unit is 255, and the corresponding current value is 10uA. Therefore, the absolute value of the difference between the target current value and the current current value ranges from 0 to 10uA, and 0 to 10uA can be divided into multiple current difference intervals. The embodiment of the present application does not specifically limit the number of current difference intervals.

[0127] Exemplarily, it can be divided into 3 current difference intervals, namely the first current difference interval, the second current difference interval and the third current difference interval. The range of the first current difference interval is 0 to 1uA, which represents the situation that the target current value is close to the current current value. At this time, the expected change in current should also be small to ensure the accuracy of the modification of the stored value. For example, the first interval range of the expected change in current corresponding to the first current difference interval can be 36nA (the corresponding expected change in the stored value is 0.9) to 160nA (the corresponding expected change in the stored value is 4).

[0128] The second interval of the current difference value ranges from 1uA to 4uA, which indicates that the target current value is far from the current current value. At this time, the expected change in current should also be large, corresponding to a higher modification speed of the stored value. The second interval of the expected change in current corresponding to the second interval of the current difference value can range from 120nA (the corresponding expected change in the stored value is 3) to 480nA (the corresponding expected change in the stored value is 12).

[0129] The third interval of the current difference value ranges from 4uA to 10uA, which indicates that the target current value is further away from the current current value. At this time, the expected change in current should also be larger, corresponding to a higher modification speed of the stored value. For example, the third interval of the current difference value corresponding to the expected change in current can range from 240nA (the corresponding expected change in the stored value is 6) to 800nA (the corresponding expected change in the stored value is 20).

[0130] On this basis, if the current current value flowing through the target storage unit read for the N+1th time is 4uA, the target current value is 10uA, and the difference between the target current value and the current current value is 6uA, it can be judged that the difference falls into the third interval of the current difference. Combined with the current current value of 4.2uA flowing through the target storage unit read for the Nth time, it can be judged that the change in current value caused by the erase voltage applied for the Nth time is 200nA, which is less than the minimum value of 240nA in the range of the expected change in the third current. It can be seen that the change in current value caused by the erase voltage applied for the Nth time is small. Therefore, after calculating the erase voltage value and its duration for the N+1th time, in order to avoid the same problem, the erase voltage value can be increased and adjusted, or its duration can be increased and adjusted, so that the change in current value can be increased to solve the problem of small change in current value and slow modification speed of the stored value.

[0131] If the current value of the current flowing through the target storage unit read for the N+1th time is 9.2uA, the target current value is 10uA, and the difference between the target current value and the current current value is 0.8uA, it can be determined that the difference falls within the first interval of the current difference. Combined with the current value of the current flowing through the target storage unit read for the Nth time being 9.5uA, it can be determined that the change in the current value caused by the Nth application of the erase voltage is 300nA, which is greater than the maximum value of 160nA in the first interval range of the expected change in current. Therefore, after calculating the erase voltage for the N+1th time, the erase voltage can be reduced or adjusted, or its duration can be reduced and adjusted, so as to reduce the change in current value, so as to solve the problem of large change in current value and too fast modification speed of the stored value.

[0132] It is understood that the structure of the non-volatile memory chip 1 illustrated in the embodiment of the present application does not constitute a specific limitation on the non-volatile memory chip 1. In other embodiments of the present application, the non-volatile memory chip 1 may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0133] The above is an introduction to the non-volatile memory chip 1 provided in the embodiment of the present application. Next, based on the above content, a storage value modification method provided in the embodiment of the present application is introduced.

[0134] The storage value modification method provided in the embodiment of the present application can be applied to the non-volatile storage chip 1 in the above embodiment, and is specifically executed by the control module 11 in the non-volatile storage chip 1. Figure 8 As shown, the storage value modification method may include the following steps:

[0135] S801. The control module 11 obtains a target storage value corresponding to a target storage unit, and calculates a target current value according to the target storage value.

[0136] In an embodiment of the present application, the processor 111 can receive data to be stored from an external module via a communication interface, determine a target storage value to be stored in a target storage cell in the storage cell array 12 according to the data to be stored, and calculate a target current value corresponding to the target storage value.

[0137] S802 , the control module 11 reads a first current value flowing through a target storage unit.

[0138] In the embodiment of the present application, the processor 111 can calculate the corresponding voltage control parameter according to the size of the power supply voltage required for the current reading cycle, and send it to the voltage generator 112. The voltage generator 112 can generate the corresponding current reading cycle power supply voltage according to the voltage control parameter. The processor 111 can also perform gating control on the corresponding decoder so that the power supply voltage can be applied to the target storage unit. Then, the current reading module 117 can sample the current flowing through the target unit and perform analog-to-digital conversion, so as to obtain the current current value, and send the current current value to the processor 111.

[0139] S803, the control module 11 calculates a first difference between the target current value and the first current value, and determines whether the absolute value of the first difference is greater than a preset current value. If so, execute step S804, otherwise, end.

[0140] In the embodiment of the present application, the preset current value is the current value corresponding to the maximum allowable error value. The processor 111 can determine whether the first difference is greater than the preset current value. If so, it indicates that the difference between the current storage value and the target storage value is greater than the maximum allowable error value, so it is necessary to modify the storage value in the target storage unit according to the first difference, and specifically, step S804 can be executed. If not, it indicates that the difference between the current storage value and the target storage value is less than the maximum allowable error value, and there is no need to modify the current storage value, so it can end directly.

[0141] S804, the control module 11 determines whether the current erasure times of the target storage unit is less than the preset times, if so, execute step S805, if not, end.

[0142] In the embodiment of the present application, in order to avoid falling into the process of invalid modification of the storage value and improve the modification efficiency of the storage value, the processor 111 can compare the number of executions of applying the erase voltage (or erase current) with the preset number of times. If it is less than the preset number of times, it indicates that the storage value in the target storage unit can continue to be modified, so step S805 can be executed. If it is greater than or equal to the preset number of times, it indicates that it is likely due to a fault that the current storage value cannot be modified to the target storage value, so it can be directly terminated and a corresponding alarm message is issued to prompt relevant personnel to detect the cause of the fault.

[0143] S805, the control module 11 calculates the first electrical parameter according to the first difference, and generates a first erase voltage or a first erase current according to the first electrical parameter; wherein the first electrical parameter includes a first erase voltage value and a first duration, or a first voltage erase current value and a second duration.

[0144] In the embodiment of the present application, the processor 111 can calculate the first electrical parameter according to the first difference, and the first electrical parameter includes the first erase voltage value and the first duration, or the first voltage erase current value and the second duration. The processor 111 can send the first electrical parameter to the voltage generator 112, and the voltage generator 112 can generate an erase voltage of the first duration or an erase current of the second duration according to the first electrical parameter.

[0145] S806 , the control module 11 applies a first erase voltage to the target memory cell according to the first duration, or applies a first erase current to the target memory cell according to the second duration.

[0146] In the embodiment of the present application, the processor 111 can control the selection of each decoder to apply a first erase voltage to the target memory cell according to a first duration, or apply a first erase current to the target memory cell according to a second duration. At this point, steps S801 to S806 have completely implemented a modification of the storage value in the target memory cell.

[0147] S807 , the control module 11 reads a second current value flowing through the target storage unit.

[0148] This step is implemented in the same manner as step S802. The control module 11 provides the target memory cell with a current reading cycle supply voltage, and the current reading module 117 can read the current value (i.e., the second current value) flowing through the target memory cell. If the erase voltage or erase current is applied in step S806, the second current value is greater than the aforementioned first current value. On the contrary, if the programming voltage or programming current is applied in step S806, the second current value is less than the aforementioned first current value.

[0149] S808, the control module 11 calculates the second difference between the target current value and the second current value, and calculates the second electrical parameter according to the second difference; the second electrical parameter includes the value of the second erase voltage and the third duration, or the second erase current value and the fourth duration.

[0150] This step is the same as the implementation of step S805, the processor 111 can calculate the second difference between the target current value and the second current value, and calculate the second electrical parameter according to the second difference. Then the second parameter is sent to the voltage generator 112, and the voltage generator 112 can generate the second erase voltage of the third duration or the second erase current of the fourth duration according to the parameter.

[0151] S809, the control module 11 determines the first current difference interval to which the absolute value of the second difference belongs; the first current difference interval is one of multiple current difference intervals, and the multiple current difference intervals together cover the range from zero to the maximum current value in the target storage unit.

[0152] In the embodiment of the present application, since the possible value range of the absolute value of the second difference is from zero to the maximum current value in the target storage unit (i.e., the current value corresponding to the maximum storage value), it can be pre-divided into multiple current difference intervals. The processor 111 compares the absolute value of the second difference with each current difference interval respectively, and can determine the current difference first interval to which the absolute value of the second difference belongs.

[0153] S810, the control module 11 determines a first interval of expected current change corresponding to a first interval of current difference; the first interval of expected current change is one of a plurality of expected current change intervals, and the plurality of expected current change intervals respectively correspond to the plurality of current difference intervals in a one-to-one correspondence.

[0154] In the embodiment of the present application, multiple current expected change amount intervals can be preset according to the expected storage value modification speed. A one-to-one correspondence is established between the multiple current expected change amount intervals and the aforementioned multiple current difference value intervals, and the specific correspondence is that the current difference interval with a larger value corresponds to the current expected change amount interval with a larger value, and the current difference interval with a smaller value corresponds to the current expected change amount interval with a smaller value. The processor 111 can determine the first current expected change amount interval corresponding to the first current difference value interval according to the preset correspondence relationship.

[0155] S811, the control module 11 calculates the actual difference between the second current value and the first current value, and determines whether the actual difference is within the first interval of the expected current change. If so, execute step S812, if not, execute step S813.

[0156] In the embodiment of the present application, the processor 111 can calculate the actual difference between the second current value and the first current value. If step S806 is the Nth application of the erase voltage or erase current, the actual difference represents the change in current value caused by the Nth application of the erase voltage or erase current. The processor 111 can compare the actual difference with the maximum and minimum values ​​of the first interval of the expected current change to determine whether the actual difference is within the first interval of the expected current change.

[0157] If the actual difference is within the first interval of the expected current change, it indicates that there is no need to adjust the second electrical parameter, and step S812 can be performed next. If the actual difference is not within the first interval of the expected current change, it indicates that the actual difference is greater than the maximum value of the first interval of the expected current change (the actual difference is too large), or less than the minimum value of the first interval of the expected current change (the actual difference is too small). In order to avoid the same problem as the Nth time when applying the erase voltage or erase current for the N+1th time, the second electrical parameter needs to be adjusted, and step S813 can be performed next.

[0158] S812: The control module 11 applies a corresponding erase voltage or erase current to the target memory cell according to the second electrical parameter.

[0159] In the embodiment of the present application, when the actual difference is within the first interval of the expected current change, it indicates that the current value change caused by the erase voltage or erase current applied for the Nth time is appropriate, and there is no problem of being too large or too small, which means that the current calculation method is applicable to the target memory cell. Therefore, when applying the N+1th erase voltage or erase current, there is no need to adjust the second electrical parameter, and the second electrical parameter can be directly sent to the voltage generator 112. The voltage generator 112 can generate the corresponding N+1th erase voltage or erase current according to the second electrical parameter, and apply it to the target memory cell to generate a suitable current value change.

[0160] S813: The control module 11 adjusts the second electrical parameter, and applies an erase voltage or an erase current to the target memory cell accordingly according to the adjusted second electrical parameter.

[0161] In the embodiment of the present application, if the actual difference is not within the first interval of the expected change in current, it indicates that the change in current value caused by the erase voltage or erase current applied for the Nth time is too large or too small. Therefore, the processor 111 can adjust the value of the second erase voltage and / or the third duration (or the value of the second erase current and / or the fourth duration) in the second electrical parameter, and send the adjusted second electrical parameter to the voltage generator 112. The voltage generator 112 can generate a corresponding erase voltage or erase current according to the modified second electrical parameter, and apply it to the target storage unit to solve the problem that the change in current value caused by the erase voltage or erase current applied for the N+1th time is too small or too large.

[0162] The specific adjustment method of the second electrical parameter has been described in detail in the above embodiments and will not be described in detail here.

[0163] It should be noted that after executing step S812 or S813, the current value flowing through the target storage unit can be further read, that is, step S802 is executed. By looping through the above steps until the difference between the target current value and the actual current value flowing through the target storage unit is less than the preset current value, the modification of the storage value in the target storage unit can be finally completed.

[0164] It should be noted that the memory cell array in the embodiment of the present application may include various types. The specific implementation details of the storage value modification method in various types of memory cell arrays have been described in detail in the above embodiments and will not be repeated here.

[0165] It is understandable that the size of the sequence number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. In addition, in some possible implementations, each step in the above embodiment can be selectively executed according to actual conditions, and can be partially executed or fully executed, which is not limited here.

[0166] The control module 11 in the embodiment of the present application includes a processor 111, and the processor 111 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0167] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0168] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions may be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0169] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

Claims

1. A method for modifying a stored value, characterized in that: The method is applied to a non-volatile memory chip, wherein the non-volatile memory chip comprises a storage cell array and a control module; the storage cell array comprises at least one storage cell, and the storage cell is a multi-value storage cell; The control module is electrically connected to the storage cell array; The method comprises: The control module obtains a target storage value corresponding to a target storage unit, and calculates a target current value according to the target storage value; reads a first current value flowing through the target storage unit; calculates a first difference between the target current value and the first current value, and calculates a first electrical parameter according to the first difference; the first electrical parameter includes a first erase voltage value and a first duration, or a first erase current value and a second duration; The control module generates a corresponding first erase voltage according to the first erase voltage value, and applies the first erase voltage to the target memory cell according to the first duration; the current change amount induced by the first erase voltage in the target memory cell is positively correlated with the absolute value of the first difference; or, The control module generates a corresponding first erase current according to the first erase current value, and applies the first erase current to the target storage unit according to the second duration; the current change caused by the first erase current in the target storage unit is positively correlated with the absolute value of the first difference.

2. The method according to claim 1, characterized in that: The method further comprises: The control module reads a second current value flowing through the target storage unit, calculates a second difference between the target current value and the second current value, and calculates a second electrical parameter according to the second difference; the second electrical parameter includes a value of a second erase voltage and a third duration, or a second erase current value and a fourth duration; The control module calculates an actual difference between the second current value and the first current value, and determines whether the actual difference is within a first interval of expected current change; If the actual difference is not within the first interval of the expected current change, the control module adjusts the second electrical parameter; The control module applies a corresponding erase voltage or erase current to the target memory cell according to the adjusted second electrical parameter.

3. The method according to claim 2, characterized in that The method further comprises: If the actual difference is within the first interval of the expected current change, the control module applies a corresponding erase voltage or erase current to the target memory cell according to the second electrical parameter.

4. The method according to claim 2 or 3, characterized in that: The control module calculates an actual difference between the second current value and the first current value, and determines whether the actual difference is within a first interval of the expected current change, including: The control module determines a first current difference interval to which the absolute value of the second difference belongs; the first current difference interval is one of a plurality of current difference intervals, and the plurality of current difference intervals together cover a range from zero to a maximum current value in the target storage unit; The control module determines a first interval of expected current change corresponding to the first interval of current difference; the first interval of expected current change is one of a plurality of intervals of expected current change, and the plurality of intervals of expected current change are in one-to-one correspondence with the plurality of current difference intervals respectively; The control module calculates an actual difference between the second current value and the first current value, and determines whether the actual difference is within a first interval of expected current change.

5. The method according to any one of claims 1 to 4, characterized in that The memory cell array is a flash memory cell array, an erasable programmable read-only memory cell array, a charged erasable programmable read-only memory cell array, a variable resistance memory cell array or a phase change memory cell array.

6. The method according to any one of claims 1 to 4, characterized in that The memory cell array is a variable resistance memory cell array; the first electrical parameter includes a current limit value, a first erase voltage value and a first duration; The control module generates a corresponding first erase voltage according to the first erase voltage value, and applies the first erase voltage to the target storage unit according to the first duration, including: The control module generates a corresponding first erase voltage according to the first erase voltage value, applies the first erase voltage to the target memory cell according to the first duration, and limits the current flowing through the target memory cell to below the current limit value.

7. The method according to any one of claims 1 to 6, characterized in that The calculating a first difference between the target current value and the first current value, and calculating a first electrical parameter according to the first difference, comprises: Calculating a first difference between a target current value and the first current value; Determine whether the absolute value of the first difference is greater than a preset current value; wherein the preset current value is a current value corresponding to a maximum allowable error value; If it is greater than a preset current value, a first electrical parameter is calculated according to the first difference.

8. The method according to any one of claims 1 to 6, characterized in that The calculating a first difference between the target current value and the first current value, and calculating a first electrical parameter according to the first difference, comprises: Calculating a first difference between a target current value and the first current value; Determine whether the number of erasures and writes to the target storage unit is less than a preset number; If it is less than the preset number, the first electrical parameter is calculated according to the first difference.

9. A non-volatile memory chip, characterized in that: include: A control module, configured to execute the method according to any one of claims 1 to 8; A memory cell array for storing data; The memory cell array includes at least one memory cell, and the memory cell is a multi-value memory cell.

10. The non-volatile memory chip according to claim 9, characterized in that: The memory cell array is a flash memory cell array, an erasable programmable read-only memory cell array, a charged erasable programmable read-only memory cell array, a variable resistance memory cell array or a phase change memory cell array.

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