Preparation method of chip packaging structure and chip packaging structure
By making a separable glue layer and seed layer on both sides of the substrate, and building a rewiring layer and packaging chip, the problem of easy warping of the glass substrate is solved, and the quality and production efficiency of the chip packaging structure are improved.
Patent Information
- Application Number
- CN202411816283.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-03-25
AI Technical Summary
In the existing semiconductor packaging technology, using glass substrates is prone to warping, which reduces product yield and affects production efficiency.
The first separable glue layer and the second separable glue layer are respectively made on both sides of the substrate, and the first seed layer and the second seed layer are made on the side away from the substrate. Then the first and second re-wire layer are constructed, the chip is arranged and the plastic sealing layer is encapsulated, and finally the separable glue layer is removed and the wiring is made based on the seed layer to form a chip packaging structure.
This method reduces substrate warpage and improves product yield and production efficiency of chip packaging structures.
Smart Images
Figure CN119694899A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a method for preparing a chip packaging structure and a chip packaging structure. Background Art
[0002] In the field of semiconductor packaging technology, glass is usually used as a substrate, and then a redistribution layer is constructed on it, and the chip mounting and plastic sealing steps are completed in sequence. However, this packaging method is not only prone to undesirable phenomena such as glass warping, which reduces the product yield of the chip packaging structure, but also affects the production efficiency of the chip packaging structure. Summary of the invention
[0003] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a method for preparing a chip packaging structure, the method comprising:
[0004] providing a substrate;
[0005] Forming a first separable adhesive layer and a second separable adhesive layer on opposite sides of the substrate respectively;
[0006] Forming a first seed layer and a second seed layer respectively on the side of the first removable adhesive layer and the second removable adhesive layer away from the substrate;
[0007] Forming a first redistribution layer on a side of the first seed layer away from the substrate, and forming a second redistribution layer on a side of the second seed layer away from the substrate;
[0008] Disposing at least one chip on a side of the first redistribution layer and a side of the second redistribution layer away from the substrate respectively;
[0009] Making a plastic packaging layer that at least encapsulates the chip;
[0010] removing the first separable adhesive layer and the second separable adhesive layer, and separating the substrate from the first seed layer and the second seed layer;
[0011] Routing is fabricated based on the first seed layer and the second seed layer respectively to obtain a chip packaging structure.
[0012] In a possible implementation, in the step of forming a first redistribution layer on a side of the first seed layer away from the substrate, and forming a second redistribution layer on a side of the second seed layer away from the substrate, the method includes:
[0013] Forming a first dielectric layer on a side of the first seed layer away from the substrate, and forming a second dielectric layer on a side of the second seed layer away from the substrate;
[0014] Making a first through hole penetrating the first dielectric layer on the first dielectric layer, and making a second through hole penetrating the second dielectric layer on the second dielectric layer;
[0015] A first wiring layer is fabricated on a side of the first dielectric layer away from the substrate, and a second wiring layer is fabricated on a side of the second dielectric layer away from the substrate, wherein the first wiring layer includes wirings filling the first through holes, and the second wiring layer includes wirings filling the second through holes;
[0016] Repeat the steps of alternately forming a first dielectric layer and a first routing layer on a side of the first routing layer away from the substrate to obtain the first redistribution layer, and alternately forming a second dielectric layer and a second routing layer on a side of the second routing layer away from the substrate to obtain the second redistribution layer.
[0017] In a possible implementation manner, in the step of manufacturing a first wiring layer on a side of the first dielectric layer away from the substrate, and manufacturing a second wiring layer on a side of the second dielectric layer away from the substrate, the method includes:
[0018] forming a third seed layer on the first dielectric layer after forming the first through hole, and forming a fourth seed layer on the second dielectric layer after forming the second through hole;
[0019] Forming a first photoresist layer on a side of the third seed layer and a side of the fourth seed layer away from the substrate respectively;
[0020] Performing patterning on the first photoresist layer to form a first photoresist layer window exposing a portion of the third seed layer and the fourth seed layer;
[0021] The third seed layer exposed through the first photoresist layer window generates a first wiring layer, and the fourth seed layer exposed through the first photoresist layer window generates a second wiring layer.
[0022] In a possible implementation manner, in the step of manufacturing a first wiring layer on a side of the first dielectric layer away from the substrate, and manufacturing a second wiring layer on a side of the second dielectric layer away from the substrate, the method includes:
[0023] forming a third seed layer on the first dielectric layer after forming the first through hole, and forming a fourth seed layer on the second dielectric layer after forming the second through hole;
[0024] forming a first electroplating layer on the first dielectric layer through the third seed layer, and forming a second electroplating layer on the second dielectric layer through the fourth seed layer;
[0025] The first electroplating layer is patterned to obtain a first wiring layer, and the second electroplating layer is patterned to obtain a second wiring layer.
[0026] In a possible implementation, the step of making a first through hole penetrating the first dielectric layer on the first dielectric layer, and making a second through hole penetrating the second dielectric layer on the second dielectric layer includes:
[0027] Making a first through hole penetrating through the first dielectric layer on the first dielectric layer;
[0028] A second through hole penetrating the second dielectric layer is formed on the second dielectric layer, and the second through hole is arranged in a staggered manner with the first through hole.
[0029] In a possible implementation, in the step of respectively making routings based on the first seed layer and the second seed layer to obtain a chip packaging structure, the method includes:
[0030] Forming a second photoresist layer on the first seed layer and the second seed layer respectively on a side away from the first dielectric layer and the second dielectric layer;
[0031] Performing patterning on the second photoresist layer to form a second photoresist layer window exposing a portion of the first seed layer and the second seed layer;
[0032] The first seed layer and the second seed layer exposed through the second photoresist layer window form wiring to obtain a chip packaging structure.
[0033] In a possible implementation, in the step of respectively making routings based on the first seed layer and the second seed layer to obtain a chip packaging structure, the method includes:
[0034] forming a third electroplating layer on the first dielectric layer through the first seed layer, and forming a fourth electroplating layer on the second dielectric layer through the second seed layer;
[0035] The third electroplating layer and the fourth electroplating layer are patterned to form wiring, thereby obtaining a chip packaging structure.
[0036] In a possible implementation, in the step of respectively making routings based on the first seed layer and the second seed layer to obtain a chip packaging structure, the method includes:
[0037] Routing units are made based on the first seed layer and the second seed layer respectively. The routing units are arranged at equal intervals on a side of the first seed layer away from the first redistribution layer and a side of the second seed layer away from the second redistribution layer to form routing to obtain a chip packaging structure.
[0038] In a possible implementation, in the step of respectively forming a first seed layer and a second seed layer on a side of the first separable adhesive layer and the second separable adhesive layer away from the substrate, the method includes:
[0039] A first seed layer and a second seed layer are respectively formed on the side of the first separable adhesive layer and the second separable adhesive layer away from the substrate by physical vapor deposition.
[0040] Another object of the present application is to provide a chip packaging structure, which is prepared by a plurality of chip packaging structure preparation methods provided in the present application.
[0041] Based on any of the above aspects, the embodiments of the present application provide a method for preparing a chip packaging structure and a chip packaging structure. The above solution manufactures the chip packaging structure on both sides of the substrate at the same time, which not only reduces the warping of the substrate, but also improves the production efficiency of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0043] Figure 1 A step diagram of a method for preparing a chip packaging structure provided in this embodiment;
[0044] Figure 2a-2e for Figure 1 The corresponding process diagram;
[0045] Figure 3 for Figure 1 Flow chart of sub-steps of step S140;
[0046] Figure 4a and Figure 4b for Figure 3 Corresponding process flow chart.
[0047] Icons: substrate-1; first detachable adhesive layer-20; second detachable adhesive layer-21; first seed layer-30; second seed layer-31; first redistribution layer-40; second redistribution layer-41; first dielectric layer-400; first through hole-4001; first routing layer-401; second dielectric layer-410; second through hole-4101; second routing layer-411; chip-5; plastic encapsulation layer-6; routing-7. DETAILED DESCRIPTION
[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0049] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0050] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0051] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0052] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0053] In order to solve the technical problems mentioned in the aforementioned background technology, the inventor innovatively designed the following technical solution, and the specific implementation solution of the present application will be described in detail below with reference to the accompanying drawings.
[0054] See also Figure 1 and Figure 2a-2e , Figure 1A step diagram of a method for preparing a chip packaging structure provided in this embodiment, Figure 2a-2e for Figure 1 The corresponding process flow chart. The preparation method of the chip packaging structure includes:
[0055] Step S110, providing a substrate 1.
[0056] In this embodiment, the substrate 1 serves as the basis of the entire chip packaging structure process, and is usually made of a material with high stability and good conductivity, such as glass, ceramic, etc.
[0057] Step S120 , forming a first removable adhesive layer 20 and a second removable adhesive layer 21 on opposite sides of the substrate 1 , respectively.
[0058] In this embodiment, the first removable adhesive layer 20 and the second removable adhesive layer 21 are mainly used to protect the substrate 1 in the subsequent packaging process, and are conveniently removed after the chip packaging structure is packaged, so as to separate the substrate 1 from the chip packaging structure.
[0059] It is worth noting that the materials of the first removable adhesive layer 20 and the second removable adhesive layer 21 can be polymer adhesives, which have the advantages of strong adhesion and strong separability. For example, the materials of the first removable adhesive layer 20 and the second removable adhesive layer 21 can be photosensitive adhesive or heat-sensitive adhesive. The materials of the first removable adhesive layer 20 and the second removable adhesive layer 21 are not specifically limited here and need to be selected according to actual conditions.
[0060] In step S130 , a first seed layer 30 and a second seed layer 31 are respectively formed on the side of the first removable adhesive layer 20 and the second removable adhesive layer 21 away from the substrate 1 .
[0061] In this embodiment, the first seed layer 30 and the second seed layer 31 provide a conductive foundation for the first redistribution layer 40 and the second redistribution layer 41 to ensure good electrical connection.
[0062] It is worth noting that the first seed layer 30 and the second seed layer 31 may be made of copper, nickel or gold, etc. The materials of the first seed layer 30 and the second seed layer 31 are not specifically limited here and need to be selected according to actual conditions.
[0063] In step S140 , a first redistribution layer 40 is formed on a side of the first seed layer 30 away from the substrate 1 , and a second redistribution layer 41 is formed on a side of the second seed layer 31 away from the substrate 1 .
[0064] In this embodiment, a first redistribution layer 40 and a second redistribution layer 41 are respectively made on the side of the first seed layer 30 and the second seed layer 31 away from the substrate 1, and the input and output ports of the chip 5 are rearranged through the first redistribution layer 40 and the second redistribution layer 41 to adapt to different electrical requirements and realize the connection between the chip 5 and the external circuit.
[0065] Step S150 , at least one chip 5 is disposed on a side of the first redistribution layer 40 and a side of the second redistribution layer 41 away from the substrate 1 .
[0066] In this step, at least one chip 5 is placed on the side of the first redistribution layer 40 and the second redistribution layer 41 away from the substrate 1 through a process such as bonding or welding, so that the chip 5 is connected to the first redistribution layer 40 and the second redistribution layer 41.
[0067] Step S160 , manufacturing a plastic packaging layer 6 for packaging at least the chip 5 .
[0068] In this embodiment, the plastic layer 6 is used to protect the chip 5 from being damaged by the external environment. The plastic layer 6 is usually made of a material with high insulation and heat resistance, such as epoxy resin, and is disposed at least around the chip 5 by injection molding or molding.
[0069] Step S170, removing the first removable adhesive layer 20 and the second removable adhesive layer 21, and separating the substrate 1 from the first seed layer 30 and the second seed layer 31;
[0070] In this step, the first removable adhesive layer 20 and the second removable adhesive layer 21 are usually removed by laser, so as to separate the substrate 1 from the first seed layer 30 and the second seed layer 31 .
[0071] Step S180 , manufacturing traces 7 based on the first seed layer 30 and the second seed layer 31 respectively, to obtain a chip packaging structure.
[0072] In this step, wiring 7 is fabricated based on the first seed layer 30 and the second seed layer 31 respectively to realize electrical connection between the internal and external circuits of the chip packaging structure.
[0073] In this embodiment, the first detachable adhesive layer 20 and the second detachable adhesive layer 21, the first seed layer 30 and the second seed layer 31, the first redistribution layer 40 and the second redistribution layer 41, the chip 5 and the plastic packaging layer 6 are sequentially manufactured on both sides of the substrate 1, and then the first detachable adhesive layer 20 and the second detachable adhesive layer 21 are removed to obtain at least one chip packaging structure. This packaging method not only ensures that the pressure distribution on both sides of the substrate 1 is balanced, reduces the warping phenomenon of the substrate 1, and improves the product yield of the chip packaging structure, but also greatly improves the production efficiency of the chip packaging structure.
[0074] For further information, see Figure 3 , Figure 4a and Figure 4b , Figure 3 The method step diagram of sub-step S143 provided in this embodiment, Figure 4a and Figure 4b for Figure 3 Corresponding process flow chart. Step S140 can be implemented in the following manner.
[0075] Sub-step S141, forming a first dielectric layer 400 on a side of the first seed layer 30 away from the substrate 1, and forming a second dielectric layer 410 on a side of the second seed layer 31 away from the substrate 1;
[0076] In this step, the first dielectric layer 400 and the second dielectric layer 410 are composed of insulating materials. When the first dielectric layer 400 and the second dielectric layer 410 and the first wiring layer 401 and the second wiring layer 411 are multi-layered, the first dielectric layer 400 and the second dielectric layer 410 are intended to isolate the conductive structures at different levels to prevent electrical short circuits. The first dielectric layer 400 and the second dielectric layer 410 can be formed by coating a first insulating material (such as epoxy resin PI), or by laminating a second insulating material (such as Ajinomoto stacking film ABF).
[0077] Sub-step S142 , making a first through hole 4001 penetrating the first dielectric layer 400 on the first dielectric layer 400 , and making a second through hole 4101 penetrating the second dielectric layer 410 on the second dielectric layer 410 ;
[0078] In this step, the first through hole 4001 and the second through hole 4101 can be respectively made on the first dielectric layer 400 and the second dielectric layer 410 by means of an exposure process or a laser process.
[0079] Sub-step S143, making a first routing layer 401 on a side of the first dielectric layer 400 away from the substrate 1, and making a second routing layer 411 on a side of the second dielectric layer 410 away from the substrate 1, wherein the first routing layer 401 includes routing that fills the first through hole 4001, and the second routing layer 411 includes routing that fills the second through hole 4101.
[0080] In this embodiment, during the production process of the first routing layer 401 and the second routing layer 411, it is necessary to ensure that the first through hole 4001 and the second through hole 4101 are filled. The first through hole 4001 and the second through hole 4101 serve as electrical connection points between the subsequent first routing layer 401 and the second routing layer 411 and the underlying conductive structure (the first seed layer 30 and the second seed layer 31).
[0081] Sub-step S144, repeatedly alternately forming the first dielectric layer 400 and the first routing layer 401 on the side of the first routing layer 401 away from the substrate 1 to obtain the first redistribution layer 40, and simultaneously alternately forming the second dielectric layer 410 and the second routing layer 411 on the side of the second routing layer 411 away from the substrate 1 to obtain the second redistribution layer 41.
[0082] In this step, when a multi-layer circuit structure is required, the first dielectric layer 400 and the first routing layer 401 should be repeatedly and alternately added to form the first redistribution layer 40, and the second dielectric layer 410 and the second routing layer 411 should be repeatedly and alternately added to form the second redistribution layer 41. The first dielectric layer 400 or the second dielectric layer 410 between each layer provides electrical isolation, while the first routing layer 401 or the second routing layer 411 between each layer realizes electrical connection between layers to meet complex circuit requirements.
[0083] Further, sub-step S143 can be implemented in the following manner.
[0084] First, a third seed layer is formed on the first dielectric layer after the first through hole is formed, and a fourth seed layer is formed on the second dielectric layer after the second through hole is formed.
[0085] In this embodiment, the third seed layer and the fourth seed layer provide a good adhesion foundation for the subsequent first wiring layer and the second wiring layer, and also ensure the reliability of electrical connection.
[0086] Next, a first photoresist layer is formed on the side of the third seed layer and the side of the fourth seed layer away from the substrate.
[0087] Then, the first photoresist layer is patterned to form a first photoresist layer window exposing a portion of the third seed layer and the fourth seed layer.
[0088] Finally, the third seed layer exposed through the first photoresist layer window generates a first wiring layer, and the fourth seed layer exposed through the first photoresist layer window generates a second wiring layer.
[0089] In this embodiment, metal is deposited on the third seed layer and the fourth seed layer exposed by the first photoresist layer window by an electroplating process to form a first wiring layer and a second wiring layer. The electroplating solution in the electroplating process usually contains a high concentration of metal ions, and the metal is deposited on the third seed layer and the fourth seed layer by the action of electric current. After the electroplating is completed, the remaining first photoresist layer and the third seed layer and the fourth seed layer corresponding to the remaining first photoresist layer are removed.
[0090] It is worth noting that the first photoresist window formed by patterning the first photoresist layer needs to include a first through hole and a second through hole to achieve electrical connection between different layers.
[0091] Furthermore, sub-step S143 can also be implemented in the following manner.
[0092] First, a third seed layer is formed on the first dielectric layer after the first through hole is formed, and a fourth seed layer is formed on the second dielectric layer after the second through hole is formed.
[0093] Next, a first electroplating layer is formed on the first dielectric layer through the third seed layer, and a second electroplating layer is formed on the second dielectric layer through the fourth seed layer.
[0094] In this embodiment, the exposed third seed layer and the fourth seed layer are usually contacted with the electroplating solution, and the exposed third seed layer and the fourth seed layer are used as electroplating cathodes in the electroplating process. The metal ions in the electroplating solution are reduced to metal atoms after obtaining electrons at the positions of the third seed layer and the fourth seed layer, and are deposited on the third seed layer and the fourth seed layer to form a first electroplating layer and a second electroplating layer.
[0095] Then, the first electroplating layer is patterned to obtain a first wiring layer, and the second electroplating layer is patterned to obtain a second wiring layer.
[0096] In this embodiment, photoresist is uniformly coated on the first electroplating layer and the second electroplating layer, and then exposed and developed by photolithography technology to form the desired patterns of the first wiring layer and the second wiring layer. Finally, the first electroplating layer and the second electroplating layer not protected by the photoresist and the corresponding third seed layer and fourth seed layer can be removed by etching to form the first wiring layer and the second wiring layer.
[0097] Further, sub-step S142 can be implemented in the following manner.
[0098] First, a first through hole penetrating the first dielectric layer is formed on the first dielectric layer.
[0099] Then, a second through hole penetrating the second dielectric layer is made on the second dielectric layer, and the second through hole is arranged in a staggered manner with the first through hole.
[0100] In this embodiment, a first through hole and a second through hole are respectively made on both sides of the substrate, the first through hole and the second through hole are staggered and arranged, and the first through hole and the second through hole are centrally symmetrically distributed about the center of the substrate, which can balance the pressure on both sides of the substrate and reduce the warping of the substrate.
[0101] Furthermore, step S180 may be implemented in the following manner.
[0102] First, a second photoresist layer is formed on the sides of the first seed layer and the second seed layer away from the first dielectric layer and the second dielectric layer respectively.
[0103] In this embodiment, the first seed layer and the second seed layer provide a good adhesion foundation for subsequent wiring production.
[0104] Next, the second photoresist layer is patterned to form a second photoresist layer window exposing a portion of the first seed layer and the second seed layer.
[0105] Then, wiring is formed on the first seed layer and the second seed layer exposed through the second photoresist layer window to obtain a chip packaging structure.
[0106] In this embodiment, metal is deposited on the first seed layer and the second seed layer exposed in the second photoresist layer window by electroplating to form a trace. After the electroplating is completed, the remaining second photoresist layer and the first seed layer and the second seed layer corresponding to the remaining second photoresist layer are removed.
[0107] Furthermore, step S180 can also be implemented in the following manner.
[0108] First, a third electroplating layer is formed on the first dielectric layer through the first seed layer, and a fourth electroplating layer is formed on the second dielectric layer through the second seed layer.
[0109] In this embodiment, the exposed first seed layer and the second seed layer are usually contacted with the electroplating solution, and the exposed first seed layer and the second seed layer are used as electroplating cathodes in the electroplating process. The metal ions in the electroplating solution are reduced to metal atoms after obtaining electrons at the positions of the first seed layer and the second seed layer, and are deposited on the first seed layer and the second seed layer to form a third electroplating layer and a fourth electroplating layer.
[0110] Then, the third electroplating layer and the fourth electroplating layer are patterned to form wiring, thereby obtaining a chip packaging structure.
[0111] In this embodiment, the desired wiring pattern is formed by uniformly coating the third electroplating layer and the fourth electroplating layer with photoresist, and then performing exposure and development by photolithography technology. Finally, the third electroplating layer and the fourth electroplating layer not protected by the photoresist and the corresponding first seed layer and second seed layer can be removed by etching process to form wiring.
[0112] Furthermore, step S180 can also be implemented in the following manner.
[0113] Routing units are made based on the first seed layer and the second seed layer respectively. The routing units are arranged at equal intervals on the side of the first seed layer away from the first redistribution layer and the side of the second seed layer away from the second redistribution layer to form routing to obtain a chip packaging structure.
[0114] Further, step S130 may be implemented in the following manner.
[0115] A first seed layer and a second seed layer are respectively formed on the side of the first separable adhesive layer and the second separable adhesive layer away from the substrate by physical vapor deposition.
[0116] In this embodiment, the first seed layer and the second seed layer may be formed on the side of the first removable adhesive layer and the second removable adhesive layer away from the substrate by chemical vapor deposition (CVD).
[0117] Based on the same inventive concept, another object of the present application is to provide a chip packaging structure, which is prepared by any of the aforementioned chip packaging structure preparation methods. The chip packaging structure preparation method can reduce the warping phenomenon of the substrate 1, improve the reliability and product yield of the chip packaging structure, and increase the production capacity of the chip packaging structure.
[0118] In summary, the present application provides a method for preparing a chip packaging structure and a chip packaging structure. First, a substrate is provided, and a first detachable adhesive layer and a second detachable adhesive layer are respectively made on opposite sides of the substrate. Then, a first seed layer and a second seed layer are respectively made on the first detachable adhesive layer and the second detachable adhesive layer. Next, a first redistribution layer is made on the first seed layer, and a second redistribution layer is made on the second seed layer. Next, at least one chip is arranged on the first redistribution layer and the second redistribution layer, respectively. Then, a plastic sealing layer for at least encapsulating the chip is made, the first detachable adhesive layer and the second detachable adhesive layer are removed, and the substrate and the first seed layer and the second seed layer are separated. Finally, routing is made based on the first seed layer and the second seed layer, respectively, to obtain a chip packaging structure. The above scheme manufactures the chip packaging structure on both sides of the substrate at the same time, which not only reduces the warping phenomenon of the substrate, but also improves the production efficiency of the chip packaging structure.
[0119] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A method for preparing a chip packaging structure, characterized in that: The method comprises: providing a substrate; Forming a first separable adhesive layer and a second separable adhesive layer on opposite sides of the substrate respectively; Forming a first seed layer and a second seed layer respectively on the side of the first removable adhesive layer and the second removable adhesive layer away from the substrate; Forming a first redistribution layer on a side of the first seed layer away from the substrate, and forming a second redistribution layer on a side of the second seed layer away from the substrate; Disposing at least one chip on a side of the first redistribution layer and a side of the second redistribution layer away from the substrate respectively; Making a plastic packaging layer that at least encapsulates the chip; removing the first separable adhesive layer and the second separable adhesive layer, and separating the substrate from the first seed layer and the second seed layer; Routing is fabricated based on the first seed layer and the second seed layer respectively to obtain a chip packaging structure.
2. The method for preparing a chip packaging structure according to claim 1, characterized in that: In the step of forming a first redistribution layer on a side of the first seed layer away from the substrate, and forming a second redistribution layer on a side of the second seed layer away from the substrate, the method comprises: Forming a first dielectric layer on a side of the first seed layer away from the substrate, and forming a second dielectric layer on a side of the second seed layer away from the substrate; Making a first through hole penetrating the first dielectric layer on the first dielectric layer, and making a second through hole penetrating the second dielectric layer on the second dielectric layer; A first wiring layer is fabricated on a side of the first dielectric layer away from the substrate, and a second wiring layer is fabricated on a side of the second dielectric layer away from the substrate, wherein the first wiring layer includes wirings filling the first through holes, and the second wiring layer includes wirings filling the second through holes; Repeat the steps of alternately forming a first dielectric layer and a first routing layer on a side of the first routing layer away from the substrate to obtain the first redistribution layer, and alternately forming a second dielectric layer and a second routing layer on a side of the second routing layer away from the substrate to obtain the second redistribution layer.
3. The method for preparing a chip packaging structure according to claim 2, characterized in that: In the step of manufacturing a first wiring layer on a side of the first dielectric layer away from the substrate, and manufacturing a second wiring layer on a side of the second dielectric layer away from the substrate, the method comprises: forming a third seed layer on the first dielectric layer after forming the first through hole, and forming a fourth seed layer on the second dielectric layer after forming the second through hole; Forming a first photoresist layer on a side of the third seed layer and a side of the fourth seed layer away from the substrate respectively; Performing patterning on the first photoresist layer to form a first photoresist layer window exposing a portion of the third seed layer and the fourth seed layer; The third seed layer exposed through the first photoresist layer window generates a first wiring layer, and the fourth seed layer exposed through the first photoresist layer window generates a second wiring layer.
4. The method for preparing a chip packaging structure according to claim 2, characterized in that: In the step of manufacturing a first wiring layer on a side of the first dielectric layer away from the substrate, and manufacturing a second wiring layer on a side of the second dielectric layer away from the substrate, the method comprises: forming a third seed layer on the first dielectric layer after forming the first through hole, and forming a fourth seed layer on the second dielectric layer after forming the second through hole; forming a first electroplating layer on the first dielectric layer through the third seed layer, and forming a second electroplating layer on the second dielectric layer through the fourth seed layer; The first electroplating layer is patterned to obtain a first wiring layer, and the second electroplating layer is patterned to obtain a second wiring layer.
5. The method for preparing a chip packaging structure according to claim 2, characterized in that: The steps of making a first through hole penetrating the first dielectric layer on the first dielectric layer, and making a second through hole penetrating the second dielectric layer on the second dielectric layer include: Making a first through hole penetrating through the first dielectric layer on the first dielectric layer; A second through hole penetrating the second dielectric layer is formed on the second dielectric layer, and the second through hole is arranged in a staggered manner with the first through hole.
6. The method for preparing a chip packaging structure according to claim 2, characterized in that: In the step of respectively making routings based on the first seed layer and the second seed layer to obtain a chip packaging structure, the method includes: Forming a second photoresist layer on the first seed layer and the second seed layer respectively on a side away from the first dielectric layer and the second dielectric layer; Performing patterning on the second photoresist layer to form a second photoresist layer window exposing a portion of the first seed layer and the second seed layer; The first seed layer and the second seed layer exposed through the second photoresist layer window form wiring to obtain a chip packaging structure.
7. The method for preparing a chip packaging structure according to claim 2, characterized in that: In the step of respectively making routings based on the first seed layer and the second seed layer to obtain a chip packaging structure, the method includes: forming a third electroplating layer on the first dielectric layer through the first seed layer, and forming a fourth electroplating layer on the second dielectric layer through the second seed layer; The third electroplating layer and the fourth electroplating layer are patterned to form wiring, thereby obtaining a chip packaging structure.
8. The method for preparing a chip packaging structure according to claim 1, characterized in that: In the step of respectively making routings based on the first seed layer and the second seed layer to obtain a chip packaging structure, the method includes: Routing units are made based on the first seed layer and the second seed layer respectively. The routing units are arranged at equal intervals on a side of the first seed layer away from the first redistribution layer and a side of the second seed layer away from the second redistribution layer to form routing to obtain a chip packaging structure.
9. The method for preparing a chip packaging structure according to claim 1, characterized in that: In the step of respectively forming a first seed layer and a second seed layer on the side of the first separable adhesive layer and the second separable adhesive layer away from the substrate, the method includes: A first seed layer and a second seed layer are respectively formed on the side of the first separable adhesive layer and the second separable adhesive layer away from the substrate by physical vapor deposition.
10. A chip packaging structure, characterized in that: The chip packaging structure is prepared by the chip packaging structure preparation method according to claims 1-9.