Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device and a method of manufacture are provided, wherein the semiconductor device is connected over a semiconductor substrate. A sealing ring in the semiconductor device extends to include a first bonding metal in the bonding layer, and is bonded to a second bonding metal over the semiconductor substrate. Such a sealing ring provides more complete protection against cracks and delamination.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this increase in integration density comes from iterative reductions in minimum feature size (e.g., shrinking semiconductor process nodes toward nodes below 20nm), which allows more components to be integrated into a given area. With the recent growing demand for miniaturization, higher speeds and greater bandwidth, as well as lower power consumption and latency, the demand for smaller and more innovative semiconductor die packaging technologies is also growing.

[0003] As semiconductor technology has further developed, stacked and bonded semiconductor devices have become an effective alternative to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, processor circuits, etc. are at least partially manufactured on separate substrates and then physically and electrically bonded together to form functional devices. This bonding process uses complex technology and therefore needs to be improved. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, the method comprising: receiving a first semiconductor device, the first semiconductor device comprising: a functional area; and a sealing ring area, the sealing ring area comprising a first sealing ring; bonding the first semiconductor device to a semiconductor wafer, the bonding comprising: bonding a first dielectric of the first semiconductor device to a second dielectric of the semiconductor wafer; bonding a first bonding pad within the functional area to a second bonding pad within the semiconductor wafer; and bonding the first sealing ring to a first bonding metal within the semiconductor wafer.

[0005] According to another aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, the method comprising: receiving a semiconductor substrate, the semiconductor substrate comprising a functional area and a sealing ring area; manufacturing a first metallization layer, the first metallization layer comprising a first portion within the functional area and a second portion within the sealing ring area, the first portion being separated from the second portion; forming a first bonding layer, the formation of the first bonding layer comprising: forming a first bonding pad within the functional area; and forming a first bonding metal within the sealing ring area, the first bonding metal and the second portion of the first metallization layer forming a first sealing ring; and bonding the first bonding metal to the second bonding metal within the semiconductor wafer.

[0006] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a first semiconductor die, the first semiconductor die comprising: an active device located in a functional area of ​​the first semiconductor die; a first metallization layer, the first metallization layer comprising: a first portion electrically connected to the active device; and a second portion forming a first component of a sealing ring surrounding the functional area; a first bonding layer, the first bonding layer comprising: a first bonding pad electrically connected to the first portion of the first metallization layer; a first bonding metal forming a second component of a sealing ring surrounding the functional area; and a second semiconductor die, the second semiconductor die comprising: a second bonding pad bonded to the first bonding pad; and a second bonding metal bonded to the sealing ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 shows a semiconductor wafer according to some embodiments;

[0009] Figure 2A-2B illustrates a semiconductor die having a seal ring according to some embodiments;

[0010] Figure 3 illustrates bonding of a semiconductor die to a semiconductor wafer according to some embodiments;

[0011] Figure 4 illustrates encapsulation of a semiconductor die according to some embodiments;

[0012] Figure 5 illustrates thinning of a semiconductor wafer according to some embodiments;

[0013] Figure 6 illustrates the formation of a redistribution structure according to some embodiments;

[0014] Figure 7-Figure 9 Various embodiments of sealing rings according to some embodiments are shown;

[0015] Fig.10 A face-to-back configuration is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] Embodiments will now be described with respect to specific embodiments in which devices within a system on an integrated circuit (SoIC) utilize seal rings extending into respective bonding layers of the various devices. However, the embodiments shown herein are intended only to illustrate the embodiments and are not intended to limit the embodiments. Rather, the concepts presented herein may be incorporated into a wide variety of embodiments, and all such embodiments are fully intended to be included within the scope of the embodiments.

[0019] Reference now Figure 1 , showing a semiconductor wafer 100, having a plurality of first semiconductor devices 101 ( Figure 1 Only one of them is shown in FIG. 1 ). In a specific embodiment, the first semiconductor device 101 may be a memory device, such as a wide I / O dynamic random access memory (DRAM) device having a large number of I / O interfaces (e.g., greater than 256 interfaces). However, the first semiconductor device 101 may also be any other suitable type of memory device with a high data transfer rate, such as an LPDDRn memory device with a high data transfer rate, or may be any other suitable device, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination of these, etc. In addition, the semiconductor wafer 100 may be received by the manufacturer from a third-party manufacturer, or may be manufactured internally.

[0020] In one embodiment, the first semiconductor device 101 may include a first substrate 103, a first active device ( Figure 1 10, a first metallization layer 105, a first bonding layer 109, a first dielectric material 110, a first bonding pad 107, and a first bonding metal 113. The first substrate 103 may include doped or undoped bulk silicon, or an active layer of a silicon-on-insulator (SOI) substrate. Typically, the SOI substrate includes a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid directional substrates.

[0021] The first active devices include various active devices such as transistors, and passive devices such as capacitors, resistors, inductors, etc., which can be used to generate the desired structural and functional requirements for the design of the first semiconductor device 101. The first active devices can be formed in or on the first substrate 103 using any suitable method.

[0022] The first metallization layer 105 is formed over the first substrate 103 and the first active device, and is designed to connect the various active devices to form a functional circuit. In one embodiment, the first metallization layer 105 is formed of alternating layers of dielectric material (e.g., low-k dielectric material, very low-k dielectric material, ultra-low-k dielectric material, combinations thereof, etc.) and conductive material, and may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In one embodiment, there may be four metallization layers separated from the first substrate 103 by at least one interlayer dielectric layer (ILD), but the exact number of first metallization layers 105 depends on the design of the first semiconductor device 101.

[0023] In addition, at any desired point in the manufacturing process, through-substrate vias 111 may be formed in the first substrate 103, and if desired, in one or more layers of the first metallization layer 105, to provide electrical connections from the front side of the first substrate 103 to the back side of the first substrate 103. In one embodiment, the TSVs 111 may be formed by initially forming through-silicon via (TSV) openings in the first substrate 103, and if desired, in any overlying first metallization layer 105 (e.g., after the desired first metallization layer 105 has been formed, but before the next overlying first metallization layer 105 is formed). The TSV openings may be formed by applying and developing a suitable photoresist, and removing portions of the underlying material exposed to a desired depth. The TSV openings may be formed to extend into the first substrate 103 to a depth greater than the final desired height of the first substrate 103. Accordingly, the depth may be between about 20 μm and about 200 μm, such as a depth of about 50 μm, although the depth depends on the overall design.

[0024] Once the TSV openings are formed in the first substrate 103 and / or any first metallization layer 105, the TSV openings may be lined with a liner. The liner may be an oxide formed, for example, from tetraethyl orthosilicate (TEOS) or silicon nitride, although any suitable dielectric material may be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other suitable processes, such as physical vapor deposition or thermal processes, may also be used. Additionally, the liner may be formed to a thickness between about 0.1 μm and about 5 μm, for example about 1 μm.

[0025] Once the liner is formed along the sidewalls and bottom of the TSV opening, a barrier layer can be formed and the remaining portion of the TSV opening can be filled with a first conductive material. The first conductive material can include copper, although other suitable materials can be used, such as aluminum, alloys, doped polysilicon, combinations thereof, etc. The first conductive material can be formed by electroplating copper on the seed layer, filling and overfilling the TSV opening. Once the TSV opening is filled, the excess liner, barrier layer, seed layer, and first conductive material outside the TSV opening can be removed by a planarization process such as chemical mechanical polishing (CMP), although any suitable removal process can be used.

[0026] A first bonding layer 109 may be formed on the first substrate 103 above the first metallization layer 105. The first bonding layer 109 may be used for dielectric-to-dielectric and metal-to-metal bonding, or fusion bonding (also referred to as oxide-to-oxide bonding). According to some embodiments, the first bonding layer 109 is formed of a first dielectric material 110 such as silicon oxide, silicon nitride, etc. The first dielectric material 110 may be deposited to a thickness between about 1 nm and about 1000 nm, for example, about 5 nm, using any suitable method, such as atomic layer deposition (ALD), CVD, high density plasma chemical vapor deposition (HDPCVD), PVD, etc. However, any suitable material, process, and thickness may be used.

[0027] Once the first dielectric material 110 is formed, a bonding opening can be formed in the first dielectric material 110 in preparation for forming the first bonding pad 107 and the first bonding metal 113. In one embodiment, the bonding opening can be formed by first applying and patterning a photoresist over the top surface of the first dielectric material 110. The photoresist is then used to etch the first bonding layer 109 to form an opening. The first bonding layer 109 can be etched by dry etching (e.g., reactive ion etching (RIE) or neutral beam etching (NBE)), wet etching, etc. According to some embodiments of the present invention, etching is stopped on the first metallization layer 105 so that the first metallization layer 105 is exposed through the opening in the first bonding layer 109.

[0028] Once the first metallization layer 105 is exposed, the first bonding pad 107 can be formed to physically and electrically contact the first metallization layer 105. In one embodiment, the first bonding pad 107 may include a barrier layer, a seed layer, a filler metal, or a combination thereof (not shown separately). For example, the barrier layer may be blanket deposited over the first metallization layer 105. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The seed layer may be a conductive material such as copper, and may be blanket deposited over the barrier layer using processes such as sputtering, evaporation, or plasma enhanced chemical vapor deposition (PECVD) depending on the desired material. The filler metal may be a conductor such as copper or a copper alloy, and may be deposited over the seed layer to fill or overfill the opening by a plating process such as electroplating or electroless plating. Once the filler metal is deposited, the excess material of the filler metal, the seed layer, and the barrier layer may be removed from the outside of the opening by a planarization process such as chemical mechanical polishing. However, although a single damascene process is described, any suitable method such as a dual damascene process may also be used.

[0029] Additionally, in some embodiments, a bonding pad via ( Figure 1The first bonding pad 107 is connected to the underlying conductive portion (not separately shown), and through the underlying conductive portion, the first bonding pad 107 is connected to the underlying first metallization layer 105. In this embodiment, the bonding pad via can be formed before the first bonding pad 107 or simultaneously with the first bonding pad 107, for example, by using a damascene or dual damascene process. However, any suitable method and material may be used.

[0030] Finally, within the first bonding layer 109, a first bonding metal 113 may be fabricated. In one embodiment, the first bonding metal 113 may be fabricated using similar materials and processes as the first bonding pad 107, and may be implemented simultaneously or sequentially with the first bonding pad 107. During the fabrication of the first bonding metal 113, a first bonding metal via ( Figure 1 However, any suitable materials and processes may be used.

[0031] However, the above-described embodiments in which the first bonding layer 109 is formed, patterned, and the first bonding pad 107 and the first bonding metal 113 are plated into the opening before planarization are intended to illustrate, but not to limit, the embodiments. Instead, any suitable method of forming the first bonding layer 109, the first bonding pad 107, and the first bonding metal 113 may be used. In other embodiments, the first bonding pad 107 and the first bonding metal 113 may be formed by first using, for example, a photolithography patterning and plating process, and then using a dielectric material to gap fill the area around the first bonding pad 107 and the first bonding metal 113 before planarization using a planarization process. Any such manufacturing process is fully intended to be included within the scope of the embodiments.

[0032] Figure 2A The second semiconductor device 201 to be bonded to the first bonding layer 109 is shown. Figure 2A The joining is not shown in FIG, but is described below with respect to Figure 3 In one embodiment, the second semiconductor device 201 may be a system-on-chip device, such as a logic device, which is intended to work in conjunction with the first semiconductor device 101 (e.g., a wide I / O DRAM device). However, any suitable functionality may be used, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination thereof, etc.

[0033] In one embodiment, the second semiconductor device 201 may have a second substrate 203, a second active device (not shown separately), a second metallization layer 205, a second bonding layer 207, a second dielectric layer 210, a second pad 209, a second bonding metal 211, and a second bonding metal through hole 213. In one embodiment, the second substrate 203, the second active device, the second metallization layer 205, the second bonding layer 207, the second bonding pad 209, the second bonding metal 211, and the second bonding metal through hole 213 may be formed similar to the above description of Figure 1 The first substrate 103, the first active device, the first metallization layer 105, the first bonding layer 109, the first bonding pad 107, the first bonding metal 113, and the first bonding metal via are described. However, in other embodiments, different processes and different materials may be used to form these structures.

[0034] Figure 2A It is also shown that in some embodiments, the second semiconductor device 201 may have a functional region 221 surrounded by a closed-loop seal ring region 223. In particular, and looking first at the functional region 221, the first active device, the second metallization layer 205, and the second bonding pad 209 are interconnected to provide the desired functionality of the second semiconductor device 201 without relying on any device of the second semiconductor device 201 outside the functional region 221, or even being electrically connected to any device of the second semiconductor device 201 outside the functional region 221.

[0035] The seal ring area 223 is located outside the functional area 221 and is used to place a first seal ring 225 located near the edge of the second semiconductor device 201. In some embodiments, the first seal ring 225 includes a second metallization layer 205, a second bonding metal via 213, and a portion of the second bonding metal 211. The second metallization layer 205, the second bonding metal via 213, and the portion of the second bonding metal 211 located within the seal ring area 223 collectively form a ring around the functional area 221 (in a top view) and help provide protection for the functional area 221 during subsequent processing and operation.

[0036] Figure 2B A top view of the seal ring region 223 is shown, wherein the second bonding metal 211 and the second bonding metal via 213 (in Figure 2B (Observed through the dotted line in the second bonding metal 211, because the second bonding metal through hole 213 is located below the second bonding metal 211) surrounds the functional area 221. Figure 2B As can be observed in FIG. 1 , in some embodiments, the first sealing ring 225 can be formed in an octagonal pattern.

[0037] In a particular embodiment, the octagonal pattern includes extended edges 215 and inclined edges 217 connecting different extended edges 215. In this embodiment, the extended edges 215 extend parallel to the edges of the functional area 221, while the inclined edges 217 connect different extended edges 215 and are located near the corners of the functional area 221, where cracks are more likely to occur. In some embodiments, the inclined edges 217 can be arranged to have a first angle θ1 between about 0° and about 90°, for example, about 45°. However, any suitable arrangement can be used.

[0038] Of course, although in Figure 2B In the embodiment shown in , the first sealing ring 225 can be formed in an octagon, but this is intended to illustrate the embodiment and is not intended to limit the embodiment to a precise octagon as described above. Instead, the first sealing ring 225 can be formed in any suitable shape, such as by having more than one inclined edge arranged at each corner. All such shapes are fully intended to be included within the scope of the embodiments.

[0039] Figure 3 As shown, once the second semiconductor device 201 is prepared, the second semiconductor device 201 is bonded to the first semiconductor device 101 (still in wafer form) using, for example, dielectric-to-dielectric and metal-to-metal bonding. In one embodiment, the surface of the first semiconductor device 101 (e.g., the first dielectric material 110, the first bonding pad 107, and the first bonding metal 113) and the surface of the second semiconductor device 201 (e.g., the second dielectric layer 210, the second bonding pad 209, and the second bonding metal 211) can be initially activated. As an example, activating the top surfaces of the first semiconductor device 101 and the second semiconductor device 201 can include dry processing, wet processing, plasma processing, exposure to an inert gas plasma, exposure to H2, exposure to N2, exposure to O2, or a combination thereof. In an embodiment using wet processing, for example, RCA cleaning can be used. In another embodiment, the activation process can include other types of processing. The activation process facilitates dielectric-to-dielectric and metal-to-metal bonding of the first semiconductor device 101 and the second semiconductor device 201.

[0040] After the activation process, the second semiconductor device 201 may be placed in contact with the first semiconductor device 101. In a specific embodiment where dielectric-to-dielectric and metal-to-metal bonding is used, the first bonding pad 107 is placed in physical contact with the second bonding pad 209, the first dielectric material 110 is placed in physical contact with the second dielectric layer 210, and the first bonding metal 113 is placed in contact with the second bonding metal 211. The bonding process between the materials begins when they are in physical contact by chemically modifying the surfaces through the activation process.

[0041] Once the physical contact begins the bonding process, the bond can be strengthened by subjecting the assembly to a heat treatment. In one embodiment, the first semiconductor device 101 and the second semiconductor device 201 can be subjected to a temperature between about 200° C. and about 400° C. to strengthen the bond between the first bonding layer 109 and the second bonding layer 207. The first semiconductor device 101 and the second semiconductor device 201 can then be subjected to a temperature at or above the eutectic point of the materials of the first bonding pad 107, the second bonding pad 209, the first bonding metal 113, and the second bonding metal 211. In this manner, the melting of the first semiconductor device 101 and the second semiconductor device 201 forms a hybrid bonded device.

[0042] In addition, although specific processes for initializing and strengthening the dielectric-to-dielectric and metal-to-metal bonding between the first semiconductor device 101 and the second semiconductor device 201 are described, these descriptions are intended to illustrate, but not to limit, the embodiments. Instead, any suitable combination of baking, annealing, pressing, or other bonding processes or combinations of processes may be used. All such processes are fully intended to be included within the scope of the embodiments.

[0043] In addition, although dielectric-to-dielectric and metal-to-metal bonding are described as a method of bonding the first semiconductor device 101 to the second semiconductor device 201, this is only intended to illustrate and is not intended to limit the embodiments. Instead, any suitable bonding method may be used, such as fusion bonding, copper-to-copper bonding, etc. Any suitable method of bonding the first semiconductor device 101 to the second semiconductor device 201 may be used.

[0044] Figure 4 4 shows that once the second semiconductor device 201 is bonded to the first semiconductor device 101, the second semiconductor device 201 can be sealed above the first semiconductor device 101 using a first sealant 401. In one embodiment, the sealing can be implemented in a molding device, which can include a top molding portion and a bottom molding portion that is separable from the top molding portion. When the top molding portion is lowered to abut against the bottom molding portion, a molding cavity for the first semiconductor device 101 and the second semiconductor device 201 can be formed.

[0045] During the sealing process, the top molded portion can be placed adjacent to the bottom molded portion, thereby enclosing the first semiconductor device 101 and the second semiconductor device 201 within the molding cavity. Once enclosed, the top molded portion and the bottom molded portion can form a hermetic seal to control the inflow and outflow of gas from the molding cavity. Once sealed, a first sealant 401 can be placed within the molding cavity.

[0046] The first sealant 401 may be an epoxy resin or a molding compound resin, such as polyimide, polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polyethersulfone (PES), a heat-resistant crystal resin, a combination thereof, etc. The first sealant 401 may be placed in the molding cavity before the top molding portion and the bottom molding portion are aligned, or may be injected into the molding cavity through an injection port using compression molding, transfer molding, etc.

[0047] Once the first sealant 401 is placed into the mold cavity so that the first sealant 401 seals the second semiconductor device 201, the first sealant 401 can be cured to harden the first sealant 401 for optimal protection. Although the exact curing process depends at least in part on the specific material selected for the first sealant 401, in embodiments where a molding compound is selected as the first sealant 401, the first sealant 401 can be cured by, for example, heating the first sealant 401 to a temperature of about 100° C. to about 200° C., such as about 125° C., for about 60 seconds to about 3000 seconds, such as about 600 seconds. In addition, an initiator and / or catalyst can be included in the first sealant 401 to better control the curing process.

[0048] However, as will be appreciated by one of ordinary skill in the art, the curing process described above is merely an exemplary process and is not meant to limit the current embodiments. Other curing processes may also be used, such as irradiation or even allowing the first sealant 401 to harden at ambient temperature. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.

[0049] Figure 4 Also shown is the thinning of the first encapsulant 401 to expose the second semiconductor device 201 for further processing. The thinning can be performed, for example, using mechanical grinding, chemical methods, or a chemical mechanical polishing (CMP) process, in which a chemical etchant and an abrasive are used to react and grind away the first encapsulant 401, thereby exposing the second semiconductor device 201. In this way, the second semiconductor device 201 can have a flat surface that is also coplanar with the first encapsulant 401. In another embodiment, grinding can be omitted. For example, if the second semiconductor device 201 is already exposed after sealing, or if it is desired that the first encapsulant 401 remain above the second semiconductor device 201, grinding can be omitted.

[0050] In addition, although the CMP process described above is presented as an illustrative embodiment, it is not intended to limit these embodiments. Any other suitable removal process can be used to thin the first sealant 401. For example, a series of chemical etching can be used. This process and any other suitable process can be used to planarize the first sealant 401, and all such processes are fully intended to be included in the scope of the embodiments.

[0051] Figure 5 Thinning of the back side of the first substrate 103 is shown to expose the TSVs 111. In one embodiment, thinning of the second side of the first substrate 103 may expose the TSVs 111. The thinning of the second side of the first substrate 103 may be performed by a planarization process such as CMP or etching. However, any suitable method of thinning the second side of the first substrate 103 may be implemented.

[0052] Figure 6 The formation of a redistribution structure 601 having one or more layers over the second side of the first substrate 103 and connected to the TSVs 111 is shown. In one embodiment, the redistribution structure 601 may be formed by initially forming a first redistribution layer 603 over the TSVs 111 and electrically connected to the TSVs 111. In one embodiment, the first redistribution layer 603 may be formed by initially forming a seed layer (not shown) of a titanium-copper alloy by a suitable formation process such as CVD or sputtering. A photoresist (also not shown) may then be formed to cover the seed layer, and the photoresist may then be patterned to expose those portions of the seed layer that are located where the first redistribution layer 603 is desired to be located.

[0053] Once the photoresist is formed and patterned, a conductive material such as copper may be formed on the seed layer by a deposition process such as plating. The conductive material may be formed to have a thickness between about 1 μm and about 10 μm, for example, about 4 μm. However, while the materials and methods discussed are suitable for forming the conductive material, these materials are merely exemplary. The first redistribution layer 603 may be formed using any other suitable material such as AlCu or Au, and any other suitable formation process such as CVD or PVD.

[0054] Once the conductive material is formed, the photoresist can be removed by a suitable removal process such as chemical stripping and / or ashing. In addition, after removing the photoresist, those portions of the seed layer covered by the photoresist can be removed by a suitable etching process such as using the conductive material as a mask.

[0055] Once the first redistribution layer 603 is formed, a redistribution passivation layer may be formed. In one embodiment, the redistribution passivation layer may be polybenzoxazole (PBO), although any suitable material may alternatively be used, such as polyimide or a polyimide derivative, such as a low temperature cured polyimide. The redistribution passivation layer may be placed to a thickness of between about 5 μm and about 17 μm, such as about 7 μm, using, for example, a spin coating process, although any suitable method and thickness may be used.

[0056] Once the redistribution passivation layer is formed, the redistribution passivation layer can be patterned to allow electrical contact to the underlying first redistribution layer 603. In one embodiment, the redistribution passivation layer can be patterned using, for example, a photolithography mask and an etching process. However, any suitable process can be used to expose the underlying first redistribution layer 603.

[0057] After patterning the redistribution passivation layer, additional layers of the first redistribution layer 603 and redistribution passivation layer may be formed, if desired, to provide additional interconnect options. In particular, any suitable number of conductive layers and dielectric layers may be formed using the processes and materials described herein. All such layers are fully intended to be included within the scope of the embodiments.

[0058] Once the redistribution passivation layer is formed and patterned, the first external connector 607 can be formed. In one embodiment, the first external connector 607 can be, for example, a ball grid array (BGA) with C4 bumps, which includes a eutectic material such as solder, although any suitable material can be used. In an embodiment in which the first external connector 607 is a solder bump, a ball drop method such as a direct ball drop process can be used to form the first external connector 607. In another embodiment, the solder bump can be formed by initially forming a tin layer by any suitable method such as evaporation, electroplating, printing, solder transfer, and then reflowing to shape the material into the desired bump shape. Once the first external connector 607 is formed, testing can be performed to ensure that the structure is suitable for further processing.

[0059] Figure 6 Additionally shown is the singulation of the remaining portion of the first encapsulant 401 and the first semiconductor device 101 from the semiconductor wafer 100. In one embodiment, singulation can be performed by slicing through the first encapsulant 401 and the semiconductor wafer 100 using a saw blade (not separately shown). However, as one of ordinary skill in the art will recognize, slicing using a saw blade is merely an illustrative embodiment and is not intended to be limiting. Any method for performing singulation can be used, such as using one or more etches. These methods and any other suitable methods can be used to singulate the structure.

[0060] Figure 7 2 shows a top view of another embodiment, in which the second sealing ring 701 includes the first sealing ring 225 and the surrounding outer ring 703. In this embodiment, the second sealing ring 701 can be as described above. Figure 2A-2B The first sealing ring 225 is formed as described. However, any suitable method and material may be used.

[0061] Regarding the surrounding outer ring 703, the outer ring 703 can be formed to surround the first sealing ring 225 and provide more protection for the functional area 221. In some embodiments, the outer ring 703 can be formed using similar materials and methods as the first sealing ring 225, and can have an octagonal shape. In addition, although the outer ring 703 can be formed in multiple levels (similar to the first sealing ring 225), in other embodiments, the outer ring 703 can be formed at the same level as the second bonding metal 211 without additional levels (e.g., without the following through hole). However, any suitable method, material, and shape can be used.

[0062] Figure 8 2 shows a top view of another embodiment in which an additional beveled edge 801 is added to the first sealing ring 225. In this embodiment, the additional beveled edge 801 can be formed at the same level as the remaining portion of the first sealing ring 225 and provide additional protection along the corners of the functional area 221. In addition, although Figure 8 A single additional sloped edge 801 is shown at each corner, but any suitable number of additional sloped edges 801 such as 2, 3, or 4 may be formed near each corner, and any suitable number may be used.

[0063] Fig. 9 A top view of another embodiment is shown, in which the first sealing ring 225 is not octagonal (as described above with respect to Figure 1-Figure 8 221 ), but rather a square or rectangular shape. In this embodiment, there are no angled edges at the corners of the functional area 221, and the first sealing ring 225 has a total of four edges. However, any suitable number of edges and any suitable shape may be used.

[0064] Fig.10 Another embodiment is shown in which the second semiconductor device 201 is bonded to the third semiconductor device 1001 in, for example, a face-to-back configuration. In this embodiment, the second semiconductor device 201 may be as described above with respect to Figure 2A 1003, but may further include a second TSV 1003 extending through the second substrate 203. In some embodiments, similar methods and materials as TSV 111 may be used (described above with respect to Figure 1 and Figure 5 ), to form the second TSV 1003. However, any suitable method and material may be used.

[0065] Once the second semiconductor device 201 is prepared, the second semiconductor device 201 can be connected to the carrier wafer 1004, and the second semiconductor device 201 can be sealed using the first sealant 401. In one embodiment, an adhesive layer ( Fig.10 ), or other components that can be bonded to the carrier wafer 1004, to connect the second semiconductor device 201. In addition, the second semiconductor device 201 can be connected as described above. Figure 4 As described above (placing the first encapsulant 401 and then planarizing the first encapsulant 401 until the second TSV 1003 is exposed or re-exposed), the second semiconductor device 201 is encapsulated with the first encapsulant 401. However, any suitable method and material may be used.

[0066] Once the second semiconductor device 201 is connected and sealed, a third bonding layer 1005 may be formed over the second semiconductor device 201 and the first sealant 401. In one embodiment, the third bonding layer 1005 may include a fifth bonding pad 1007 and a third bonding metal 1009, which may be used as described above with respect to Figure 1 The first bonding layer 109, the first bonding pad 107, and the first bonding metal 113 are made using similar processes and materials as described above. However, any suitable materials and processes may be used.

[0067] Once the third bonding layer 1005 is formed, the third semiconductor device 1001 may be bonded to the third bonding layer 1005. In one embodiment, the third semiconductor device 1001 may have a similar structure to the second semiconductor device 201, but may or may not have a different design to provide functionality that works in conjunction with the second semiconductor device 201. Thus, the third semiconductor device 1001 may have a second substrate 203, a second metallization layer 205, a second bonding layer 207, and a second TSV 1003. In addition, for example, as described above with respect to Figure 3 The dielectric-to-dielectric and metal-to-metal bonding processes described bond the third semiconductor device 1001 to the third bonding layer 1005. However, any suitable device, structure, and method may be used.

[0068] Once the third semiconductor device 1001 is bonded to the third bonding layer 1005, the third semiconductor device 1001 may be sealed with a second sealant 1011. In one embodiment, the third semiconductor device 1001 may be sealed as described above with respect to Figure 4 As discussed above, the third semiconductor device 1001 is sealed. However, any suitable methods and materials may be used.

[0069] Once the second encapsulant 1011 is placed and planarized, a redistribution structure 601 may be formed that is in electrical contact with the second TSV 1003 in the third semiconductor device 1001. In one embodiment, the redistribution structure 601 may be formed as described above with respect to Figure 6 The redistribution structure 601 and the first external connector 607 are formed as described. However, any suitable methods and materials may be used.

[0070] By forming the first sealing ring 225 to include the second bonding metal 211 and the second bonding metal via 213, the first sealing ring 225 can be connected to the first bonding metal 113, thereby forming a continuous closed loop of a ring of material extending from the second semiconductor device 201 to the semiconductor wafer 100. In this way, a closed loop is formed, which helps prevent delamination of the bonding interface and prevents any cracks (e.g., from thermal mismatch stress) from extending into the functional area 221. This protection also helps provide a strong metal-to-metal (e.g., Cu-to-Cu) bond. Such an improvement can be formed simultaneously with the rest of the bonding layer and therefore does not involve additional process steps.

[0071] According to one embodiment, a method for manufacturing a semiconductor device includes: receiving a first semiconductor device, the first semiconductor device including: a functional area; and a sealing ring area, the sealing ring area including a first sealing ring; bonding the first semiconductor device to a semiconductor wafer, the bonding including: bonding a first dielectric of the first semiconductor device to a second dielectric of the semiconductor wafer; bonding a first bonding pad in the functional area to a second bonding pad in the semiconductor wafer; and bonding the first sealing ring to a first bonding metal in the semiconductor wafer. In one embodiment, the first sealing ring completely surrounds the functional area. In one embodiment, the first sealing ring has an octagon. In one embodiment, the octagon includes a first inclined side positioned along a corner of the functional area. In one embodiment, the octagon includes a second inclined side positioned along a corner of the functional area. In one embodiment, the first sealing ring has a second octagon surrounding the octagon. In one embodiment, the first sealing ring has a square shape.

[0072] According to another embodiment, a method for manufacturing a semiconductor device includes: receiving a semiconductor substrate, the semiconductor substrate includes a functional area and a sealing ring area; manufacturing a first metallization layer, the first metallization layer includes a first portion in the functional area and a second portion in the sealing ring area, the first portion is separated from the second portion; forming a first bonding layer, the forming of the first bonding layer includes: forming a first bonding pad in the functional area; and forming a first bonding metal in the sealing ring area, the first bonding metal and the second portion of the first metallization layer forming a first sealing ring; and bonding the first bonding metal to the second bonding metal in the semiconductor wafer. In one embodiment, forming the first bonding layer also includes forming a first bonding via. In one embodiment, the first bonding metal has a first configuration and the second bonding metal has a first configuration. In one embodiment, the method also includes sealing the semiconductor substrate with a sealant. In one embodiment, the method also includes thinning the semiconductor wafer after bonding to expose the through-via. In one embodiment, the method also includes forming a first redistribution structure electrically connected to the through-via. In one embodiment, forming the first bonding metal forms the first bonding metal into an octagon.

[0073] In yet another embodiment, a semiconductor device includes: a first semiconductor die, the first semiconductor die includes: an active device, located in a functional area of ​​the first semiconductor die; a first metallization layer, the first metallization layer includes: a first portion, electrically connected to the active device; and a second portion, forming a first part of a sealing ring around the functional area; a first bonding layer, the first bonding layer includes: a first bonding pad, electrically connected to the first portion of the first metallization layer; a first bonding metal, forming a second part of a sealing ring around the functional area; and a second semiconductor die, the second semiconductor die includes: a second bonding pad, bonded to the first bonding pad; and a second bonding metal, bonded to the sealing ring. In one embodiment, the first bonding metal has an octagonal shape. In one embodiment, the semiconductor device also includes a third bonding metal surrounding the sealing ring. In one embodiment, the first bonding metal has a plurality of inclined sidewalls adjacent to the corners of the functional area. In one embodiment, the semiconductor device also includes an encapsulant surrounding the first semiconductor die and located above the second semiconductor die. In one embodiment, the first semiconductor die and the second semiconductor die are in a semiconductor-on-integrated circuit configuration.

[0074] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A first semiconductor device is received, the first semiconductor device comprising: Functional areas; and a sealing ring area, the sealing ring area comprising a first sealing ring; Bonding the first semiconductor device to a semiconductor wafer, the bonding comprising: bonding a first dielectric of the first semiconductor device to a second dielectric of the semiconductor wafer; bonding a first bonding pad within the functional area to a second bonding pad within the semiconductor wafer; and The first seal ring is bonded to a first bonding metal within the semiconductor wafer.

2. The method according to claim 1, wherein: The first sealing ring completely surrounds the functional area.

3. The method according to claim 1, wherein: The first sealing ring has an octagonal shape.

4. The method according to claim 3, wherein: The octagon includes a first sloped side located along a corner of the functional area.

5. The method according to claim 4, wherein: The octagon includes a second sloped side located along the corner of the functional area.

6. A method for manufacturing a semiconductor device, the method comprising: receiving a semiconductor substrate, the semiconductor substrate comprising a functional area and a seal ring area; manufacturing a first metallization layer, the first metallization layer comprising a first portion in the functional area and a second portion in the sealing ring area, the first portion being separated from the second portion; Forming a first bonding layer, the forming of the first bonding layer comprising: forming a first bonding pad within the functional area; and forming a first bonding metal in the seal ring area, the first bonding metal and the second portion of the first metallization layer forming a first seal ring; and The first bonding metal is bonded to a second bonding metal within a semiconductor wafer.

7. The method according to claim 6, wherein: The forming of the first bonding layer further includes forming a first bonding through-hole.

8. The method according to claim 6, wherein: The first bonding metal has a first configuration, and the second bonding metal has the first configuration.

9. The method of claim 6, further comprising sealing the semiconductor substrate with a sealant.

10. A semiconductor device comprising: A first semiconductor die, the first semiconductor die comprising: an active device located within a functional region of the first semiconductor die; A first metallization layer, the first metallization layer comprising: A first portion electrically connected to the active device; and a second part, forming a first component of a sealing ring around the functional area; A first bonding layer, the first bonding layer comprising: a first bonding pad electrically connected to the first portion of the first metallization layer; a first bonding metal forming a second portion of the sealing ring surrounding the functional area; and A second semiconductor die, the second semiconductor die comprising: a second bonding pad bonded to the first bonding pad; and A second bonding metal is bonded to the sealing ring.

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