Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate and a gate structure on the substrate; forming an interlayer dielectric layer on the substrate and the gate structure; etching the interlayer dielectric layer to form a trench within the interlayer dielectric layer, the trench being located at a corresponding position of the gate structure; forming a barrier structure within the trench; etching the interlayer dielectric layer and the barrier structure to form a first via and a second via, the first via being located on the gate structure and penetrating the barrier structure, and the second via being located on the substrate on at least one side of the gate structure, with the depth of the second via being greater than that of the first via. The barrier structure, located at the corresponding position of the gate structure, slows down the etching rate at the position corresponding to the first via, thereby effectively reducing the occurrence of over-etching at the position of the first via on the gate structure when the etching of the second via on the substrate is completed, reducing the probability of gate structure loss, and improving the performance stability of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Semiconductor integrated circuits are integrated on the same wafer, i.e., a semiconductor substrate, such as a silicon substrate. The doped regions of the devices in the integrated circuit on the wafer need to be brought out through contact holes and metal layers. The contact holes and metal layers form a metal interconnect structure. In semiconductor manufacturing processes, silicon contact hole etching mainly forms two types of structures: one is contact holes on polysilicon gates, and the other is contact holes on active regions (formed on electron / hole heavily doped silicon substrates).

[0003] However, the current methods for forming contact holes still need improvement. Summary of the Invention

[0004] The problem solved by this invention is how to improve the method of forming contact holes so that the contact holes on the active region are formed while the contact holes on the polysilicon gate are not over-etched.

[0005] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate and a gate structure located on the substrate; forming an interlayer dielectric layer on the substrate and the gate structure; etching the interlayer dielectric layer to form a groove within the interlayer dielectric layer, the groove being located at a corresponding position of the gate structure; forming a barrier structure within the groove; etching the interlayer dielectric layer and the barrier structure to form a first via and a second via, the first via being located on the gate structure and penetrating the barrier structure, the second via being located on the substrate on at least one side of the gate structure and having a depth greater than that of the first via.

[0006] Optionally, the width of the first through hole is not greater than the width of the blocking structure.

[0007] Optionally, in the step of etching the interlayer dielectric layer and the barrier structure to form the first via and the second via, the etching rate of the material of the interlayer dielectric layer is greater than the etching rate of the material of the barrier structure.

[0008] Optionally, the material of the interlayer dielectric layer is silicon oxide; the material of the barrier structure is silicon nitride.

[0009] Optionally, in the step of providing a substrate and a gate structure located on the substrate, the gate structure has a first height relative to the substrate; in the step of etching the interlayer dielectric layer and the barrier structure to form a first via and a second via, the etching rate of the material of the interlayer dielectric layer has a first ratio to the etching rate of the material of the barrier structure; in the step of forming the barrier structure in the groove, the thickness of the barrier structure is determined based on the first height and the first ratio.

[0010] Optionally, in the step of forming a blocking structure within the groove, the thickness of the blocking structure is the ratio of the first height to the first ratio.

[0011] Optionally, the step of forming a blocking structure within the groove includes: filling the groove with blocking material; and performing a planarization process to form a blocking structure located within the groove.

[0012] Optionally, the step of etching the interlayer dielectric layer and the barrier structure includes: forming a patterned material on the barrier structure and the interlayer dielectric layer; patterning the patterned material to form a patterned structure having a first opening and a second opening, wherein the first opening is located at a corresponding position of the barrier structure; and using the patterned structure as a mask, etching the interlayer dielectric layer and the barrier structure to form the first via and the second via.

[0013] Optionally, it may also include: forming a first conductive plug located within the first through hole and a second conductive plug located within the second through hole.

[0014] Optionally, the step of forming a first conductive plug located in the first through hole and a second conductive plug located in the second through hole includes: filling the first through hole and the second through hole with conductive material to form a first initial conductive plug located in the first through hole and a second initial conductive plug located in the second through hole; and planarizing the first initial conductive plug, the second initial conductive plug and the interlayer dielectric layer to form the first conductive plug and the second conductive plug.

[0015] Optionally, the first initial conductive plug, the second initial conductive plug, and the interlayer dielectric layer are planarized to form the first conductive plug and the second conductive plug, and the blocking structure is removed during the process.

[0016] Optionally, in the step of providing a substrate and a gate structure located on the substrate, the substrate on both sides of the gate structure has source / drain doped regions; in the step of forming a first conductive plug and a second conductive plug, the first conductive plug is electrically connected to the gate structure, and the second conductive plug is electrically connected to the source / drain doped regions.

[0017] Accordingly, the present invention also provides a semiconductor structure formed by the semiconductor structure forming method described in any of the preceding claims.

[0018] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0019] In the semiconductor structure formation method of the present invention, the interlayer dielectric layer and the barrier structure are etched to form the first via, and the interlayer dielectric layer is etched to form the second via, wherein the depth of the second via is greater than that of the first via. The barrier structure is located at the corresponding position of the gate structure, which slows down the etching rate at the position corresponding to the first via, thereby effectively reducing the occurrence of over-etching at the position of the first via on the gate structure when the second via on the substrate is etched, reducing the probability of damage to the gate structure, and improving the performance stability of the semiconductor device.

[0020] In an optional embodiment of the present invention, during the step of etching the interlayer dielectric layer and the barrier structure to form the first via and the second via, the etching rate of the material of the interlayer dielectric layer is in a first ratio to the etching rate of the material of the barrier structure. Based on this first ratio, the thickness of the barrier structure is adjusted to reduce the occurrence of over-etching at the location of the first via on the gate structure when the second via on the substrate is etched, thereby reducing the probability of gate structure loss and improving the performance stability of the semiconductor device. Attached Figure Description

[0021] Figures 1 to 2 This is a schematic diagram of the various steps in the formation process of a semiconductor structure according to an embodiment;

[0022] Figures 3 to 12 This is a schematic diagram of the various steps in the formation process of the semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0023] As can be seen from the background art, the existing methods for forming contact holes still have problems. The causes of these problems are analyzed below with reference to one embodiment:

[0024] Please refer to Figure 1 A substrate 100 and a gate structure 101 located on the substrate 100 are provided; an interlayer dielectric layer 102 is formed on the substrate 100 and the gate structure 101.

[0025] The material of the interlayer dielectric layer 102 is silicon oxide.

[0026] Please refer to Figure 2The interlayer dielectric layer 102 is etched to form a first via 103 and a second via 104. The first via 103 is located on the gate structure 101, and the second via 104 is located on the substrate 100 on at least one side of the gate structure 101, and the depth of the second via 104 is greater than that of the first via 103.

[0027] The second via 104 has a greater depth than the first via 103, and both vias 103 and 104 are etched using silicon oxide. This results in the first via 103 being over-etched on the gate structure 101 when the second via 104 on the substrate 100 is etched, causing damage to the gate structure 101 and affecting the stability of the semiconductor device.

[0028] To address the aforementioned technical problem, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate and a gate structure located on the substrate; forming an interlayer dielectric layer on the substrate and the gate structure; etching the interlayer dielectric layer to form a groove within the interlayer dielectric layer, the groove being located at a corresponding position of the gate structure; forming a barrier structure within the groove; etching the interlayer dielectric layer and the barrier structure to form a first via and a second via, the first via being located on the gate structure and penetrating the barrier structure, the second via being located on the substrate on at least one side of the gate structure and having a depth greater than that of the first via.

[0029] In the semiconductor structure formation method of the present invention, the interlayer dielectric layer and the barrier structure are etched to form a first via, and the interlayer dielectric layer is etched to form a second via, wherein the depth of the second via is greater than that of the first via. The barrier structure is located at the corresponding position of the gate structure, which slows down the etching rate at the position corresponding to the first via, thereby effectively reducing the occurrence of over-etching at the position of the first via on the gate structure when the second via on the substrate is etched, reducing the probability of damage to the gate structure, and improving the performance stability of the semiconductor device.

[0030] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0031] Please refer to Figure 3 A substrate 200 and a gate structure 201 located on the substrate 200 are provided; an interlayer dielectric layer 202 is formed on the substrate 200 and the gate structure 201.

[0032] The substrate 200 is made of materials including silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide. The substrate 200 includes an active region and an isolation region.

[0033] The material of the interlayer dielectric layer 202 is silicon oxide.

[0034] The gate structure 201 is located on the active region. Source / drain doped regions are formed within the substrates 200 on both sides of the gate structure 201. The source / drain doped regions are located within the active region.

[0035] Specifically, in some embodiments of the present invention, the gate structure 201 has a first height H relative to the substrate 200.

[0036] Please refer to Figure 4 The interlayer dielectric layer 202 is etched to form a groove 203 in the interlayer dielectric layer 202, and the groove 203 is located at the corresponding position of the gate structure 201.

[0037] The groove 203 is located at the corresponding position of the gate structure 201, that is, the projection of the gate structure 201 on the surface of the substrate 200 is located within the projection range of the groove 203 on the surface of the substrate 200.

[0038] The step of etching the interlayer dielectric layer 202 to form a groove 203 in the interlayer dielectric layer 202 includes: forming a mask layer on the interlayer dielectric layer 202, the mask layer exposing a portion of the interlayer dielectric layer 202; using the mask layer as a mask, etching the interlayer dielectric layer 202 to form a groove 203 in the interlayer dielectric layer 202, the groove 203 being located at the corresponding position of the gate structure 201.

[0039] Specifically, in some embodiments of the present invention, the etching is dry etching.

[0040] Specifically, in some embodiments of the present invention, the etching is anisotropic etching.

[0041] The position of the groove 203 defines the position of the subsequently formed blocking structure 205, and the groove 203 provides a structural basis for the subsequent formation of the blocking structure 205.

[0042] Please refer to Figures 5 to 6 In the groove 203 (e.g. Figure 4 A blocking structure 205 is formed within the groove 203 (as shown). The step of forming the blocking structure 205 within the groove 203 includes: as shown... Figure 5 As shown, the groove 203 is filled with a barrier material 204; as Figure 6 As shown, a planarization process is performed to form a blocking structure 205 located within the groove 203.

[0043] The top surface of the barrier structure 205 is flush with the surface of the interlayer dielectric layer 202. The flushness of the top surface of the barrier structure 205 with the top surface of the interlayer dielectric layer 202 provides a flat growth base for the patterned material 206 subsequently formed on the surfaces of the barrier structure 205 and the interlayer dielectric layer 202.

[0044] Specifically, in some embodiments of the present invention, the material of the blocking structure 205 is silicon nitride. In other embodiments, the material of the blocking structure may be other materials.

[0045] The thickness h of the barrier structure 205 is determined based on the first height H of the gate structure 201 and the ratio of the etching rate of the material of the interlayer dielectric layer 202 to the etching rate of the material of the barrier structure 205.

[0046] The purpose of the planarization process is to obtain a barrier structure 205 with a flat surface.

[0047] The planarization methods include mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing (CMP). Specifically, in this embodiment, the planarization method is CMP. Unlike traditional purely mechanical or purely chemical polishing methods, CMP, through the combined action of chemicals and machinery, avoids the surface damage caused by purely mechanical polishing and the drawbacks of purely chemical polishing, such as slow polishing speed, poor surface smoothness, and poor polishing consistency. CMP is widely used for high planarization polishing of various materials at the nanoscale.

[0048] Please refer to Figures 7 to 10 The interlayer dielectric layer 202 and the barrier structure 205 are etched to form a first via 210 and a second via 211. The first via 210 is located on the gate structure 201 and penetrates the barrier structure 205. The second via 211 is located on the substrate 200 on at least one side of the gate structure 201 and the depth of the second via 211 is greater than that of the first via 210.

[0049] The steps of etching the interlayer dielectric layer 202 and the barrier structure 205 include: as follows Figure 7 As shown, a patterned material 206 is formed on the barrier structure 205 and the interlayer dielectric layer 202; as Figure 8 As shown, the patterned material 206 is patterned to form a patterned structure 209 with a first opening 207 and a second opening 208, wherein the first opening 207 is located at the corresponding position of the blocking structure 205; as Figure 9As shown, using the patterned structure 209 as a mask, the interlayer dielectric layer 202 and the barrier structure 205 are etched to form the first via 210 and the second via 211. Figure 10 As shown, after forming the first through hole 210 and the second through hole 211, the patterned structure 209 is removed.

[0050] The graphic material 206 provides a structural basis for forming the graphic structure 209.

[0051] The top surface of the blocking structure 205 is flush with the surface of the interlayer dielectric layer 202, and the surface of the patterned material 206 formed is flat, which can effectively ensure the realization of the patterning process of the patterned material 206 and effectively ensure the accuracy of the patterning of the patterned material 206.

[0052] The first opening 207 of the graphical structure 209 is used to define the position and width of the first through hole 210; the second opening 208 of the graphical structure 209 is used to define the position and width of the second through hole 211.

[0053] The width of the first via 210 is the size of the first via 210 along the direction from one gate structure 201 to the adjacent gate structure 201.

[0054] The width of the second via 211 is the size of the second via 211 along the direction from one gate structure 201 to the adjacent gate structure 201.

[0055] Specifically, in some embodiments of the present invention, the width of the first through-hole 210 is not greater than the width of the blocking structure 205. That is, the projection of the first through-hole 210 on the surface of the substrate 200 is located within the projection range of the blocking structure 205 on the surface of the substrate 200, and the width of the blocking structure 205 is greater than or equal to the width of the first through-hole 210. This can effectively expand the process window of the formed first through-hole 210, which is beneficial to improving the etching accuracy of the first through-hole 210.

[0056] Specifically, in some embodiments of the present invention, in the step of etching the interlayer dielectric layer 202 and the barrier structure 205 to form the first via 210 and the second via 211, the etching rate of the material of the interlayer dielectric layer 202 is greater than the etching rate of the material of the barrier structure 205. Because the etching rate of the material of the barrier structure 205 is less than the etching rate of the material of the interlayer dielectric layer 202, the depth of the first via 210 obtained by etching is less than the depth of the second via 211 within the same etching time. This reduces the occurrence of over-etching at the location of the first via 210 on the gate structure 201, reduces the possibility of damage to the gate structure 201, and improves the performance stability of the semiconductor device.

[0057] Specifically, in some embodiments of the present invention, in the step of etching the interlayer dielectric layer 202 and the barrier structure 205 to form the first via 210 and the second via 211, the etching is dry etching.

[0058] Specifically, in some embodiments of the present invention, in the step of etching the interlayer dielectric layer 202 and the barrier structure 205 to form the first via 210 and the second via 211, the etching is anisotropic etching.

[0059] In the step of etching the interlayer dielectric layer 202 and the barrier structure 205 to form the first via 210 and the second via 211, the etching rate of the material of the interlayer dielectric layer 202 and the etching rate of the material of the barrier structure 205 have a first ratio A. Specifically, in some embodiments of the present invention, in the step of forming the barrier structure 205 in the groove 203, the thickness h of the barrier structure 205 is determined based on the first height H of the gate structure 201 and the first ratio A. The relationship between the thickness h of the barrier structure 205, the first height H, and the first ratio A is:

[0060] h = H / (A-1).

[0061] Please refer to Figures 11 to 12 After forming the first through hole 210 and the second through hole 211, the method further includes forming a first conductive plug 214 located in the first through hole 210 and a second conductive plug 215 located in the second through hole 211.

[0062] The steps of forming a first conductive plug 214 located in the first through hole 210 and a second conductive plug 215 located in the second through hole 211 include: as follows Figure 11As shown, conductive material is filled into the first through hole 210 and the second through hole 211 to form a first initial conductive plug 212 located in the first through hole 210 and a second initial conductive plug 213 located in the second through hole 211; as Figure 12 As shown, the first initial conductive plug 212, the second initial conductive plug 213, and the interlayer dielectric layer 202 are planarized to form the first conductive plug 214 and the second conductive plug 215.

[0063] In the step of filling the first through hole 210 and the second through hole 211 with conductive material to form a first initial conductive plug 212 located in the first through hole 210 and a second initial conductive plug 213 located in the second through hole 211, the conductive material includes tungsten.

[0064] Specifically, in some embodiments of the present invention, during the process of planarizing the first initial conductive plug 212, the second initial conductive plug 213 and the interlayer dielectric layer 202 to form the first conductive plug 214 and the second conductive plug 215, the blocking structure 205 is removed.

[0065] In the step of forming the first conductive plug 214 and the second conductive plug 215, the first conductive plug 214 is electrically connected to the gate structure 201, and the second conductive plug 215 is electrically connected to the source and drain doped regions.

[0066] Accordingly, embodiments of the present invention also provide a semiconductor structure, which is formed by the above-described semiconductor structure formation method, and will not be described in detail here.

[0067] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate and a gate structure located on the substrate are provided; An interlayer dielectric layer is formed on the substrate and the gate structure; The interlayer dielectric layer is etched to form a groove in the interlayer dielectric layer, and the groove is located at the corresponding position of the gate structure. The groove is filled with a barrier material; A planarization process is performed to form a blocking structure located within the groove; The interlayer dielectric layer and the barrier structure are etched to form a first via and a second via. The first via is located on the gate structure and penetrates the barrier structure. The second via is located on the substrate on at least one side of the gate structure and the depth of the second via is greater than that of the first via.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The width of the first through hole is not greater than the width of the blocking structure.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of etching the interlayer dielectric layer and the barrier structure to form the first via and the second via, the etching rate of the material of the interlayer dielectric layer is greater than the etching rate of the material of the barrier structure.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the interlayer dielectric layer is silicon oxide; the material of the barrier structure is silicon nitride.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing a substrate and a gate structure located on the substrate, the gate structure has a first height relative to the substrate; In the step of etching the interlayer dielectric layer and the barrier structure to form the first through-hole and the second through-hole, the etching rate of the material of the interlayer dielectric layer and the etching rate of the material of the barrier structure have a first ratio. In the step of forming a blocking structure within the groove, the thickness of the blocking structure is determined based on the first height and the first ratio.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, In the step of forming a blocking structure within the groove, the thickness of the blocking structure is the ratio of the first height to the first ratio.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps of etching the interlayer dielectric layer and the barrier structure include: A patterned material is formed on the barrier structure and the interlayer dielectric layer; The graphic material is graphicized to form a graphic structure with a first opening and a second opening, wherein the first opening is located at the corresponding position of the blocking structure. Using the patterned structure as a mask, the interlayer dielectric layer and the barrier structure are etched to form the first via and the second via.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A first conductive plug is formed within the first through hole, and a second conductive plug is formed within the second through hole.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The steps of forming a first conductive plug located in the first through hole and a second conductive plug located in the second through hole include: The first through hole and the second through hole are filled with conductive material to form a first initial conductive plug located in the first through hole and a second initial conductive plug located in the second through hole; The first initial conductive plug, the second initial conductive plug, and the interlayer dielectric layer are planarized to form the first conductive plug and the second conductive plug.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, During the planarization process of the first initial conductive plug, the second initial conductive plug, and the interlayer dielectric layer to form the first conductive plug and the second conductive plug, the blocking structure is removed.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing a substrate and a gate structure located on the substrate, source and drain doped regions are present in the substrate on both sides of the gate structure; In the step of forming the first conductive plug and the second conductive plug, the first conductive plug is electrically connected to the gate structure, and the second conductive plug is electrically connected to the source and drain doped regions.

12. A semiconductor structure, characterized in that, The semiconductor structure is formed by the semiconductor structure forming method as described in any one of claims 1 to 11.

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