Preparation method of silicon adapter plate and silicon adapter plate

Abstract

The invention discloses a preparation method of a silicon adapter plate and the silicon adapter plate, and belongs to the technical field of semiconductors. The preparation method comprises the following steps: providing a wafer; wherein the wafer comprises a silicon substrate and an interlayer dielectric layer, the interlayer dielectric layer is arranged on the silicon substrate, the dielectric constant of the interlayer dielectric layer is within a preset range, and a first conductive piece is arranged in the interlayer dielectric layer; depositing a mask layer on one side, far away from the interlayer dielectric layer, of the silicon substrate, etching a through hole in the mask layer based on the first conductive part, and etching the bottom of the through hole to one side, close to the silicon substrate, of the first conductive part; the through hole is filled with a conductive material, and the conductive material is electrically connected with the first conductive part. According to the technical scheme, the through hole is etched from the side, away from the interlayer dielectric layer, of the silicon substrate, etching to the interlayer dielectric layer is completely or partially avoided, and therefore the over-etching problem of the interlayer dielectric layer is avoided.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a method for preparing a silicon adapter plate and a silicon adapter plate. Background Art

[0002] At present, in the field of semiconductor technology, a silicon adapter plate includes a silicon substrate and an interlayer dielectric layer and a mask layer stacked on the silicon substrate. Since the interlayer dielectric layer includes a low dielectric constant (Low-k) material, when etching a through hole based on the mask layer, the interlayer dielectric layer with a low dielectric constant has a porous structure. Due to the porous structure, the etching gas is more likely to penetrate and react, resulting in a higher etching rate of the interlayer dielectric layer with a low dielectric constant.

[0003] In addition, the interlayer dielectric layer with low dielectric constant has a porous structure, which makes it easier for the volatile products produced by the low dielectric constant material to be released during the etching process of the Through Silicon Via (TSV). Therefore, under the same etching conditions, the etching rate of the interlayer dielectric layer of the low dielectric constant material is faster, resulting in over-etching of the TSV through hole during the etching process, which will cause the interlayer dielectric layer in the silicon adapter to be damaged during the TSV through hole etching process. Summary of the invention

[0004] The present application proposes a method for preparing a silicon adapter plate and a silicon adapter plate, which completely or partially avoids etching the interlayer dielectric layer by etching a through hole from a side of a silicon substrate away from an interlayer dielectric layer, thereby avoiding over-etching of the interlayer dielectric layer.

[0005] In a first aspect, the present application provides a method for preparing a silicon adapter plate, the method comprising providing a wafer; wherein the wafer comprises a silicon substrate and an interlayer dielectric layer, the interlayer dielectric layer is arranged on the silicon substrate, and the dielectric constant of the interlayer dielectric layer is within a preset range, and a first conductive member is arranged in the interlayer dielectric layer; Depositing a mask layer on a side of the silicon substrate away from the interlayer dielectric layer, and etching a through hole on the mask layer based on the first conductive member, and etching the bottom of the through hole to a side of the first conductive member close to the silicon substrate; A conductive material is filled in the through hole, wherein the conductive material is electrically connected to the first conductive member.

[0006] In some embodiments, the material of the mask layer includes SiO 2 ; There are multiple interlayer dielectric layers, and the multiple interlayer dielectric layers are stacked on the silicon substrate; wherein the material of one interlayer dielectric layer in two adjacent interlayer dielectric layers is SiO 2; The material of the other interlayer dielectric layer in the two adjacent interlayer dielectric layers is SiOCH.

[0007] In some embodiments, the first conductive member is disposed in an interlayer dielectric layer close to the silicon substrate.

[0008] In some embodiments, etching a through hole on the mask layer based on the first conductive member, etching the bottom of the through hole to a side of the first conductive member close to the silicon substrate, comprises: Based on the first conductive member, a through hole is etched on the mask layer, and the bottom of the through hole is etched to a side of the interlayer dielectric layer close to the silicon substrate; A through hole is etched on the interlayer dielectric layer based on the first conductive member to extend the length of the through hole until the bottom of the through hole is etched to a side of the first conductive member close to the silicon substrate.

[0009] In some embodiments, providing a wafer includes: Providing a logic wafer and a carrier wafer, wherein the logic wafer includes the silicon substrate and the interlayer dielectric layer; Bonding the logic wafer and the carrier wafer; The side of the silicon substrate away from the carrier wafer is thinned.

[0010] In some embodiments, before bonding the logic wafer and the carrier wafer, the preparation method further includes: A first interconnection structure is formed on a side of the interlayer dielectric layer away from the silicon substrate; wherein the first interconnection structure includes a first conductive wire and a first micro-convex structure, one end of the first conductive wire is electrically connected to the first conductive member, and the other end of the first conductive wire is electrically connected to the first micro-convex structure, and the first micro-convex structure is used to electrically connect a chip or a substrate.

[0011] In some embodiments, the logic wafer further includes an active device, a fourth conductive line and a groove, a portion of the active device is disposed in the silicon substrate, and another portion is disposed in the interlayer dielectric layer, one end of the fourth conductive line is electrically connected to the active device, the groove is disposed on a surface of the interlayer dielectric layer away from the silicon substrate, and the groove is filled with a conductive element, and the conductive element is electrically connected to the other end of the fourth conductive line, wherein before bonding the logic wafer and the carrier wafer, the preparation method further includes: A dielectric layer and a second interconnect structure are formed on a side of the interlayer dielectric layer away from the silicon substrate; wherein the conductive element is electrically connected to the second interconnect structure, and the second interconnect structure includes a second conductive wire and a second micro-convex structure, one end of the second conductive wire is electrically connected to the conductive element, and the other end of the second conductive wire is electrically connected to the second micro-convex structure, and the second micro-convex structure is used to electrically connect a chip or a substrate.

[0012] In some embodiments, after the conductive material is filled in the through hole, the preparation method further includes: A third interconnect structure is formed on a side of the mask layer away from the silicon substrate; wherein the third interconnect structure is electrically connected to the conductive material; the third interconnect structure comprises a third conductive wire and a third micro-convex structure, one end of the third conductive wire is electrically connected to the conductive material, the other end of the third conductive wire is electrically connected to the third micro-convex structure, and the third micro-convex structure is used to electrically connect a chip or a substrate; The logic wafer and the carrier wafer are debonded.

[0013] In some embodiments, the orthographic projection of the first conductive member on the first plane covers the orthographic projection of the through hole on the first plane, and the orthographic projection of the third interconnect structure on the first plane covers the orthographic projection of the through hole on the first plane, wherein the first plane is a plane parallel to the silicon substrate.

[0014] In some embodiments, the material of the mask layer includes SiO 2 .

[0015] In the method for preparing the silicon adapter provided in the embodiment of the present application, a through hole is etched from the side of the silicon substrate away from the interlayer dielectric layer, and the through hole is etched to the side of the first conductive member in the interlayer dielectric layer close to the silicon substrate. Compared with the through hole in the silicon adapter provided in the related art, which is etched from the side of the interlayer dielectric layer away from the silicon substrate, during the etching process of the through hole, etching to the interlayer dielectric layer can be completely avoided or only part of the interlayer dielectric layer needs to be etched, thereby avoiding the problem of over-etching of the interlayer dielectric layer.

[0016] In a second aspect, the present application further provides a silicon adapter board, comprising: A logic wafer, wherein the wafer comprises a silicon substrate and an interlayer dielectric layer, the interlayer dielectric layer is arranged on the silicon substrate, and the dielectric constant of the interlayer dielectric layer is within a preset range, and a first conductive member is arranged in the interlayer dielectric layer; A mask layer, wherein the mask layer is arranged on a side of the silicon substrate away from the interlayer dielectric layer; A through hole passes through the silicon substrate and is filled with a conductive material, wherein the conductive material is electrically connected to the first conductive member. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figures 1 to 11 A process flow chart of a silicon transfer board provided for related technology; Fig.12 A SiO2 2 and a schematic diagram of the structural formula of SiOCH; Fig.13 A schematic diagram of horizontal over-etching of an interlayer dielectric layer with a low dielectric constant provided for related technology; Fig.14 A schematic diagram of a process for preparing a silicon adapter plate provided in the present application; Fig.15 A schematic structural diagram of a method for preparing a silicon adapter plate provided in the present application; Fig.16 A schematic structural diagram of another method for preparing a silicon adapter plate provided in the present application; Figures 17 to 29 A process flow chart of a silicon adapter board provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0019] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0020] In the description of the present application, “plurality” means two or more.

[0021] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0022] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "electrically connected" indicates, for example, that two or more components are in direct physical or electrical contact, and may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0023] At present, in the existing electronic packaging technology, organic substrates have certain limitations in wiring density due to their material properties, such as high thermal expansion coefficient and poor heat dissipation performance. They are difficult to meet the growing demand for high-density integration, thus limiting the further improvement of the performance and function of electronic systems, especially in application scenarios that require high integration and complex circuit design.

[0024] To solve the above problems, the related art proposes a silicon substrate using TSV vertical interconnection vias and high-density metal wiring. The silicon substrate realizes electrical interconnection between the two sides of the silicon wafer by forming TSV vertical interconnection vias in the silicon wafer. The TSV vertical interconnection vias are filled with conductive materials to ensure good electrical connection performance. At the same time, high-density metal wiring on the silicon substrate can improve the wiring density and circuit complexity, thereby improving the density integration of the silicon substrate to facilitate the realization of system-level heterogeneous integration.

[0025] The silicon-based passive platform with TSV vertical interconnect vias is also called a TSV interposer. TSV Interposer is a special interposer that uses TSV technology to create vertical vias in the silicon substrate. These vias are filled with conductive materials (such as copper) to achieve electrical connection between the upper and lower surfaces of the chip.

[0026] For example, the packaging structure using TSV interposer is called 2.5D Interposer. In the 2.5D Interposer packaging structure, several chips are arranged side by side on the Interposer, and high-density interconnection between chips and chips, and between chips and silicon interposers is achieved through TSV vertical interconnection vias, redistribution layers (RDL), micro bumps and other structures on the Interposer.

[0027] With the demand for high performance and high integration of advanced packaging, active silicon interposer came into being. Active silicon interposer refers to a silicon interposer that integrates active electronic components (such as power management integrated circuit (PMIC) or static random access memory (SRAM)).

[0028] Furthermore, the silicon interposer can not only serve as a traditional passive connector for signal transmission between different chips, but also contains active functions, enabling it to perform more tasks, such as power management or data processing. Silicon interposers are often used in 3D chip stacking or chip (chiplet) packaging to improve system performance and integration. It should be noted that the passive adapter only contains the metal interconnect layer, while the active adapter can integrate functions such as power supply and on-chip network communication. The emergence of active chip high-density TSV interconnect technology, represented by high bandwidth memory (HBM) and active adapter integration technology, marks the arrival of the front-end packaging era.

[0029] In 2020, Intel released the Lakefield processor, which uses multiple 10nm compute chips (Compute Die) stacked on a 22nm base chip (Base Die). The above 22nm base chip is the "Active Interposer". The 10nm compute chip and the 22nm base chip use TSV through-holes for electrical interconnection, thereby realizing communication and interconnection between the base chip and the compute chip.

[0030] The manufacturing of active silicon adapter board is the front-end process of Fab, and the chips used are mostly logic chips (Logic Wafer) with advanced process. Currently, the commonly used logic chips have replaced the Al metal interconnection line with Cu metal interconnection line to reduce the resistance (the resistivity of Cu is The resistivity of Al is ).

[0031] In addition, low dielectric constant (Low-k) dielectric materials (k < 3) replace Materials (3.9<k<4.2) can reduce the dielectric constant of the insulating layer between metal interconnect layers. For example, the 90 nm process requires the dielectric constant k to be in the range of [2.9, 3.0], and the 65 nm process requires the dielectric constant k to be in the range of [2.8, 2.7]. Among them, the 45 nm process requires the dielectric constant k to be in the range of [2.5, 2.6], and the 32 nm and below processes require the dielectric constant k to be in the range of k less than 2.4.

[0032] Among them, the above-mentioned 90 nm process means that the minimum distance or characteristic size between circuits in an integrated circuit is 90nm; the 65 nm process means that the minimum distance or characteristic size between circuits in an integrated circuit is 65nm; the 45 nm process means that the minimum distance or characteristic size between circuits in an integrated circuit is 45nm; the 32 nm and below process means that the minimum distance or characteristic size between circuits in an integrated circuit is 32nm.

[0033] It should be noted that Low-k technology is to select materials with a smaller dielectric constant (k) as the interlayer dielectric layers (ILD) between the internal circuit layers of the chip, thereby preventing mutual interference between the circuits of each layer to improve the stability and operating frequency of the chip. The operating speed of the integrated circuit is determined by the gate delay of the transistor and the propagation delay of the signal. Among them, the use of high dielectric constant (high-k) materials can effectively reduce the gate delay.

[0034] RC delay is determined by the resistance R of the metal wire and the capacitance C formed by the internal dielectric. The smaller the RC delay value, the faster the signal transmission speed. The R value is determined by the properties of the material, so reducing the capacitance value can improve the transmission speed of the line. The capacitance value is related to the dielectric constant k of the interlayer dielectric layer (ILD). The smaller the k value, the smaller the capacitance value.

[0035] Low-k technology refers to the use of low dielectric constant (Low-k) materials as interlayer dielectric layers between circuit layers inside the chip to reduce parasitic capacitance between metal interconnects and reduce RC delay, thereby improving chip stability and operating frequency.

[0036] In addition, Low-k technology can also reduce line crosstalk. When a transmission line transmits a signal, it generates an induced signal on another transmission line through mutual inductance, or generates a coupled signal through capacitance. These two phenomena are collectively called crosstalk.

[0037] Furthermore, crosstalk can cause abnormal signal pulses to appear in adjacent transmission lines, resulting in malfunction of logic circuits.

[0038] The coupling interference is caused by the parasitic capacitance between the wires. According to the capacitive reactance expression , we can know that: the larger the capacitance C, the greater the c The smaller it is, the easier it is for the signal to pass through the dielectric from one conductor to another, and the more serious the crosstalk between the lines; the higher the frequency of the signal, the shorter the rise and fall time of the pulse, and the more serious the crosstalk.

[0039] In summary, using Low-k materials as the material of the interlayer dielectric layer can reduce the distributed capacitance to shorten the RC delay, thereby increasing the operating speed of the chip; in addition, the reduction of distributed capacitance can reduce signal crosstalk, allowing the distance between interconnect lines to be closer, which can further improve the integration of the chip.

[0040] Figures 1 to 11 A process flow chart of a silicon transfer board provided for related technology, such as Figures 1 to 11 As shown, the related technology provides a method for preparing a silicon transfer plate as follows: S1A, providing a logic wafer, and depositing a hard mask layer on the logic wafer. The logic wafer includes a silicon substrate 1a and an interlayer dielectric layer 2a disposed on the silicon substrate 1a. The dielectric constant of the interlayer dielectric layer 2a is within a preset range.

[0041] S2A, etching a through hole based on the mask layer, etching the through hole to the inside of the silicon substrate; and filling the through hole with a conductive material. The conductive material 10a may be SiO 2 .

[0042] S3A, forming an interconnection structure on the logic wafer having the above structure, and bonding the logic wafer having the interconnection structure to a carrier wafer.

[0043] S4A, thinning the silicon substrate side of the logic wafer away from the interlayer dielectric side, so that the conductive material in the through hole is exposed to the outside.

[0044] S5A, debonding the logic wafer and the carrier wafer.

[0045] In summary, in the related art, etching of the through hole Va requires etching of the interlayer dielectric layer 2a, which may cause over-etching of the interlayer dielectric layer 2a and moisture absorption, thereby affecting the electrical performance of the silicon adapter.

[0046] In addition, in the related art, during the preparation of the silicon adapter, the through hole Va is first etched and the conductive material 10a is filled in the through hole Va. After the conductive material 10a is filled in the through hole Va, the logic wafer and the carrier wafer are bonded. After the wafer bonding is completed, the "back copper exposure" process is performed. Among them, "back copper exposure" means: by thinning the silicon substrate 1a away from the side of the interlayer dielectric layer 2a, the conductive material 10a (copper) inside the through hole Va is exposed to the outside world.

[0047] In the related art, during the preparation of the silicon adapter plate, the silicon substrate 1a is thinned by grinding. In the related art, a through hole Va filled with a conductive material 10a is first prepared, and then the silicon substrate 1a is ground to thin the silicon substrate 1a. However, since the silicon substrate 1a has the problem of "copper exposed on the back side" after being thinned, copper metal contamination inside the through hole Va will occur during the grinding process of the silicon substrate 1a.

[0048] Based on the above embodiment, the related technology also provides a specific embodiment as follows: The relevant technical personnel purchase the completed logic wafer as the raw material of the silicon adapter board. The logic wafer includes a silicon substrate 1a and an interlayer dielectric layer 2a. A hard mask layer 3a is deposited on the side of the interlayer dielectric layer 2a away from the silicon substrate 1a, and the silicon substrate 1a is etched based on the hard mask layer 3a using the Bosch process to form a through hole va.

[0049] A protective layer is deposited inside the partial through hole va located inside the silicon substrate 1a, and a seed layer and a barrier layer are sequentially deposited on the side of the protective layer away from the through hole va. A conductive material 10a is filled inside the through hole va and on the side of the barrier layer away from the through hole va to form a vertical conductive channel.

[0050] Wherein, the protective layer may be an insulating linear oxide layer.

[0051] The through hole va is subjected to a surface copper chemical mechanical polishing (CMP) process to complete the loop structure in the through hole va. A groove is etched based on the hard mask layer 3a, and the groove is etched to the inside of the interlayer dielectric layer 2a, and a conductive member is filled inside the groove for subsequent electrical connection with the interconnection structure. Among them, the interconnection structure includes electrically connected interconnection lines and micro-bumps. A second mask layer is deposited on the side of the hard mask layer 3a away from the silicon substrate 1a, and an interconnection structure is formed on the second mask layer for subsequent electrical connection with the chip. The logic wafer provided with the above structure is temporarily bonded to the carrier wafer.

[0052] The silicon substrate 1a of the logic wafer provided with the above structure is subjected to a backside copper exposure process to expose the through hole va and the conductive material 10a in the through hole va from the back side of the silicon substrate 1a. Metal wiring is performed based on the conductive material 10a in the through hole va exposed from the back side of the silicon substrate 1a, wherein the metal wiring is used to lead the circuit out from the back side of the through hole va. An interconnection structure is formed on the metal lead, and the interconnection structure is used to be electrically connected to the substrate later. Finally, the logic wafer formed with the above structure is debonded from the carrier wafer to complete the preparation of the entire silicon transfer board.

[0053] Based on the above-mentioned related technologies, currently, the material of the interlayer dielectric layer 2a in the silicon adapter plate includes SiO 2 , and the dielectric constant (k) of the interlayer dielectric layer 2a can be reduced by 2 This is achieved by introducing carbon elements into the interlayer dielectric layer 2a. Since the introduction of carbon reduces the polarization effect of the interlayer dielectric layer 2a, the dielectric constant of the interlayer dielectric layer 2a can be reduced.

[0054] In addition, when carbon is added to the material SiO 2 In the middle, Si-CH 3 Group or Si-CH 2 The -Si group replaces the Si-O group and terminates the Si-O group network.

[0055] Fig.12 A SiO2 2 And the schematic diagram of the structural formula of SiOCH, where SiO 2 The structural formula is Fig.12 As shown in Figure (a), the structural formula of SiOCH is as follows Fig.12 As shown in Figure (b).

[0056] Compared to Fig.12 The SiO 2 The structural formula of Fig.12The density of SiOCH shown in Figure (b) is reduced and has a porous structure. The porous structure of SiOCH reduces the electronic polarization of the SiOCH material, thereby helping to further reduce the dielectric constant of the interlayer dielectric layer 2a.

[0057] Furthermore, in the SiOCH structure, Si-CH 3 Group and Si-CH 2 -Si groups can easily interact with water molecules H 2 O undergoes a hydrolysis reaction, in which the -OH group replaces the carbon atom and is converted into a Si-OH group.

[0058] In addition, the deep reactive ion etching (DRIE) process of the through hole VA is a process that combines physical and chemical reactions. The deep reactive ion etching of the through hole VA removes the material on the surface of the logic wafer by utilizing high-power plasma bombardment to enhance etching. However, in an oxygen environment, O 2 Easily decomposed into O and . Due to O and It has strong oxidizing properties, resulting in O and It reacts readily with hydrocarbons and oxygen-containing polymers.

[0059] Therefore, Si-CH in SiOCH 3 The group may be oxidized to Si-OH, CO 2 and H 2 O, the reaction equation is shown in equation (3).

[0060] The Si-OH group is hydrophilic and easily induces water absorption. In addition, due to the porous structure of SiOCH, it is more conducive to the adsorption of water. The high dielectric constant of water molecules (about 78) will lead to an increase in leakage current and dielectric constant.

[0061] In addition, the deep reactive ion etching (DRIE) process of the through hole is a process that combines physical and chemical reactions to remove materials from the wafer surface by utilizing high-power plasma bombardment to enhance etching. 2 Easily decomposed into O and . O and It has strong oxidizing properties and easily reacts with hydrocarbons and oxygen-containing polymers. The Si-OH group is hydrophilic and easily induces water absorption. In addition, due to the porous structure of SiOCH, it is more conducive to the adsorption of water. The high dielectric constant of water molecules (about 78) will lead to an increase in leakage current and dielectric constant.

[0062] Among them, Si-CH3 and Si-CH 2 The reaction equations of Si-CH in SiOCH are shown in the following equations (1) and (2). 3 The group may be oxidized to Si-OH, CO 2 and H 2 O, the reaction equation is shown in equation (3): (1) (2) (3) In addition, due to the porous structure of SiOCH, the mechanical strength of SiOCH is much weaker than that of SiO 2 .SiO 2 The hardness of SiOCH is about 9 GPa, while the hardness of SiOCH is about 2 GPa. 2 The elastic modulus of SiOCH is about 80 GPa, while that of SiOCH is about 10 GPa. In fact, the lower the dielectric constant (DK) of a dielectric material, the weaker its mechanical properties are generally.

[0063] In the silicon transfer board provided by the related art, an interlayer dielectric layer 2a made of a low dielectric constant material is used. During the preparation process of the silicon transfer board, the interlayer dielectric layer 2a may have the following problems: Firstly, the over-etching problem of the interlayer dielectric layer 2a occurs during the etching of the through hole va.

[0064] Specifically, during the etching of the through hole va, the porous structure of the low dielectric constant material makes it easier for the etching gas to penetrate and react, thereby resulting in a higher etching rate of the low dielectric constant material.

[0065] In addition, carbon compounds are usually more likely to form volatile gases during the etching process, which further promotes the etching reaction. The porous structure also makes it easier to release volatile products generated in the material during the etching process. Therefore, under the same etching conditions, the etching rate of SiOCH is greater than that of SiO 2 When deep through hole etching, the main etching gas is SF 6 Due to the chemical bond energy, SF 6 With SiO 2 The reaction rate is much lower than that of SF 6 The reaction rate with Si. However, due to the porous structure of SiOCH, SiOCH will be damaged during deep through-hole etching, resulting in horizontal over-etching in the through-hole etching process in the related art. Fig.13 A schematic diagram of horizontal overetching of an interlayer dielectric layer with a low dielectric constant is provided for related technologies, such as Fig.13As shown, a groove vb is produced in the horizontal direction of the through hole va due to over-etching.

[0066] Secondly, when cleaning the interlayer dielectric layer 2a made of low dielectric constant material, the interlayer dielectric layer 2a absorbs moisture, thereby affecting the electrical performance of the silicon transfer board.

[0067] Specifically, since the etching of the entire through hole va is carried out in steps, each step needs to be cleaned with deionized water, ammonia water, hydrogen peroxide solution, etc. In particular, after the through hole va is etched, when the through hole va is etched to a deeper depth, the polymer contaminants therein are heavier. Since the wet cleaning of polymer contaminants is strong, the cleaning step after etching the through hole va will cause the low dielectric constant material to have moisture absorption problems, thereby affecting the electrical performance of the silicon adapter board, and there is a potential risk of short circuit.

[0068] In view of the over-etching problem of the interlayer dielectric layer 2a and the moisture absorption problem of the interlayer dielectric layer 2a, the following optimizations are provided: First, in terms of through-hole VA etching, the etching process recipe is optimized by adjusting parameters such as Source Power, Bias Power, gas type, and gas flow ratio, and / or by making certain modifications to the machine, such as optimizing the relevant structure of the machine, so that the ions are more directional, thereby reducing the lateral etching of the low dielectric constant interlayer dielectric layer 2a.

[0069] Secondly, in terms of cleaning, there is the problem of moisture absorption of the interlayer dielectric layer 2a, and corresponding processes can be added later to remove the moisture.

[0070] Specifically, since the water absorption characteristics of the above-mentioned low dielectric constant materials are prone to cause short circuit problems, after each cleaning process, a furnace tube baking or UV (ultraviolet) irradiation process needs to be added to ensure that the moisture is completely removed.

[0071] Of course, the main problem with through-hole VA etching is that it is too difficult to debug both the machine hardware (Hardware) and software (Recipe).

[0072] The reasons are as follows: the machine hardware has high equipment complexity and high requirements for equipment maintenance and stability; the machine software has numerous and interrelated process parameters and high requirements for precise control of the process window.

[0073] It should be noted that if the overall process window is too small, it will cause lateral etching of materials with low dielectric constants.

[0074] Specifically, when the process window for etching the through hole VA is small, the adjustable range of each process parameter is very narrow during the etching process. For example, a slight extension of the etching time will lead to over-etching. For another example, a slight reduction in the etching gas flow rate will lead to incomplete etching. Therefore, in actual production, the control requirements for process parameters are extremely high. Once the process window is exceeded, the etching quality will be unqualified.

[0075] Of course, the main problem with cleaning low-k materials is that during the preparation of the silicon adapter, a furnace or UV irradiation process needs to be added after each cleaning. Both processes are heating in nature and occupy the overall chip thermal budget. Excessive heating will affect the performance of the chip.

[0076] In summary, in the related art, there are problems of lateral etching and moisture absorption in the process of etching the through hole va for the interlayer dielectric layer 2a with a low dielectric constant.

[0077] To solve the above problems, the present application proposes a method for preparing a silicon adapter plate and a silicon adapter plate, by etching a through hole from the side of the silicon substrate away from the interlayer dielectric layer, thereby completely avoiding etching the interlayer dielectric layer or only etching part of the interlayer dielectric layer, thereby avoiding the problem of over-etching of the interlayer dielectric layer.

[0078] Fig.14 A schematic diagram of a process for preparing a silicon adapter plate provided in this application, Fig.15 A schematic diagram of a method for preparing a silicon adapter plate provided in this application is shown in FIG. Fig.16 A structural schematic diagram of another method for preparing a silicon adapter plate provided in this application, such as Figures 14 to 16 As shown, in an embodiment of the present application, a method for preparing a silicon adapter plate includes: S1. Provide a wafer; wherein the wafer includes a silicon substrate and an interlayer dielectric layer, the interlayer dielectric layer is arranged on the silicon substrate, and the dielectric constant of the interlayer dielectric layer is within a preset range, and a first conductive member is arranged in the interlayer dielectric layer.

[0079] S2. Depositing a mask layer on a side of the silicon substrate away from the interlayer dielectric layer, etching a through hole on the mask layer based on the first conductive member, and etching the bottom of the through hole to a side of the first conductive member close to the silicon substrate.

[0080] S3. Filling the through hole with a conductive material, wherein the conductive material is electrically connected to the first conductive member.

[0081] It should be noted that the silicon adapter board includes an active silicon adapter board and a passive silicon adapter board.

[0082] The difference between the method for preparing the silicon adapter board provided by the present application and the method for preparing the silicon adapter board provided by the related art is that in the method for preparing the silicon adapter board provided by the present application, the through hole V1 is etched from the side of the silicon substrate 1 away from the interlayer dielectric layer, and the through hole V1 is etched to the side of the first conductive member 100 located in the interlayer dielectric layer close to the silicon substrate 1. Compared with the setting mode provided by the related art that the through hole V1 in the silicon adapter board is etched from the side of the interlayer dielectric layer away from the silicon substrate 1, during the etching process of the through hole V1, etching to the interlayer dielectric layer can be completely avoided or only part of the interlayer dielectric layer needs to be etched, thereby not only avoiding the problem of over-etching of the interlayer dielectric layer, but also avoiding the problem of poor electrical connection of the silicon adapter board due to moisture absorption of the interlayer dielectric layer.

[0083] In some embodiments, there are multiple interlayer dielectric layers, and the multiple interlayer dielectric layers are stacked on the silicon substrate 1. Among them, the material of one interlayer dielectric layer in two adjacent interlayer dielectric layers is SiO 2 , the material of the other interlayer dielectric layer in the two adjacent interlayer dielectric layers is SiOCH.

[0084] For example, Fig.15 As shown, two adjacent interlayer dielectric layers 201 and 202, or two adjacent interlayer dielectric layers 203 and 204, or two adjacent interlayer dielectric layers 204 and 205, wherein the material of the interlayer dielectric layer 201, the interlayer dielectric layer 203 and the interlayer dielectric layer 205 is SiO 2 The material of the interlayer dielectric layer 202 and the interlayer dielectric layer 204 is SiOCH.

[0085] In some embodiments, Fig.16 As shown, the first conductive member 100 is disposed in the interlayer dielectric layer close to the silicon substrate 1. For example, the first conductive member 100 is disposed in the interlayer dielectric layer 201, wherein the interlayer dielectric layer 201 is disposed on a side closer to the silicon substrate 1. This arrangement not only optimizes the process sequence, but also completely avoids etching the interlayer dielectric layer during the etching process of the through hole V1, thereby avoiding the problem of over-etching the interlayer dielectric layer, and avoids the problem of moisture absorption caused by direct contact between the cleaning agent and the interlayer dielectric layer during the cleaning process, thereby causing poor electrical connection of the silicon adapter.

[0086] Based on the above embodiments, the present application also provides a specific embodiment to explain the preparation process of the silicon adapter plate provided by the present application. Figures 17 to 29 A process flow chart of a silicon adapter board provided in an embodiment of the present application, such as Figures 17 to 29As shown, this specific embodiment is explained by taking the first conductive member 100 as being disposed in the interlayer dielectric layer away from the silicon substrate 1 as an example. For example, the first conductive member 100 is disposed in the interlayer dielectric layer 205 away from the silicon substrate 1. In this arrangement, the through hole is first etched to penetrate the silicon substrate 1, and after the through hole is cleaned, the through hole is etched again to extend the through hole to the side of the first conductive member 100 close to the silicon substrate 1. In this through hole etching method, only part of the interlayer dielectric layer needs to be etched, which can avoid the over-etching problem and moisture absorption problem of the interlayer dielectric layer.

[0087] Of course, the present application also provides another specific embodiment to explain the preparation process of the silicon adapter provided by the present application. Among them, the specific embodiment is explained by taking the first conductive member 100 as an example to be arranged in the interlayer dielectric layer close to the silicon substrate 1. For example, the first conductive member 100 is arranged in the interlayer dielectric layer 201 close to the silicon substrate 1. The preparation process of this specific embodiment is similar to Figures 17 to 29 The preparation process is similar to that in , and will not be repeated here.

[0088] In an embodiment of the present application, providing a wafer includes the steps of: S10. Provide a logic wafer and a carrier wafer, wherein the logic wafer includes a silicon substrate and an interlayer dielectric layer.

[0089] S20, bonding the logic wafer and the carrier wafer.

[0090] S30, thinning the side of the silicon substrate away from the carrier wafer.

[0091] The method for preparing the silicon adapter provided in the embodiment of the present application is different from the method for preparing the silicon adapter provided in the related art in that, in the process for preparing the silicon adapter provided in the related art, the through hole V1 is first etched and the conductive material 10 is filled in the through hole V1, and after the conductive material 10 is filled in the through hole V1, the logic wafer 50a and the carrier wafer 50b are bonded, and after the wafer bonding is completed, the "back copper exposure" process is performed. Among them, "back copper exposure" means: by thinning the silicon substrate 1 away from the side of the interlayer dielectric layer, the conductive material 10 (copper) inside the through hole V1 is exposed to the outside world.

[0092] In the process of preparing the silicon adapter plate provided in the embodiment of the present application, Figures 20 to 28 As shown, the logic wafer 50a and the carrier wafer 50b are bonded first, and after the wafer bonding is completed, the side of the silicon substrate 1 away from the carrier wafer 50b is thinned, and after the silicon substrate 1 is thinned, the through hole V1 is etched.

[0093] In summary, the method for preparing the silicon adapter plate provided by the present application is different from the method for preparing the silicon adapter plate provided by the related art. Since the present application thins the side of the silicon substrate 1 away from the carrier wafer 50b after wafer bonding, and etches the through hole V1 after the thinning of the silicon substrate 1, and fills the inside of the through hole V1 with a conductive material 10. In the embodiment of the present application, the conductive material 10 filled inside the through hole V1 is copper.

[0094] Of course, the conductive material 10 filled inside the through hole V1 in the present application may also be other conductive materials, and the present application does not limit this. The conductive material 10 filled inside the through hole V1 is now explained as copper.

[0095] Furthermore, in the method for preparing the silicon adapter provided in the present application, when thinning the side of the silicon substrate 1 away from the carrier wafer 50b, there is no need to consider the problem of "copper exposure on the back side" that occurs in the related art.

[0096] In the related art, in the process of preparing the silicon adapter plate, the silicon substrate 1a is thinned by grinding. In the related art, a through hole V1 filled with a conductive material 10 is first prepared, and then the silicon substrate 1a is ground to thin the silicon substrate 1a. However, since the silicon substrate 1a has the problem of "copper exposed on the back" after thinning, copper metal contamination inside the through hole V1 will occur during the grinding of the silicon substrate 1a. Since the method for preparing the silicon adapter plate provided in the present application does not have the problem of "copper exposed on the back" in the related art, it is not necessary to adopt the relatively complex process of the original BVR or BFR, thereby greatly simplifying the overall process flow. At the same time, since the surface of the silicon substrate 1 can be thoroughly cleaned after grinding to ensure that there is no contamination before the etching process of the through hole V1 is performed, the present application can avoid or reduce the contamination of the conductive material 10 inside the through hole V1 compared with the related art.

[0097] Reference Fig.18 and Fig.19 In some embodiments, before bonding the logic wafer 50a and the carrier wafer 50b, the preparation method further includes the steps of: S20a, forming a first interconnection structure H1 on a side of the interlayer dielectric layer away from the silicon substrate. The first interconnection structure H1 includes a first conductive line L1 and a first micro-convex structure T1, one end of the first conductive line L1 is electrically connected to the first conductive member 100, and the other end of the first conductive line T1 is electrically connected to the first micro-convex structure T1, and the first micro-convex structure T1 is used to electrically connect the chip or substrate.

[0098] In some embodiments, the logic wafer 50a further includes an active device 4, a fourth conductive line L4 and a groove Vc, a portion of the active device 4 is disposed in the silicon substrate 1, and another portion is disposed in the interlayer dielectric layer, one end of the fourth conductive line L4 is electrically connected to the active device 4, the groove Vc is disposed on the surface of the interlayer dielectric layer away from the silicon substrate 1, and the groove Vc is filled with a conductive element 6, and the conductive element 6 is electrically connected to the other end of the fourth conductive line L4, wherein before bonding the logic wafer 50a and the carrier wafer 50b, the method for preparing the silicon transfer board further includes: like Fig.18 and Fig.19 As shown, a dielectric layer and a second interconnect structure H2 are formed on a side of the interlayer dielectric layer away from the silicon substrate 1; wherein the conductive element 6 is electrically connected to the second interconnect structure H2, and the second interconnect structure H2 includes a second conductive line L2 and a second micro-convex structure T2, one end of the second conductive line L2 is electrically connected to the conductive element 6, and the other end of the second conductive line L2 is electrically connected to the second micro-convex structure T2, and the second micro-convex structure T2 is used to electrically connect the chip or substrate.

[0099] Reference Fig. 20 , temporarily bonding the logic wafer 50a with the above structure to the carrier wafer.

[0100] Reference Figure 21 to Figure 23 In some embodiments, during the preparation of the silicon adapter, a photoresist layer Pr is formed on the side of the mask layer 3 away from the silicon substrate 1 by using a photoresist technique, and a through hole is etched on the mask layer 3 and the silicon substrate 1 by using the photoresist layer Pr.

[0101] Reference Figure 23 to Figure 26 In some embodiments, in step S2, etching a through hole on the mask layer based on the first conductive member 100, etching the bottom of the through hole to the side of the first conductive member 100 close to the silicon substrate 1, comprises the steps of: A through hole is etched on the mask layer based on the first conductive member 100, and the bottom of the through hole is etched to the side of the interlayer dielectric layer close to the silicon substrate 1; then, a through hole is etched on the interlayer dielectric layer based on the first conductive member 100 to extend the length of the through hole until the bottom of the through hole is etched to the side of the first conductive member 100 close to the silicon substrate 1.

[0102] The present application etches the through hole from the back side of the silicon substrate 1 (that is, the side of the silicon substrate away from the interlayer dielectric layer), and first etches the through hole to the side of the interlayer dielectric layer close to the silicon substrate 1. At this time, the through hole only passes through the silicon substrate 1.

[0103] Furthermore, the through holes after etching are cleaned with a cleaning agent (eg, hydrofluoric acid and its diluted solution, organic acid cleaning agent).

[0104] Afterwards, the cleaned through hole is etched again to extend the length of the through hole, until the bottom of the through hole is etched to the side of the first conductive member 100 close to the silicon substrate.

[0105] In summary, in the embodiment of the present application, since the etching depth of the through hole (the depth is numerically the same as the through hole length) is deep, the etching intensity of the through hole is relatively large. 4 F 8 , SF 6 And other gases.

[0106] Since the etching gas may cause significant damage to the interlayer dielectric layer, etching the through hole first can prevent the etching gas from contacting the interlayer dielectric layer, thereby preventing the etching gas from damaging the interlayer dielectric layer.

[0107] In some embodiments, after the conductive material is filled in the through hole V1, the method for preparing the silicon adapter plate further includes: like Figure 27 to Figure 28 As shown, a third interconnection structure H3 is formed on the side of the mask layer 3 away from the silicon substrate 1; wherein the third interconnection structure H3 is electrically connected to the conductive material. The third interconnection structure H3 includes a third conductive line L3 and a third micro-convex structure T3, one end of the third conductive line L3 is electrically connected to the conductive material, and the other end of the third conductive line L3 is electrically connected to the third micro-convex structure T3, and the third micro-convex structure T3 is used to electrically connect the chip or substrate. Further, the material of the mask layer 3 includes SiO 2 .

[0108] like Figure 28 to Figure 29 As shown, the logic wafer 50 a and the carrier wafer 50 b are debonded.

[0109] In some embodiments, the orthographic projection of the first conductive member 100 on the first plane covers the orthographic projection of the through hole V1 on the first plane, and the orthographic projection of the third interconnect structure H3 on the first plane covers the orthographic projection of the through hole V1 on the first plane, wherein the first plane is a plane parallel to the silicon substrate 1. This arrangement helps to improve the conductivity of the conductive material 10 inside the through hole, so as to improve the electrical performance of the silicon adapter.

[0110] On the second aspect, the present application also provides a silicon adapter board, which includes a logic wafer 50a, a mask layer 3 and a through hole V1, wherein the wafer includes a silicon substrate 1 and an interlayer dielectric layer, the interlayer dielectric layer is arranged on the silicon substrate 1, and the dielectric constant of the interlayer dielectric layer is within a preset range, and a first conductive member 100 is arranged in the interlayer dielectric layer.

[0111] The mask layer 3 is arranged on a side of the silicon substrate 1 away from the interlayer dielectric layer.

[0112] The through hole V1 passes through the silicon substrate 1 , and the inside of the through hole V1 is filled with a conductive material 10 , wherein the conductive material 10 is electrically connected to the first conductive member 100 .

[0113] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a silicon adapter plate, characterized in that: include: Providing a wafer; wherein the wafer comprises a silicon substrate and an interlayer dielectric layer, the interlayer dielectric layer is arranged on the silicon substrate, and the dielectric constant of the interlayer dielectric layer is within a preset range, and a first conductive member is arranged in the interlayer dielectric layer; Depositing a mask layer on a side of the silicon substrate away from the interlayer dielectric layer, and etching a through hole on the mask layer based on the first conductive member, and etching the bottom of the through hole to a side of the first conductive member close to the silicon substrate; A conductive material is filled in the through hole, wherein the conductive material is electrically connected to the first conductive member.

2. The preparation method according to claim 1, characterized in that: The material of the mask layer includes SiO2; There are multiple interlayer dielectric layers, and the multiple interlayer dielectric layers are stacked on the silicon substrate; wherein the material of one of the two adjacent interlayer dielectric layers is SiO2; and the material of the other of the two adjacent interlayer dielectric layers is SiOCH.

3. The preparation method according to claim 2, characterized in that: The first conductive element is arranged in an interlayer dielectric layer close to the silicon substrate.

4. The preparation method according to claim 2, characterized in that: Based on the first conductive member etching a through hole on the mask layer, etching the bottom of the through hole to a side of the first conductive member close to the silicon substrate, comprising: Based on the first conductive member, a through hole is etched on the mask layer, and the bottom of the through hole is etched to a side of the interlayer dielectric layer close to the silicon substrate; A through hole is etched on the interlayer dielectric layer based on the first conductive member to extend the length of the through hole until the bottom of the through hole is etched to a side of the first conductive member close to the silicon substrate.

5. The preparation method according to any one of claims 1 to 4, characterized in that: The wafer provided comprises: Providing a logic wafer and a carrier wafer, wherein the logic wafer includes the silicon substrate and the interlayer dielectric layer; Bonding the logic wafer and the carrier wafer; The side of the silicon substrate away from the carrier wafer is thinned.

6. The preparation method according to claim 5, characterized in that: Before bonding the logic wafer and the carrier wafer, the preparation method further includes: A first interconnection structure is formed on a side of the interlayer dielectric layer away from the silicon substrate; wherein the first interconnection structure includes a first conductive wire and a first micro-convex structure, one end of the first conductive wire is electrically connected to the first conductive member, and the other end of the first conductive wire is electrically connected to the first micro-convex structure, and the first micro-convex structure is used to electrically connect a chip or a substrate.

7. The preparation method according to claim 5, characterized in that: The logic wafer further includes an active device, a fourth conductive line and a groove, wherein a portion of the active device is disposed in the silicon substrate, and another portion is disposed in the interlayer dielectric layer, one end of the fourth conductive line is electrically connected to the active device, the groove is disposed on a surface of the interlayer dielectric layer away from the silicon substrate, and the groove is filled with a conductive element, and the conductive element is electrically connected to the other end of the fourth conductive line, wherein before bonding the logic wafer and the carrier wafer, the preparation method further includes: A dielectric layer and a second interconnect structure are formed on a side of the interlayer dielectric layer away from the silicon substrate; wherein the conductive element is electrically connected to the second interconnect structure, and the second interconnect structure includes a second conductive wire and a second micro-convex structure, one end of the second conductive wire is electrically connected to the conductive element, and the other end of the second conductive wire is electrically connected to the second micro-convex structure, and the second micro-convex structure is used to electrically connect a chip or a substrate.

8. The preparation method according to claim 5, characterized in that: After the conductive material is filled in the through hole, the preparation method further comprises: A third interconnect structure is formed on a side of the mask layer away from the silicon substrate; wherein the third interconnect structure is electrically connected to the conductive material; the third interconnect structure comprises a third conductive wire and a third micro-convex structure, one end of the third conductive wire is electrically connected to the conductive material, the other end of the third conductive wire is electrically connected to the third micro-convex structure, and the third micro-convex structure is used to electrically connect a chip or a substrate; The logic wafer and the carrier wafer are debonded.

9. The preparation method according to claim 8, characterized in that: The orthographic projection of the first conductive member on the first plane covers the orthographic projection of the through hole on the first plane, and the orthographic projection of the third interconnect structure on the first plane covers the orthographic projection of the through hole on the first plane, wherein the first plane is a plane parallel to the silicon substrate.

10. A silicon adapter plate, characterized in that: include: A logic wafer, wherein the wafer comprises a silicon substrate and an interlayer dielectric layer, the interlayer dielectric layer is arranged on the silicon substrate, and the dielectric constant of the interlayer dielectric layer is within a preset range, and a first conductive member is arranged in the interlayer dielectric layer; A mask layer, wherein the mask layer is arranged on a side of the silicon substrate away from the interlayer dielectric layer; A through hole passes through the silicon substrate and is filled with a conductive material, wherein the conductive material is electrically connected to the first conductive member.

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