Packaging structure and manufacturing method thereof

By filling the epoxy underfill glue in the packaging structure of the BAW and FBAR filter chips, the problem of gold bumps rupture under the influence of external force is solved, and the stability and performance of the chip are improved.

CN119694986APending Publication Date: 2025-03-25SUZHOU JIEYANXIN NANO TECH CO LTD
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Patent Information

Application Number
CN202311234939.X
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2023-09-22
Publication Date
2025-03-25

AI Technical Summary

Technical Problem

The gold bumps of existing BAW and FBAR filter chips are prone to rupture under the influence of external forces, affecting chip performance.

Method used

By filling the epoxy underfill between the chip, substrate and gold bumps, and making the gold bumps using ultrasonic hot pressing process, and setting the epoxy resin film in combination with the vacuum coating process, the stability of the packaging structure is enhanced.

Benefits of technology

It significantly improves the stability of the gold bumps, reduces the risk of gold bumps rupture under the action of external forces, and thus improves the performance and service life of the chip.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention discloses a packaging structure and a manufacturing method thereof. The packaging structure comprises a chip, a bonding pad, a gold bump, a substrate, underfill and a plastic packaging layer. The chip comprises a chip body and a micro-electro-mechanical structure arranged on the surface of the chip body, the micro-electro-mechanical structure faces the substrate, and the surface of the micro-electro-mechanical structure is sleeved with a protective sleeve; bonding pads are arranged on one sides, close to the substrate, of the substrate and the chip body, and the substrate and the chip body are electrically connected through part of the bonding pads and the gold bumps; the underfill is filled among the chip, the substrate and the gold bumps; the plastic packaging layer is arranged on the substrate and wraps the chip. According to the packaging structure and the manufacturing method thereof provided by the invention, the situation that the performance of the filter chip is affected due to the fact that the gold bumps between the filter chip and the substrate are broken can be avoided.
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Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and more specifically, to a packaging structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of communication technology, from 2G to 5G, the communication frequency continues to increase, and the frequency bands are increasing. This puts forward more stringent technical requirements for RF front-end components such as filter chips, RF switches, and power amplifiers. For example, these components must have high reliability, excellent product performance, and short production cycles. Among them, BAW filter chips and FBAR filter chips in filter chips are widely used in the field of wireless communications due to their high Q values ​​and easy miniaturization.

[0003] In order to ensure the performance and service life of BAW and FBAR filter chips, they need to be packaged to prevent them from being affected by external environments such as chemical corrosion and air oxidation and causing failure. At present, the packaging of BAW and FBAR filter chips uses gold bump flip-chip technology to achieve electrical interconnection between the chip and the substrate. However, when there is an external force between the chip and the substrate, the gold bump will break, which will affect the performance of the filter chip.

[0004] Therefore, how to prevent the gold bumps between the filter chip and the substrate from breaking and thus affecting the performance of the filter chip becomes a technical problem that needs to be solved by those skilled in the art. Summary of the invention

[0005] The present application provides a packaging structure and a manufacturing method thereof, which can prevent the gold bumps between the filter chip and the substrate from breaking and thus affecting the performance of the filter chip.

[0006] In order to solve one or more of the above technical problems, the technical solution adopted in this application is:

[0007] The present application provides a packaging structure, which includes a chip, a pad, a gold bump, a substrate, an underfill, and a plastic sealing layer;

[0008] The chip comprises a chip body and a micro-electromechanical structure arranged on the surface of the chip body, the micro-electromechanical structure faces the substrate, and a protective cover is provided on the surface of the micro-electromechanical structure;

[0009] The substrate and the chip body are provided with pads on one side close to the substrate, and the substrate and the chip body are electrically interconnected through part of the pads and the gold bumps;

[0010] The underfill is filled between the chip, the substrate and the gold bumps;

[0011] The plastic packaging layer is arranged on the substrate and wraps the chip.

[0012] Furthermore, the pad includes a first pad, a second pad, a third pad and a fourth pad, one end of the first pad is connected to the chip body, the other end of the first pad is connected to the second pad, one end of the second pad is connected to the first pad, the other end of the second pad is connected to the gold bump, one end of the third pad is connected to the gold bump, the other end of the third pad is connected to a side of the substrate close to the chip, and the fourth pad is connected to a side of the substrate away from the chip.

[0013] Further, the material of the first pad is at least one of titanium or tungsten;

[0014] and / or,

[0015] The material of the second pad and the third pad is at least one of gold and aluminum.

[0016] Furthermore, the gold bump includes at least two spheres, the at least two spheres are bonded together, the sphere close to the chip body is connected to the second pad, and the sphere far from the chip body is connected to the third pad.

[0017] Furthermore, the substrate includes a substrate body and substrate interconnection wires and a multi-layer metal wiring layer arranged in the substrate body, the metal wiring layer is arranged between the substrate interconnection wires for connecting the substrate interconnection wires, and the substrate interconnection wires are respectively arranged between the third pad and the metal wiring layer adjacent to the third pad, between the fourth pad and the metal wiring layer adjacent to the fourth pad, and between adjacent metal wiring layers.

[0018] Furthermore, the substrate body includes at least one of a ceramic substrate, a resin substrate, and a silicon substrate.

[0019] Furthermore, the plastic sealing layer is an epoxy resin film, and the epoxy resin film is disposed on the substrate through a vacuum coating process.

[0020] Furthermore, the underfill is an epoxy underfill, and the epoxy underfill is filled between the chip, the substrate and the gold bumps through a capillary effect, and the void ratio of the epoxy underfill after filling is less than 0.5%.

[0021] Furthermore, the gold content of the gold bump is greater than 99.99%.

[0022] The present application also provides a method for manufacturing a packaging structure, the manufacturing method is used to prepare the above packaging structure, the manufacturing method comprises:

[0023] The pads are arranged on the substrate and on a side of the chip close to the substrate;

[0024] The substrate and the chip are electrically interconnected using gold bumps and part of the pads;

[0025] Filling the underfill between the chip, the substrate and the gold bumps;

[0026] A plastic packaging layer is disposed on the substrate and wraps the chip.

[0027] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0028] The present application provides a packaging structure and a manufacturing method thereof, which can greatly improve the stability of the gold bumps by filling the bottom filler between the chip, the substrate and the gold bumps and firmly integrate the chip, the substrate and the gold bumps into a whole, and reduce the stress on the gold bumps caused by the chip and the substrate being subjected to external forces, thereby reducing the gold bumps from breaking and affecting the performance of the chip.

[0029] Furthermore, the present application can utilize the ultrasonic hot pressing process of existing bonding equipment to complete the production of gold bumps on the substrate, which can reduce the process cycle and thus effectively reduce the production cost.

[0030] Furthermore, an epoxy resin film that wraps the chip is disposed on the substrate through a vacuum coating process. The epoxy resin film has the characteristics of high mechanical strength, waterproofness and corrosion resistance, and can avoid contamination of the core area of ​​the chip.

[0031] Of course, any product implementing the present application does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A side cross-sectional view of a packaging structure provided in an embodiment of the present application;

[0034] Figure 2 A top view of the packaging structure provided in an embodiment of the present application;

[0035] Figure 3 and Figure 4 A flow chart of a method for manufacturing a packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of the present application.

[0037] As described in the background technology, in order to ensure the performance and service life of BAW and FBAR filter chips, they need to be packaged to prevent them from being affected by external environments such as chemical corrosion and air oxidation and causing failure. At present, the packaging of BAW and FBAR filter chips uses gold bump flip-chip technology to achieve electrical interconnection between the chip and the substrate. However, when there is an external force between the chip and the substrate, the gold bump will break, thereby affecting the performance of the filter chip.

[0038] In this regard, the present application provides a packaging structure and a method for manufacturing the same. By filling the bottom filler between the chip, the substrate and the gold bumps and firmly integrating the chip, the substrate and the gold bumps into a whole, the stability of the gold bumps can be greatly improved, and the stress on the gold bumps caused by external forces on the chip and the substrate can be reduced, which may cause the gold bumps to break, thereby affecting the performance of the chip.

[0039] The following will be introduced through specific embodiments:

[0040] Embodiment 1

[0041] In view of the above problems, the present application creatively proposes a packaging structure, such as Figure 1 As shown, refer to Figure 2 The packaging structure includes a substrate 100, a pad 200, a gold bump 300, a chip 400, an underfill 500, and a plastic layer 600.

[0042] Specifically, the chip 400 includes a chip body 410 and a micro-electromechanical structure 420 arranged on the surface of the chip body 410, and the micro-electromechanical structure 420 faces the substrate 100. In order to prevent the micro-electromechanical structure 420 from being contaminated, a protective cover (not shown) is provided on the surface of the micro-electromechanical structure 420, and the protective cover here includes but is not limited to a silicon cap. A pad 200 is provided on the substrate 100 and the side of the chip body 410 close to the substrate 100, and the substrate 100 and the chip body 410 are electrically interconnected through part of the pad 200 and the gold bump 300. The present application can use the ultrasonic hot pressing process of the existing bonding equipment to complete the production of the gold bump 300 on part of the pad 200, which can reduce the process cycle, thereby effectively reducing the production cost. In addition, since gold has excellent ductility, strong antioxidant ability, high conductivity and other advantages, the final prepared packaging structure can be made with high reliability and excellent product performance.

[0043] Although the chip 400 is packaged using the gold bump 300 flip-chip technology to achieve electrical interconnection between the chip 400 and the substrate 100, when there is an external force between the chip 400 and the substrate 100, the gold bump 300 will be broken, thereby affecting the performance of the chip. In order to solve this problem, the embodiment of the present application fills the underfill 500 between the chip 400, the substrate 100 and the gold bump 300 and firmly integrates the chip 400, the substrate 100 and the gold bump 300 into a whole, which can greatly improve the stability of the gold bump 300, reduce the stress generated on the gold bump 300 when the chip 400 and the substrate 100 are subjected to external forces, and cause the gold bump 300 to break, thereby affecting the performance of the chip 400.

[0044] In order to avoid contamination of the core area of ​​the chip 400, a plastic encapsulation layer 600 is also provided on the substrate 100 to wrap the chip 400. The plastic encapsulation layer 600 can improve the strength and waterproof and dustproof performance of the entire packaging structure and avoid contamination of the core area of ​​the chip 400.

[0045] Embodiment 2

[0046] On the basis of the first embodiment, the structures of the pad 200 , the gold bump 300 and the substrate 100 are further refined in this embodiment.

[0047] The pad 200 includes a first pad 210, a second pad 220, a third pad 230 and a fourth pad 240, one end of the first pad 210 is connected to the chip body 410, the other end of the first pad 210 is connected to the second pad 220, one end of the second pad 220 is connected to the first pad 210, the other end of the second pad 220 is connected to the gold bump 300, one end of the third pad 230 is connected to the gold bump 300, the other end of the third pad 230 is connected to a side of the substrate 100 close to the chip 400, and the fourth pad 240 is connected to a side of the substrate 100 away from the chip 400. Among them, in order to facilitate the production of common gold with the gold bump 300, the material of the second pad 220 and the third pad 230 in contact with the gold bump 300 is at least one of gold or aluminum; the material of the first pad 210 is at least one of titanium or tungsten, because titanium or tungsten is harder and can play a certain supporting role, and titanium or tungsten and the chip body 410 have a strong bonding force; the material of the fourth pad 240 includes but is not limited to copper, silver, nickel, gold, aluminum and other metal materials with good conductivity, corrosion resistance and heat resistance.

[0048] The gold bumps 300 are arranged on the second pad 220 and the third pad 230 to realize the electrical interconnection between the chip 400 and the substrate 100. The gold bumps 300 in this embodiment are made of high-purity gold. Specifically, the gold content of the gold bumps 300 is greater than 99.99%. The gold bumps with a gold content greater than 99.99% have the advantages of high electrical conductivity, excellent thermal conductivity, corrosion resistance, good toughness, high chemical stability, etc. In order to prevent the bottom filler 500 from contacting the micro-electromechanical structure 420 on the surface of the chip body 410 and contaminating the micro-electromechanical structure 420, a protective cover is provided on the surface of the micro-electromechanical structure 420. Since the protective cover has a certain height, the distance between the chip body 410 and the substrate 100 increases, which requires the gold bump 300 to have a certain height. In this embodiment, the gold bump 300 includes at least two spheres, at least two spheres are bonded together, the sphere close to the chip body 410 is connected to the second pad 220, and the sphere away from the chip body 410 is connected to the third pad 230. In specific implementation, a gold wire with a gold content greater than 99.99% is bonded to the pad of the chip body 410 through a gold bump device to form a first sphere, and a gold wire with a gold content greater than 99.99% is used on the first sphere to form a second sphere through a gold bump device. The first sphere and the second sphere constitute a double-layer gold bump 300, the adhesive force of the gold bump 300 is greater than 30g, the diameter of the gold bump 300 is 60±5μm, the thickness of the gold bump 300 is 13±5μm, and the height of the gold bump 300 is 33±5μm. It should be noted that, depending on the actual process, the gold bump 300 may also be a multi-layer structure formed by multiple spheres, such as a three-layer gold bump, a four-layer gold bump, etc.

[0049] The substrate 100 includes a substrate body 110 and a substrate interconnection wire 120 and a multilayer metal wiring layer 130 arranged in the substrate body 110, wherein the metal wiring layer 130 is arranged between the substrate interconnection wires 120 for connecting the substrate interconnection wires 120, and the substrate interconnection wires 120 are respectively arranged between the third pad 230 and the metal wiring layer 130 adjacent to the third pad 230, between the fourth pad 240 and the metal wiring layer 130 adjacent to the fourth pad 240, and between adjacent metal wiring layers 130. The electrical interconnection between the third pad 230 and the fourth pad 240 can be achieved through the substrate interconnection wire 120 and the multilayer metal wiring layer 130, thereby achieving electrical interconnection between the chip 400 and the substrate 100. It should be noted here that the number of layers of the metal wiring layer 130 can be selected according to the specific design of the chip, and is not specifically limited here. The substrate body 110 can be a substrate body of various known materials, which is only used as an illustrative example, not a limitation on the scope of protection. The substrate body 110 includes at least one of a ceramic substrate, a resin substrate, and a silicon substrate.

[0050] For the undescribed parts in the second embodiment, please refer to the description of the aforementioned embodiment, which will not be repeated here.

[0051] Embodiment 3

[0052] On the basis of the first and second embodiments, this embodiment further refines the underfill 500 and the plastic encapsulation layer 600.

[0053] In this embodiment, the underfill 500 is preferably an epoxy underfill, which has the advantages of low fluidity, fast curing speed, and long service life. The epoxy underfill is filled between the chip 400, the substrate 100, and the gold bumps 300 and firmly integrates the chip 400, the substrate 100, and the gold bumps 300 into a whole, which can greatly improve the stability of the gold bumps 300 and reduce the stress on the gold bumps 300 when the chip 400 and the substrate 100 are subjected to external forces, which may cause the gold bumps 300 to break, thereby affecting the performance of the chip 400.

[0054] In a specific embodiment, the epoxy underfill is filled between the chip 400, the substrate 100 and the gold bump 300 by capillary effect. Since the capillary effect filling process is simple, the void rate is low, and the compatibility is better, it is widely used in practical applications. In the embodiment of the present application, the void rate of the epoxy underfill after filling is less than 0.5%.

[0055] The plastic sealing layer 600 is preferably an epoxy resin film, which has the characteristics of high mechanical strength, waterproofness and corrosion resistance, and can avoid contamination of the core area of ​​the chip 400. The epoxy resin film is plastic sealed by a vacuum lamination process. Of course, the epoxy resin film can also be laminated by other methods, such as heating the film layer and applying pressure to its surface so that the film layer is attached to the surface of the substrate 100 and the chip 400.

[0056] For the parts not described in detail in the third embodiment, please refer to the description of the aforementioned embodiment, which will not be repeated here.

[0057] Embodiment 4

[0058] On the basis of the first to third embodiments, this embodiment further provides a method for manufacturing a packaging structure, and the manufacturing method is used to prepare the above packaging structure. Figure 3 As shown, the manufacturing method comprises:

[0059] S1: Setting pads on a substrate and a side of a chip close to the substrate.

[0060] Specifically, a first pad 210 is disposed on the side of the chip body 410 close to the substrate 100 , a second pad 220 is disposed on the first pad 210 , a third pad 230 is disposed on the side of the substrate 100 close to the chip 400 , and a fourth pad 240 is disposed on the side of the substrate 100 away from the chip 400 .

[0061] S2: Using gold bumps and part of the pads to electrically interconnect the substrate and the chip.

[0062] Specifically, a gold wire with a gold content greater than 99.99% is first bonded to the second pad 220 through a gold bump device to form a first sphere, and then a gold wire with a gold content greater than 99.99% is used on the first sphere through a gold bump device to form a second sphere. The first sphere and the second sphere form a double-layer gold bump 300, the adhesion of the gold bump 300 is greater than 30g, the diameter of the gold bump 300 is 60±5μm, the thickness of the gold bump 300 is 13±5μm, and the height of the gold bump 300 is 33±5μm.

[0063] It should be noted here that before making the packaging structure, it is necessary to inspect the raw materials such as chips, substrates, gold wires, etc. to ensure that the quality of the raw materials meets the requirements.

[0064] S3: Filling the underfill between the chip, the substrate and the gold bumps.

[0065] In the embodiment of the present application, the underfill 500 is preferably an epoxy underfill, which is filled between the chip 400, the substrate 100 and the gold bump 300 by capillary effect, and finally cured by heating to complete the packaging. The void rate of the epoxy underfill after filling is less than 0.5%.

[0066] S4: placing a plastic packaging layer on the substrate and wrapping the chip.

[0067] In the embodiment of the present application, the plastic sealing layer 600 is preferably an epoxy resin film, which is covered on the substrate 100 and wraps the chip 400 through a vacuum coating process, and then the epoxy resin film is cured to make the epoxy resin film hard, thereby protecting the chip 400 from the influence of the external environment.

[0068] In a specific embodiment, Figure 4 As shown, the manufacturing method comprises:

[0069] 1) Chip incoming material inspection, substrate incoming material inspection

[0070] Before making the packaging structure, the BAW, FBAR filter chips and substrates are first inspected to ensure that the quality of the BAW, FBAR filter chips and substrates meets the requirements before packaging.

[0071] 2) Preparation of the first sphere of gold bump

[0072] The gold wire with a gold content greater than 99.99% is bonded to the pad of the BAW and FBAR filter chip through a gold bump device to form the first sphere.

[0073] 3) Preparation of the second sphere of the gold bump

[0074] A second sphere is formed on the first sphere by using a gold wire with a gold content greater than 99.99% through a gold bump device. The first sphere and the second sphere form a double-layer gold bump, the adhesion of the gold bump is greater than 30g, the diameter of the gold bump is 60±5μm, the thickness of the gold bump is 13±5μm, and the height of the gold bump is 33±5μm.

[0075] 4) Chip cutting

[0076] Use high-precision dicing equipment to singulate BAW and FBAR filter chips, separate the chips into single particles, and thus form single-particle chips. The process needs to meet the requirements that the chip edge collapse is less than 15μm and the cutting groove knife mark is 30±10μm.

[0077] 5) Chip cleaning, substrate cleaning

[0078] The BAW and FBAR filter chips and substrates are plasma cleaned to ensure the adhesion between the subsequent epoxy resin film and the substrate and chip, thereby improving the reliability of the package.

[0079] 6) Ultrasonic flip chip bonding

[0080] The BAW and FBAR filter chips are flipped onto the substrate using a high-precision ultrasonic hot-pressing flip-chip device, where the micro-electromechanical structure on the surface of the BAW and FBAR filter chips is inverted directly above the substrate, and the BAW and FBAR filter chips and the substrate are interconnected through gold bumps. After flipping, the interconnection strength between the chip and the substrate reaches: bonding force > 300g, the diameter of the gold bump ball meets 90±10μm, and the gap between the chip and the substrate meets 12±3μm.

[0081] 7) Epoxy base filler

[0082] The epoxy underfill is filled into the BAW, FBAR filter chip, substrate and between the gold bumps through the capillary effect.

[0083] 8) Vacuum coating and curing

[0084] The epoxy resin film is placed on the substrate through a vacuum coating process and wraps the chip, and then a curing operation is performed. The curing operation can make the epoxy resin film hard, thereby protecting the chip from the influence of the external environment.

[0085] 9) Substrate cutting

[0086] According to actual needs, the substrate is cut into multiple small devices by high-precision mechanical dicing equipment. After cutting, the cutting accuracy of the single particle size meets the tolerance of ±50μm.

[0087] 10) Laser marking

[0088] The small device prepared in step 9) is laser engraved to facilitate subsequent use and management. The laser engraving requirements are met, the characters are clearly visible, and the character depth is 5-20 μm.

[0089] 11) Functional testing

[0090] The laser-printed small device prepared in step 10) is subjected to functional testing, wherein the functional testing includes testing the device for in-band insertion loss, out-of-band suppression, isolation, bandwidth, standing wave ratio, etc.

[0091] 12) Sorting and packaging

[0092] The small devices that have passed the functional test in step 11) are packaged according to their types.

[0093] 13) Finished products are put into storage

[0094] The packaged devices are put into storage.

[0095] For the undescribed parts in the fourth embodiment, please refer to the description of the aforementioned embodiments, which will not be repeated here.

[0096] The above is a detailed introduction to a packaging structure and a manufacturing method thereof provided by the present application. The present invention is described in detail using specific examples. The above embodiments are only used to help understand the method and core idea of ​​the present invention. At the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

[0097] In the description of the present application, it should be understood that the terms "vertical", "parallel", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "multiple" means two or more.

[0098] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0099] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A packaging structure, characterized in that: The packaging structure includes a chip, a pad, a gold bump, a substrate, an underfill, and a plastic sealing layer; The chip comprises a chip body and a micro-electromechanical structure arranged on the surface of the chip body, the micro-electromechanical structure faces the substrate, and a protective cover is provided on the surface of the micro-electromechanical structure; The substrate and the chip body are provided with pads on one side close to the substrate, and the substrate and the chip body are electrically interconnected through part of the pads and the gold bumps; The underfill is filled between the chip, the substrate and the gold bumps; The plastic packaging layer is arranged on the substrate and wraps the chip.

2. The packaging structure according to claim 1, characterized in that: The pads include a first pad, a second pad, a third pad and a fourth pad, one end of the first pad is connected to the chip body, the other end of the first pad is connected to the second pad, one end of the second pad is connected to the first pad, the other end of the second pad is connected to the gold bump, one end of the third pad is connected to the gold bump, the other end of the third pad is connected to a side of the substrate close to the chip, and the fourth pad is connected to a side of the substrate away from the chip.

3. The packaging structure according to claim 2, characterized in that: The material of the first pad is at least one of titanium or tungsten; and / or, The material of the second pad and the third pad is at least one of gold and aluminum.

4. The packaging structure according to claim 2, characterized in that: The gold bump includes at least two spheres, which are bonded together, the sphere close to the chip body is connected to the second pad, and the sphere far from the chip body is connected to the third pad.

5. The packaging structure according to claim 1, characterized in that: The substrate includes a substrate body and substrate interconnection wires and a multi-layer metal wiring layer arranged in the substrate body. The metal wiring layer is arranged between the substrate interconnection wires for connecting the substrate interconnection wires. The substrate interconnection wires are respectively arranged between the third pad and the metal wiring layer adjacent to the third pad, between the fourth pad and the metal wiring layer adjacent to the fourth pad, and between adjacent metal wiring layers.

6. The packaging structure according to claim 5, characterized in that: The substrate body includes at least one of a ceramic substrate, a resin substrate, and a silicon substrate.

7. The packaging structure according to claim 1, characterized in that: The plastic sealing layer is an epoxy resin film, and the epoxy resin film is arranged on the substrate through a vacuum coating process.

8. The packaging structure according to claim 1, characterized in that: The underfill is epoxy underfill, which is filled between the chip, the substrate and the gold bumps through a capillary effect. The void ratio of the epoxy underfill after filling is less than 0.5%.

9. The packaging structure according to claim 1, characterized in that: The gold content of the gold bump is greater than 99.99%.

10. A method for manufacturing a packaging structure, characterized in that: The manufacturing method is used to prepare the packaging structure according to any one of claims 1 to 9, and the manufacturing method comprises: The pads are arranged on the substrate and on a side of the chip close to the substrate; The substrate and the chip are electrically interconnected using gold bumps and part of the pads; Filling the underfill between the chip, the substrate and the gold bumps; A plastic packaging layer is disposed on the substrate and wraps the chip.