Chip package

Abstract

The invention discloses a chip package, which comprises a substrate, at least one first circuit layer, at least one second circuit layer and at least one first metal layer, the substrate is provided with at least one blind hole penetrating through the substrate, and each blind hole is filled with each first metal layer to increase the conduction efficiency of electrical connection. The first surface of each first metal layer is a flat surface formed by grinding operation; wherein each first circuit layer is electrically connected with each second circuit layer through each first metal layer in each blind hole, and each first circuit layer enhances the conduction efficiency of electrical connection with each second circuit layer through each first metal layer; wherein each first metal layer is formed by filling each blind hole with at least one conductive adhesive; wherein each first metal layer is arranged in a groove of at least one conducting circuit in each blind hole.

Description

Technical Field

[0001] The invention relates to a chip package, and more particularly to a chip package in which a blind hole is filled with a metal layer to increase the conduction efficiency of electrical connection. Background Art

[0002] In order to electrically connect the circuit layers on two opposite surfaces of the substrate in the existing chip packaging, a through blind hole is generally provided on the substrate, and then a thin circuit layer (or conductive line) is electroplated on the inner wall of the blind hole, so that the circuit layers on the two opposite surfaces of the substrate can be electrically connected to each other through the thin circuit layer on the inner wall of the blind hole.

[0003] However, the thin circuit layer on the inner wall of the blind hole is formed by electroplating, which may cause holes (or unevenness) or incomplete forming of the thin circuit layer, thereby reducing the yield of the product. In addition, the conduction capacity of the thin circuit layer is also limited due to its small size, which is not conducive to the market competitiveness of the product.

[0004] Therefore, a chip package that can solve the problems of poor yield and limited conduction capability of thin-layer circuits on the inner wall surface of blind holes in existing chip packages is urgently expected by the relevant industries. Summary of the invention

[0005] The main purpose of the present invention is to provide a chip package, comprising a substrate, at least one first circuit layer, at least one second circuit layer and at least one first metal layer, wherein the substrate is provided with at least one blind hole penetrating the substrate, each blind hole is filled with each first metal layer to increase the conduction efficiency of the electrical connection, and the first surface of each first metal layer is a flat surface formed by grinding; wherein each first circuit layer is electrically connected to each second circuit layer through each first metal layer in each blind hole, and each first circuit layer is further enhanced in the conduction efficiency of the electrical connection with each second circuit layer through each first metal layer; wherein each first metal layer is formed after at least one conductive glue is filled in each blind hole; wherein each first metal layer is further provided in a groove of at least one conductive circuit in each blind hole, effectively solving the problem of poor yield and limited conduction capacity of thin-layer circuits on the inner wall surface of the blind hole in the existing chip package.

[0006] To achieve the above-mentioned purpose, the present invention provides a chip package, which includes a substrate, at least one first circuit layer, at least one second circuit layer, at least one chip, an insulating layer and at least one first metal layer; wherein the substrate has a first surface and an opposite second surface, and the substrate is provided with at least one blind hole penetrating the substrate; wherein each of the first circuit layers is provided on the first surface of the substrate, and each of the first circuit layers has a first surface; wherein each of the second circuit layers is provided on the second surface of the substrate; wherein each of the chips is electrically connectedly provided on the first surface of each of the first circuit layers, and each of the chips has a backside and an opposite connection surface, and the connection surface of each of the chips There are at least two crystal pads on the surface, each chip is electrically connected to each first circuit layer through each crystal pad; wherein the insulating layer is arranged on the substrate and covers each chip, and the insulating layer has a first surface; wherein each first metal layer is filled in each blind hole of the substrate to increase the conduction efficiency of the electrical connection, and the horizontal height of a first surface of each first metal layer is the same as the horizontal height of the first surface of each first circuit layer, wherein each first metal layer is formed by filling each blind hole of the substrate with at least one conductive glue, wherein the first surface of each first metal layer is a flat surface formed by grinding operation; wherein each first circuit layer is formed by each Each of the first metal layers in the blind hole is electrically connected to each of the second circuit layers, and each of the first circuit layers further enhances the conduction efficiency of the electrical connection with each of the second circuit layers through each of the first metal layers; wherein each of the chips is first electrically connected to the first surface of each of the first circuit layers, and then electrically connected to each of the second circuit layers through each of the first circuit layers, so that each of the chips can be electrically connected to the outside through each of the second circuit layers; wherein the manufacturing method of the chip package comprises the following steps: step S1: providing a substrate, wherein the substrate has a first surface and an opposite second surface, wherein at least one first circuit layer is arranged on the first surface of the substrate, and each of the first circuit layers has a first surface, wherein the At least one second circuit layer is arranged on the second surface of the substrate; step S2: drilling the substrate to form at least one blind hole on the substrate; step S3: filling each blind hole of the substrate with at least one conductive glue, and grinding each conductive glue to the same surface level as the first surface level of each first circuit layer by grinding, after the grinding operation is completed, each conductive glue in each blind hole of the substrate is formed into at least one first metal layer; step S4: arranging at least one chip on the first surface of each first circuit layer, wherein each chip has a back side and an opposite connection surface, and each chip has at least two pads on the connection surface;and step S5: disposing an insulating layer on the substrate and making the insulating layer cover each of the chips, thereby completing a chip package. ;

[0007] In a preferred embodiment of the present invention, each of the first metal layers is silver metal; wherein each of the conductive pastes formed into each of the first metal layers is silver paste.

[0008] In a preferred embodiment of the present invention, the insulating layer further has at least one opening, so that each opening of the insulating layer can allow the back of each chip to be exposed to the outside; wherein at least one second metal layer is further provided on the first surface of the insulating layer, and each of the second metal layers has a first surface and at least one opening, and each of the openings of each of the second metal layers is connected to each of the openings of the insulating layer, so that each of the openings of each of the second metal layers can allow the back of each chip to be exposed to the outside; wherein at least one third metal layer is further filled in each of the openings of the insulating layer and each of the openings of the second metal layers, each of the third metal layers covers the back of each chip, and the first surface level of each of the third metal layers is the same as the first surface level of each of the second metal layers.

[0009] In a preferred embodiment of the present invention, each of the second circuit layers further has a first surface; wherein the chip package also has at least one first outer protective layer and at least one second outer protective layer; wherein each of the first outer protective layers is disposed on the first surface of each of the second metal layers and the first surface of each of the third metal layers; wherein each of the second outer protective layers is disposed on the first surface of each of the second circuit layers, and each of the second outer protective layers has at least one opening, and each of the openings enables the first surface of each of the second circuit layers to be exposed to the outside.

[0010] The present invention also provides a chip package, which includes a substrate, at least one first circuit layer, at least one second circuit layer, at least one chip, an insulating layer and at least one first metal layer; wherein the substrate has a first surface and an opposite second surface, and the substrate is provided with at least one blind hole penetrating the substrate; wherein each of the first circuit layers is provided on the first surface of the substrate, and each of the first circuit layers has a first surface; wherein each of the second circuit layers is provided on the second surface of the substrate; wherein each of the chips is electrically connectedly provided on the first surface of each of the first circuit layers, and each of the chips has a back side and an opposite second surface. A connection surface, each chip has at least two crystal pads on the connection surface, each chip is electrically connected to each first circuit layer through each crystal pad; wherein the insulating layer is arranged on the substrate and covers each chip, and the insulating layer has a first surface; wherein each first metal layer is filled in each blind hole of the substrate to increase the conduction efficiency of the electrical connection, and the level of a first surface of each first metal layer is the same as the level of the first surface of each first circuit layer, wherein each first metal layer is formed by filling each blind hole of the substrate with at least one conductive glue, wherein the first surface of each first metal layer The flat surface is formed by grinding; each of the blind holes is also provided with a conducting circuit, each of the conducting circuit has a groove, each of the first metal layers is further provided in the groove of each of the conducting circuits in each of the blind holes, each of the first circuit layers is electrically connected to each of the second circuit layers through each of the first metal layers in each of the blind holes, and each of the first circuit layers further enhances the conduction efficiency of the electrical connection with each of the second circuit layers through each of the first metal layers; each of the chips is first electrically connected to the first surface of each of the first circuit layers, and then electrically connected to each of the second circuit layers through each of the first circuit layers, so that Each of the chips can be electrically connected to the outside through each of the second circuit layers; wherein the manufacturing method of the chip package comprises the following steps: step S1: providing a substrate, wherein the substrate has a first surface and an opposite second surface, wherein at least one first circuit layer is arranged on the first surface of the substrate, and each of the first circuit layers has a first surface, wherein at least one second circuit layer is arranged on the second surface of the substrate; step S2: drilling the substrate to form at least one blind hole on the substrate; step S3: performing electroplating in each of the blind holes of the substrate to form a conducting circuit in each of the blind holes, wherein each of the conducting circuits has a groove;Step S4: Fill the groove of each conductive line in each blind hole with at least one conductive glue, and grind each conductive glue to the same surface level as the first surface of each first circuit layer by grinding. After the grinding, each conductive glue in the groove of each conductive line is formed into at least one first metal layer; Step S5: Arrange at least one chip on the first surface of each first circuit layer, wherein each chip has a backside and a connecting surface opposite thereto, and each chip has at least two pads on the connecting surface; and Step S6: Arrange an insulating layer on the substrate and cover each chip with the insulating layer, thereby completing a chip package. ;

[0011] In a preferred embodiment of the present invention, each of the conductive pastes formed into each of the first metal layers is silver paste.

[0012] In a preferred embodiment of the present invention, the insulating layer further has at least one opening, so that each opening of the insulating layer can allow the back of each chip to be exposed to the outside; wherein at least one second metal layer is further provided on the first surface of the insulating layer, and each of the second metal layers has a first surface and at least one opening, and each of the openings of each of the second metal layers is connected to each of the openings of the insulating layer, so that each of the openings of each of the second metal layers can allow the back of each chip to be exposed to the outside; wherein at least one third metal layer is further filled in each of the openings of the insulating layer and each of the openings of the second metal layers, each of the third metal layers covers the back of each chip, and the first surface level of each of the third metal layers is the same as the first surface level of each of the second metal layers.

[0013] In a preferred embodiment of the present invention, each of the second circuit layers further has a first surface; wherein the chip package also has at least one first outer protective layer and at least one second outer protective layer; wherein each of the first outer protective layers is disposed on the first surface of each of the second metal layers and the first surface of each of the third metal layers; wherein each of the second outer protective layers is disposed on the first surface of each of the second circuit layers, and each of the second outer protective layers has at least one opening, and each of the openings enables the first surface of each of the second circuit layers to be exposed to the outside. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of a side cross-section of the first embodiment of the present invention.

[0015] Figure 2 It is a schematic side cross-sectional view of a blind hole filled with conductive glue according to the first embodiment of the present invention.

[0016] Figure 3 For the general Figure 2 Schematic diagram of grinding the conductive adhesive using grinding operation.

[0017] Figure 4 For Figure 3 Schematic diagram of arranging a chip on the first surface of the first circuit layer in FIG.

[0018] Figure 5 For Figure 4 Schematic diagram of providing an insulating layer on a substrate in FIG.

[0019] Figure 6 It is a schematic diagram of a side cross-section of a second embodiment of the present invention.

[0020] Figure 7 It is a schematic side cross-sectional view of a substrate according to the first embodiment of the present invention, in which a blind hole is formed by drilling operation.

[0021] Figure 8 For Figure 7 Schematic diagram of forming a conductive circuit in a blind hole in FIG.

[0022] Fig. 9 For Figure 8 Schematic diagram of filling the groove of the conductive line with conductive glue.

[0023] Fig.10 For the general Fig. 9 Schematic diagram of grinding the conductive adhesive using grinding operation.

[0024] Fig.11 For Fig.10 Schematic diagram of arranging a chip on the first surface of the first circuit layer in FIG.

[0025] Fig.12 For Fig.11 Schematic diagram of providing an insulating layer on a substrate in FIG.

[0026] Explanation of the accompanying drawings: 1-chip package; 10-substrate; 11-first surface; 12-second surface; 13-blind hole; 20-first circuit layer; 21-first surface; 30-second circuit layer; 40-chip; 41-crystal back; 42-connection surface; 43-crystal pad; 50-insulating layer; 51-first surface; 52-opening; 60-first metal layer; 60a-conductive glue; 61-first surface; 62-opening; 70-second metal layer; 71-first surface; 72-opening; 80-third metal layer; 81-first surface; 90-first outer protective layer; 100-second outer protective layer; 101-opening; 110-conductive line; 111-groove. DETAILED DESCRIPTION

[0027] The following content of the present invention provides many different embodiments or examples for implementing different features of the provided objectives. Of course, these are merely examples and are not intended to be limiting. In addition, in various examples, the present invention may repeat reference numbers and / or letters. This repetition is for the purpose of simplicity and clarity, and does not itself define the relationship between the various embodiments and / or configurations discussed.

[0028] With the help of illustrations, the structure and technical features of the present invention are described in detail as follows, wherein each illustration is only used to illustrate the structural relationship and related functions of the present invention, so the size of each element in each illustration is not drawn according to the actual scale and is not used to limit the present invention.

[0029] refer to Figure 1 and Figure 6 The present invention provides a chip package 1, which includes a substrate 10, at least a first circuit layer 20, at least a second circuit layer 30, at least a chip 40, an insulating layer 50 and at least a first metal layer 60.

[0030] The substrate 10 has a first surface 11 and an opposite second surface 12, and the substrate is provided with at least one blind hole 13 penetrating the substrate 10. Figure 1 and Figure 6 As shown, in a preferred embodiment of the chip package 1 of the present invention, the number of the blind holes 13 on the chip package 1 is 2, but it is not limited to Figure 1 shown.

[0031] Each first circuit layer 20 is disposed on the first surface 11 of the substrate 10. Each first circuit layer 20 has a first surface 21. Figure 1 and Figure 6 shown.

[0032] Each second circuit layer 30 is disposed on the second surface 12 of the substrate 10. Figure 1 and Figure 6 shown.

[0033] Each chip 40 is electrically connected and disposed on the first surface 21 of each first circuit layer 20. Each chip 40 has a backside 41 and an opposite connection surface 42. The connection surface 42 of each chip 40 has at least two pads 43. In a preferred embodiment of the chip package 1 of the present invention, the number of pads 43 on the chip package 1 is 2, but is not limited to Figure 1 As shown, each chip 40 is electrically connected to each first circuit layer 20 through each pad 43. Figure 1 and Figure 6 shown.

[0034] The insulating layer 50 is disposed on the substrate 10 and covers each chip 40. The insulating layer 50 has a first surface 51. Figure 1 and Figure 6 shown.

[0035] Each first metal layer 60 is filled in each blind hole 13 of the substrate 10 to increase the conduction efficiency of the electrical connection. Figure 1 and Figure 6 As shown; wherein each first metal layer 60 is silver metal but not limited; wherein each conductive glue 60a formed into each first metal layer 60 is silver glue but not limited as Figure 3 and Fig.10 shown.

[0036] refer to Figure 1 and Figure 6 The insulating layer 50 further has at least one opening 52 but is not limited, so that each opening 52 of the insulating layer 50 can allow the back 41 of each chip 40 to be exposed to the outside; wherein at least one second metal layer 70 is further provided on the first surface 51 of the insulating layer 50 but is not limited to increase the electromagnetic shielding effect, and each second metal layer 70 has a first surface 71 and at least one opening 72, and each opening 72 of each second metal layer 70 is connected to each opening 52 of the insulating layer 50, so that each second metal layer 70 is connected to each opening 52 of the insulating layer 50. Each opening 72 of the metal layer 70 can allow the back 41 of each chip 40 to be exposed to the outside; wherein each opening 52 of the insulating layer 50 and each opening 72 of each second metal layer 70 is further filled with at least one third metal layer 80 but not limited thereto, each third metal layer 80 covers the back 41 of each chip 40 to directly provide heat dissipation for each chip 40, and a first surface 81 of each third metal layer 80 has the same horizontal height as the first surface 71 of each second metal layer 70.

[0037] refer to Figure 5 and Fig.12 , each second circuit layer 30 further has a first surface 31 but is not limited; wherein the chip package 1 also has at least one first outer protective layer 90 and at least one second outer protective layer 100 but is not limited, which helps to increase the strength of the structure; wherein each first outer protective layer 90 is arranged on the first surface 71 of each second metal layer 70 and on the first surface 81 of each third metal layer 80; wherein each second outer protective layer 100 is arranged on the first surface 31 of each second circuit layer 30, and each second outer protective layer 100 has at least one opening 101, and each opening 101 can allow the first surface 31 of each second circuit layer 30 to be exposed to the outside.

[0038] refer to Figure 1 and Figure 6According to the structural differences of each first metal layer 60 after being formed inside each blind hole 13, the chip package 1 of the present invention can be further divided into a first embodiment (such as Figure 1 ) and the second embodiment (as shown Figure 6 The differences are as follows:

[0039] exist Figure 1 and Figure 5 The embodiment shown in is the first embodiment of the invention. In the first embodiment, the level of a first surface 61 of each first metal layer 60 is the same as the level of the first surface 21 of each first circuit layer 20; wherein each first metal layer 60 is formed by filling each blind hole 13 of the substrate 10 with at least one conductive glue 60a, as shown in FIG. Figure 3 wherein the first surface 61 of each first metal layer 60 is a flat surface formed by a grinding operation, such as Figure 3 shown.

[0040] Each first circuit layer 20 is electrically connected to each second circuit layer 30 through each first metal layer 60 in each blind hole 13, and each first circuit layer 20 further enhances the conduction efficiency of the electrical connection with each second circuit layer 30 through each first metal layer 60. Figure 1 and Figure 5 shown.

[0041] Each chip 40 is first electrically connected to the first surface 21 of each first circuit layer 20, and then electrically connected to each second circuit layer 30 through each first circuit layer 20, so that each chip 40 can be electrically connected to the outside through each second circuit layer 30, such as Figure 1 and Figure 5 shown.

[0042] In the first embodiment of the chip package 1 of the present invention (such as Figure 1 and Figure 5 The manufacturing method of the invention comprises the following steps:

[0043] Step S1: Provide a substrate 10, such as Figure 2 Wherein the substrate 10 has a first surface 11 and an opposite second surface 12, such as Figure 2 wherein the first surface 11 of the substrate 10 is provided with at least one first circuit layer 20, each first circuit layer 20 having a first surface 21, such as Figure 2 wherein the second surface 12 of the substrate 10 is provided with at least one second circuit layer 30, such as Figure 2 shown.

[0044] Step S2: drilling the substrate 10 to form at least one blind hole 13 on the substrate 10. Figure 2 shown.

[0045] Step S3: Fill each blind hole 13 of the substrate 10 with at least one conductive adhesive 60a. Figure 2 As shown, each conductive adhesive 60a is ground by grinding until the surface level is the same as the level of the first surface 21 of each first circuit layer 20, as shown in FIG. Figure 3 As shown, after the grinding operation is completed, each conductive glue 60a located in each blind hole 13 of the substrate 10 is formed into at least one first metal layer 60, as shown in FIG. Figure 3 shown.

[0046] Step S4: Dispose at least one chip 40 on the first surface 21 of each first circuit layer 20, such as Figure 4 wherein each chip 40 has a back side (Backside) 41 and a connection surface 42 opposite thereto, and each chip 40 has at least two pads 43 on the connection surface 42, such as Figure 4 shown.

[0047] Step S5: an insulating layer 50 is disposed on the substrate 10 so that the insulating layer 50 covers each chip 40, thereby completing a chip package 1. Figure 1 and Figure 5 shown.

[0048] The first embodiment of the present invention (such as Figure 1 and Figure 5 The manufacturing process shown in FIG. 1 can form each first metal layer 60 in each blind hole 13 of the chip package 1 without using an electroplating process, thereby helping to reduce the cost of the manufacturing end.

[0049] exist Figure 6 and Fig.12 The embodiment shown in FIG. 1 is a second embodiment of the invention. In the second embodiment, each first metal layer 60 is formed by filling each blind hole 13 of the substrate 10 with at least one conductive paste 60a. Fig.10 wherein the first surface 61 of each first metal layer 60 is a flat surface formed by a grinding operation, such as Fig.10 As shown; wherein each blind hole 13 is also provided with a conducting circuit 110, each conducting circuit 110 has a groove 111, such as Figure 8 wherein each first metal layer 60 is disposed in each blind hole 13 in each conductive line 110 of the groove 111, such as Fig.10 As shown; wherein each first circuit layer 20 is electrically connected to the second circuit layer 30 through each first metal layer 60 in each blind hole 13, and each first circuit layer 20 is further enhanced through each first metal layer 60 and the conduction efficiency of the electrical connection with each second circuit layer 30, such as Figure 6 and Fig.12 shown.

[0050] Each chip 40 is first electrically connected to the first surface 21 of each first circuit layer 20, and then electrically connected to each second circuit layer 30 through each first circuit layer 20, so that each chip 40 can be electrically connected to the outside through each second circuit layer 30, such as Figure 6 and Fig.12 shown.

[0051] In the second embodiment of the chip package 1 of the present invention (such as Figure 6 and Fig.12 The manufacturing method of the invention comprises the following steps:

[0052] Step S1: Provide a substrate 10, such as Figure 7 Wherein the substrate 10 has a first surface 11 and an opposite second surface 12, such as Figure 7 As shown; wherein the first surface 11 of the substrate 10 is provided with at least one first circuit layer 20, each first circuit layer 20 having a first surface 21; wherein the second surface 12 of the substrate 10 is provided with at least one second circuit layer 30, as Figure 7 shown.

[0053] Step S2: drilling the substrate 10 to form at least one blind hole 13 on the substrate 10. Figure 7 shown.

[0054] Step S3: Electroplating is performed in each blind hole 13 of the substrate 10 to form a conducting circuit 110 in each blind hole 13. Figure 8 As shown; wherein each conductive line 110 has a groove 111, such as Figure 8 shown.

[0055] Step S4: Fill the groove 111 of each conductive line 110 in each blind hole 13 with at least one conductive glue 60a. Fig. 9 As shown, each conductive adhesive 60a is ground by grinding until the surface level is the same as the level of the first surface 21 of each first circuit layer 20, as shown in FIG. Fig.10 As shown, after the grinding operation is completed, each conductive glue 60a located in the groove 111 of each conductive circuit 110 is formed into at least one first metal layer 60, as shown in FIG. Fig.10 shown.

[0056] Step S5: Dispose at least one chip 40 on the first surface 21 of each first circuit layer 20, such as Fig.11 wherein each chip 40 has a back side (Backside) 41 and a connection surface 42 opposite thereto, and each chip 40 has at least two pads 43 on the connection surface 42, such as Fig.11 shown.

[0057] Step S6: an insulating layer 50 is disposed on the substrate 10 and the insulating layer 50 covers each chip 40, thereby completing a chip package 1. Figure 6 and Fig.12 shown.

[0058] In summary, each blind hole 13 of the present invention is filled with each first metal layer 60 to increase the conduction efficiency of the electrical connection, and the first surface 61 of each first metal layer 60 is a flat surface formed by grinding. Figure 1 As shown; wherein each first circuit layer 20 is electrically connected to each second circuit layer 30 through each first metal layer 60 in each blind hole 13, and each first circuit layer 20 is further enhanced through each first metal layer 60 The conduction efficiency of the electrical connection with each second circuit layer 30 is, such as Figure 1 wherein each first metal layer 60 is formed by filling each blind hole 13 with conductive glue 60a, as shown in FIG. Figure 3 and Fig.10 As shown, the chip package 1 of the present invention has the following advantages compared with the existing chip package:

[0059] (1) Each first metal layer 60 of the present invention is formed by filling each blind hole 13 with each conductive adhesive 60a, which effectively solves the problem of poor yield of thin-layer circuits on the inner wall of the blind hole in the existing chip packaging due to pits (or unevenness) or incomplete molding during the copper electroplating process, thereby facilitating improving the yield and increasing the market competitiveness of the product.

[0060] (2) Each blind hole 13 of the present invention is filled with each first metal layer 60 to increase the conduction efficiency of the electrical connection, so that each first circuit layer 20 can enhance the conduction efficiency of the electrical connection with each second circuit layer 30 through each first metal layer 60, effectively solving the problem of limited conduction capacity due to the limited volume of the thin layer circuit on the inner wall of the blind hole in the existing chip packaging, thereby facilitating the improvement of conduction capacity and increasing the market competitiveness of the product.

[0061] The above description is only a preferred embodiment of the present invention, which is only illustrative rather than restrictive of the present invention. A person skilled in the art will understand that many changes, modifications, and even equivalent changes may be made to the present invention within the spirit and scope defined by the claims of the present invention, but all of these will fall within the scope of protection of the present invention.

Claims

1. A chip package, characterized in that: Include: A substrate having a first surface and an opposite second surface, and the substrate is provided with at least one blind hole penetrating the substrate; At least one first circuit layer, each of the first circuit layers is disposed on the first surface of the substrate, and each of the first circuit layers has a first surface; At least one second circuit layer, each of the second circuit layers is disposed on the second surface of the substrate; At least one chip, each of the chips is electrically connected and disposed on the first surface of each of the first circuit layers, each of the chips has a back surface and an opposite connection surface, each of the chips has at least two pads on the connection surface, and each of the chips is electrically connected to each of the first circuit layers through each of the pads; an insulating layer, the insulating layer being disposed on the substrate and covering each of the chips, the insulating layer having a first surface; and At least one first metal layer, each of the first metal layers is filled in each of the blind holes of the substrate to increase the conduction efficiency of the electrical connection, and the level of a first surface of each of the first metal layers is the same as the level of the first surface of each of the first circuit layers; wherein each of the first metal layers is formed by filling each of the blind holes of the substrate with at least one conductive paste; wherein the first surface of each of the first metal layers is a flat surface formed by grinding; Each of the first circuit layers is electrically connected to each of the second circuit layers through each of the first metal layers in each of the blind holes, and each of the first circuit layers further enhances the conduction efficiency of the electrical connection with each of the second circuit layers through each of the first metal layers; Each of the chips is first electrically connected to the first surface of each of the first circuit layers, and then electrically connected to each of the second circuit layers through each of the first circuit layers, so that each of the chips can be electrically connected to the outside through each of the second circuit layers; The manufacturing method of the chip package comprises the following steps: Step S1: providing a substrate; wherein the substrate has a first surface and an opposite second surface; wherein at least one first circuit layer is disposed on the first surface of the substrate, and each of the first circuit layers has a first surface; wherein at least one second circuit layer is disposed on the second surface of the substrate; Step S2: performing a drilling operation on the substrate to form at least one blind hole on the substrate; Step S3: Filling each of the blind holes of the substrate with at least one conductive paste, and grinding each of the conductive pastes to a surface level that is the same as the level of the first surface of each of the first circuit layers by grinding. After the grinding operation is completed, each of the conductive pastes in each of the blind holes of the substrate is formed into at least one first metal layer; Step S4: disposing at least one chip on the first surface of each of the first circuit layers; wherein each of the chips has a back surface and an opposite connection surface, and each of the chips has at least two pads on the connection surface; and Step S5: disposing an insulating layer on the substrate and making the insulating layer cover each of the chips, thereby completing a chip package.

2. The chip package according to claim 1, characterized in that: Each of the first metal layers is silver metal; Each of the conductive pastes formed into each of the first metal layers is silver paste.

3. The chip package according to claim 1, characterized in that: The insulating layer further has at least one opening, so that each opening of the insulating layer can allow the back of each chip to be exposed to the outside; wherein at least one second metal layer is further provided on the first surface of the insulating layer, and each of the second metal layers has a first surface and at least one opening, and each of the openings of each of the second metal layers is connected to each of the openings of the insulating layer, so that each of the openings of each of the second metal layers can allow the back of each chip to be exposed to the outside; wherein at least one third metal layer is further filled in each of the openings of the insulating layer and each of the openings of each of the second metal layers, each of the third metal layers covers the back of each chip, and the first surface level of each of the third metal layers is the same as the first surface level of each of the second metal layers.

4. The chip package according to claim 3, characterized in that: Each of the second circuit layers further has a first surface; wherein the chip package also has at least one first outer protective layer and at least one second outer protective layer; wherein each of the first outer protective layers is arranged on the first surface of each of the second metal layers and the first surface of each of the third metal layers; wherein each of the second outer protective layers is arranged on the first surface of each of the second circuit layers, and each of the second outer protective layers has at least one opening, and each of the openings can allow the first surface of each of the second circuit layers to be exposed to the outside.

5. A chip package, characterized in that: Include: A substrate having a first surface and an opposite second surface, and the substrate is provided with at least one blind hole penetrating the substrate; At least one first circuit layer, each of the first circuit layers is disposed on the first surface of the substrate, and each of the first circuit layers has a first surface; At least one second circuit layer, each of the second circuit layers is disposed on the second surface of the substrate; At least one chip, each of the chips is electrically connected and disposed on the first surface of each of the first circuit layers, each of the chips has a back surface and an opposite connection surface, each of the chips has at least two pads on the connection surface, and each of the chips is electrically connected to each of the first circuit layers through each of the pads; an insulating layer, the insulating layer being disposed on the substrate and covering each of the chips, the insulating layer having a first surface; and At least one first metal layer, each of the first metal layers is filled in each of the blind holes of the substrate to increase the conduction efficiency of the electrical connection, and the level of a first surface of each of the first metal layers is the same as the level of the first surface of each of the first circuit layers; wherein each of the first metal layers is formed by filling each of the blind holes of the substrate with at least one conductive paste; wherein the first surface of each of the first metal layers is a flat surface formed by grinding; Each of the blind holes is provided with a conducting circuit, and each of the conducting circuits has a groove; each of the first metal layers is further provided in the groove of each of the conducting circuits in each of the blind holes; each of the first circuit layers is electrically connected to each of the second circuit layers through each of the first metal layers in each of the blind holes, and each of the first circuit layers further enhances the conduction efficiency of the electrical connection with each of the second circuit layers through each of the first metal layers; Each of the chips is first electrically connected to the first surface of each of the first circuit layers, and then electrically connected to each of the second circuit layers through each of the first circuit layers, so that each of the chips can be electrically connected to the outside through each of the second circuit layers; The manufacturing method of the chip package comprises the following steps: Step S1: providing a substrate; wherein the substrate has a first surface and an opposite second surface; wherein at least one first circuit layer is disposed on the first surface of the substrate, and each of the first circuit layers has a first surface; wherein at least one second circuit layer is disposed on the second surface of the substrate; Step S2: performing a drilling operation on the substrate to form at least one blind hole on the substrate; Step S3: performing electroplating in each of the blind holes of the substrate to form a conducting circuit in each of the blind holes; Each of the conducting circuits has a groove; Step S4: Filling the groove of each of the conducting circuits in each of the blind holes with at least one conductive glue, and grinding each of the conductive glue until the surface level is the same as the level of the first surface of each of the first circuit layers by grinding. After the grinding operation is completed, each of the conductive glues in the groove of each of the conducting circuits is formed into at least one first metal layer; Step S5: disposing at least one chip on the first surface of each of the first circuit layers; wherein each of the chips has a back surface and an opposite connection surface, and each of the chips has at least two pads on the connection surface; and Step S6: disposing an insulating layer on the substrate and making the insulating layer cover each of the chips, thereby completing a chip package.

6. The chip package according to claim 5, characterized in that: Each of the conductive pastes formed into each of the first metal layers is silver paste.

7. The chip package according to claim 5, characterized in that: The insulating layer further has at least one opening, so that each opening of the insulating layer can allow the back of each chip to be exposed to the outside; wherein at least one second metal layer is further provided on the first surface of the insulating layer, and each of the second metal layers has a first surface and at least one opening, and each of the openings of each of the second metal layers is connected to each of the openings of the insulating layer, so that each of the openings of each of the second metal layers can allow the back of each chip to be exposed to the outside; wherein at least one third metal layer is further filled in each of the openings of the insulating layer and each of the openings of each of the second metal layers, each of the third metal layers covers the back of each chip, and the first surface level of each of the third metal layers is the same as the first surface level of each of the second metal layers.

8. The chip package according to claim 7, characterized in that: Each of the second circuit layers further has a first surface; wherein the chip package also has at least one first outer protective layer and at least one second outer protective layer; wherein each of the first outer protective layers is arranged on the first surface of each of the second metal layers and the first surface of each of the third metal layers; wherein each of the second outer protective layers is arranged on the first surface of each of the second circuit layers, and each of the second outer protective layers has at least one opening, and each of the openings can allow the first surface of each of the second circuit layers to be exposed to the outside.

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